Nick:
That was my first approach, but I can’t even fit two DDCs in the E310 FPGA.
Royce
> On Aug 8, 2019, at 1:36 PM, Nick Foster wrote:
>
> Nevermind, I just saw you're doing it in an E310. Reading is fundamental.
>
> You might consider splitting the problem into a pair of DDCs instead.
>
>
Last ditch, does your application permit aliasing? I.e., do you need to be
able to receive all four channels simultaneously? It would be
computationally cheap to sample at 5Msps and alias to 1Msps, then filter in
the CPU. You'd have to rotate two of the carriers down to baseband but the
sample rate
Nevermind, I just saw you're doing it in an E310. Reading is fundamental.
You might consider splitting the problem into a pair of DDCs instead.
Nick
On Thu, Aug 8, 2019 at 11:35 AM Nick Foster wrote:
> Royce,
>
> Is there a reason you absolutely need it to be done in RFNoC? This is only
> 5MHz
Royce,
Is there a reason you absolutely need it to be done in RFNoC? This is only
5MHz of bandwidth, and any commodity PC should be able to handle
channelizing it in software.
Nick
On Thu, Aug 8, 2019 at 11:19 AM Royce Connerley via USRP-users <
usrp-users@lists.ettus.com> wrote:
> EJ:
>
> I’m
EJ:
I’m currently wanting to receive a total of four channels that are 12.5 kHz
wide. The channels are not equally spaced.
F2 = F1 + 1 MHz
F3 = F1 + 3.99375 MHz
F4 = F3 + 1 MHz
For this type of system, I typically have a number of channel pairs (repeater
output and input separated by 1 MHz) t
Hi Royce,
Can you walk me through your use case real quick?
- How many channels?
- How wide is each channel?
- Are the channels equally spaced?
The polyphase channelizer in theseus-cores currently has a static number of
"max channels" that get instantiated which is not insignificant. We've
d
EJ:
I want to pick a few narrowband channels scattered over about 5 MHz. I would
like to be able to use your channelizer in an E310. Do you think it could fit
in the E310’s FPGA? When I run uhd_image_builder with just the channelizer and
a FIFO, I’m seeing the following errors:
ERROR: [Plac
Very cool! Feel free to reach out if you have any questions or issues.
Right now it's set up as a M/2 channelizer, and the output rate is 2x input
rate. All the channels come out interleaved and have to be deinterleave in
software (you'll see in the example flowgraph).
Cheers,
EJ
On Thu, Jul 25,
I'll test! Forgot about this one and now have a very good use case for it.
I'll let you know how it goes.
On Wed, Jul 24, 2019 at 4:35 PM EJ Kreinar via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Hi Royce,
>
> Phil and I have been working on the channelizer in the theseus-cores repo
> here
Hi Royce,
Phil and I have been working on the channelizer in the theseus-cores repo
here: gitlab.com/theseus-cores/theseus-cores
The master branch has a (potentially) working channelizer, at least
according to my recent tests on the x310, as long as the network interface
supports the desired outp
At the 2018 GRCon, EJ Kreinar spoke about improvements to the RFNoC polyphase
channelizer. Has there been any activity on this?
Royce Connerley
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