[USRP-users] E320 GNUradio question

Hi, In the flow-graphs that use RFNOC blocks for E320 devices, is GRC installed on the Zynq processor on the SOC or a separate PC/host? Thanks Chintan ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-us

Re: [USRP-users] How to debug timed commands on FPGA side?

Lukas, There are two broad approaches to debug FPGAs, including the B210: 1. Instantiate chipscope/ILA in the Xilinx tool, and use JTAG to monitor signals. 2. Instrument the code, with debug signals (for e.g, a counter that increments when the fault condition happens) and connect the debug signa

[USRP-users] 9361 Sample Rate question

Hi, On the B210 devices which use the AD9361, what is the granularity on the sample rate supported? I know the max sample rate is 61.44MHz, and that the BBPLL that drives the ADC sample clock allows for a varying rates, but I am trying to find what are the values that are actually supported. In ot

[USRP-users] VITA time question

Hi, A conceptual question: for the b205 mini, how does the FPGA get the 64-bit VITA timefield? I know the PPS/10 MHz can be used to sync the clocks to, but trying to understand how the timestamp is synchronized to a UTC/known-good reference value. Reading the HDL, it seems that the timestamp is pr

Re: [USRP-users] Software changes for new FPGA registers B205

plate. Thanks Chintan On Tue, Sep 4, 2018 at 1:15 PM Martin Braun wrote: > On 09/03/2018 08:21 PM, Chintan Patel via USRP-users wrote: > > Hello, > > > > I have defined a new readback register in the FPGA in the b205_core > > file, adjacent to the lock state regi

Re: [USRP-users] Software changes for new FPGA registers B205

as a template. Thanks Chintan On Tue, Sep 4, 2018 at 1:15 PM Martin Braun wrote: > On 09/03/2018 08:21 PM, Chintan Patel via USRP-users wrote: > > Hello, > > > > I have defined a new readback register in the FPGA in the b205_core > > file, adjacent to the lock state regi

Re: [USRP-users] Rssi reading on b205/b210

ou should be able to read it using the usual sensor read-back mechanism > (look at get_rx_senor_names and get_rx_sensor()) > > Cheers, > Julian > > > On 21. Sep 2018, at 17:04, Chintan Patel via USRP-users < > usrp-users@lists.ettus.com> wrote: > > > > Hi, &

[USRP-users] Rssi reading on b205/b210

Hi, Is there a function/script in the uhd driver to read the rssi for the b205/b210? Thanks ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

[USRP-users] X310 general Question

Hello, Some high-level questions on the X310 architecture and implementation related to the GigE/PCIe support. The X310 allows host connectivity using 10G or PCIe connections. Is it implied that if the Ethernet interfaces are being used to connect to the host, the PCIe is not being used? In the F

[USRP-users] X310 schematic

I was looking at the X310 schematic to understand the PCIe circuitry, and it seems that the schematic is missing pages which presumably had the PCIe circuitry. Is this intentionall? Chintan ___ USRP-users mailing list USRP-users@lists.ettus.com http://li

[USRP-users] PCI-e bandwidth on X310

Hi, What is a realistic achievable capacity on the PCI-e(x4) link on the X310? The NI PXI brochure claims a 832MBytes/s rate, but not sure what has been achieved in practice. Trying to figure out how what sample rate will be supported for a 4-channel RX radio configuration. Thanks Chintan ___

Re: [USRP-users] B210 two channel capacity

1x1 mode, the maximum sampling rate is 61.44 Msps, > and in 2x2 mode, the maximum sampling rate is 30.72 Msps. > > The tweak/modification that you mention has not been implemented for the > B210. > > --Neel Pandeya > > > > > On 9 September 2018 at 13:20, C

Re: [USRP-users] B210 two channel capacity

ers@lists.ettus.com> wrote: > On 09/09/2018 11:21 AM, Chintan Patel via USRP-users wrote: > > Hi, > > > > Two questions on the B210. > > > > 1. Generally speaking, are there are known issues transporting two RX > > channels at 61.44Msps over USB 3.0 on the B210. I know

[USRP-users] B210 two channel capacity

Hi, Two questions on the B210. 1. Generally speaking, are there are known issues transporting two RX channels at 61.44Msps over USB 3.0 on the B210. I know from a theoretical standpoint, the 5Gbps capacity of USB 3.0 has enough capacity to transport the dual-channel 16-bits i/q @ 61.44Msps. I als

[USRP-users] N310 Question

Hi, Given that the N310 has the Zynq parts (like the E310), has there been any benchmark testing done to test the PS-PL data transfer bandwidth? For the E310, it has been said that the data transfer bandwidth from the FPGA fabric to the processor is limited to the 15-20Msps (due to DMA/driver bott

[USRP-users] Software changes for new FPGA registers B205

Hello, I have defined a new readback register in the FPGA in the b205_core file, adjacent to the lock state register. What is the least invasive function call/method in the UHD driver/software to be able to read this newly defined register? Thanks C ___

Re: [USRP-users] B205mini debug register

Any thoughts on the above? Hello, Is there a non-invasive way to monitor a debug register in the b205mini FPGA, with minimal/no changes to software. To give some background, I am looking at making some changes to the B205 mini HDL and trying to see if I can use an existing debug/unused register

[USRP-users] B205mini debug register

Hello, Is there a non-invasive way to monitor a debug register in the b205mini FPGA, with minimal/no changes to software. To give some background, I am looking at making some changes to the B205 mini HDL and trying to see if I can use an existing debug/unused register for debug purposes. I am try

Re: [USRP-users] Synchronizing multiple B205 mini radios

B200mini clocking circuitry is on p. 4 of the schematic. The PLL is >>> digital and implemented inside the FPGA. >>> >>> There is a divide-by-2 for the external LO input in the AD9361/AD9364 >>> RFIC that can result in a 180 degree phase ambiguity. More details here >>

Re: [USRP-users] Synchronizing multiple B205 mini radios

re details here >> provided by my former colleague at ADI also named Robin: >> https://ez.analog.com/thread/73543?commentID=225150#comment-225150 >> >> >> -Robin >> >> >> On Mon, Jun 25, 2018 at 9:07 PM, Marcus D. Leech via USRP-users < >>

Re: [USRP-users] Synchronizing multiple B205 mini radios

73543?commentID=225150#comment-225150 > > > -Robin > > > On Mon, Jun 25, 2018 at 9:07 PM, Marcus D. Leech via USRP-users < > usrp-users@lists.ettus.com> wrote: > >> On 06/25/2018 11:57 PM, Dan CaJacob wrote: >> >> Without looking at the schematic, I&#x

Re: [USRP-users] Synchronizing multiple B205 mini radios

ly available. > > > > > > Thanks > Chintan > > On Sat, Jun 23, 2018 at 1:07 AM, Marcus D. Leech via USRP-users < > usrp-users@lists.ettus.com> wrote: > >> On 06/23/2018 12:25 AM, Chintan Patel via USRP-users wrote: >> >>> Hello, >>> >

[USRP-users] Synchronizing multiple B205 mini radios

Hello, I am an Ettus newbie. We have an application that requires us to synchronize multiple B205 mini radios (RX side) using the PPS in signal. In the FPGA, the pps_in is reclocked into the radio clock domain. What we notice is that when we monitor this PPS signal (reclocked in radio clock domain