[USRP-users] Re: X310 calibration

2022-09-30 Thread Avila, Jose A
SRP-users Digest, Vol 145, Issue 55 To: usrp-users@lists.ettus.com Message-ID: Content-Type: multipart/alternative; boundary="----gvkvlFFcHe0JJA1MHesKFzhB" On 2022-09-27 09:01, Avila, Jose A wrote: > Using the UBX board on the x310 and the lo leakage is the same > amplitude if

[USRP-users] Re: USRP-users Digest, Vol 145, Issue 55

2022-09-27 Thread Avila, Jose A
naging the list at usrp-users-ow...@lists.ettus.com When replying, please edit your Subject line so it is more specific than "Re: Contents of USRP-users digest..." Today's Topics: 1. X310 calibration (Avila, Jose A) 2. Re: X310 cal

[USRP-users] X310 calibration

2022-09-23 Thread Avila, Jose A
I have noticeable lo leakage when running the cpp rfnoc replay samples from file. So I ran the calibration functions but it doesn't seem to be using the created files since I did not notice a difference. Is there a function call or setting in cpp I need to add? I thought it would be automatic. U

[USRP-users] Companion issue

2022-09-13 Thread Avila, Jose A
Im trying to downgrade from gnuradio 3.9 to 3.8 both from source. I installed 3.8 and deleted as much as I found of 3.9. When I check gnuradio-config-info --version it shows the right 3.8 version. However when I run gnuradio-companion it tries to grab version 3.9 and errors out trying to find l

[USRP-users] 4 channels tx on N310

2018-09-11 Thread Avila, Jose A via USRP-users
Hello, We are trying to transmit out of the N310 with 4 channels simultaneously, with the attached flowgraph we got it to transmit by using 2 rfnoc:radio blocks with 2 channels each but we can't seem to find where to change the center frequency of the 2nd channel of the rfnoc: radio block. T

[USRP-users] N310 FPGA image mismatch with UHD

2018-08-30 Thread Avila, Jose A via USRP-users
Hello, I created an image for the N310 with the fpga master branch commit 615d9b8eeb94ee2d19c3b1e7aa526d4999495e05. I have UHD installed master branch commit 3b42e6f029f0d3de0f54d720964357aa0a32986f. When I go to probe the N310 I get the following error [ERROR] [0/DmaFIFO_0] Major compat n

Re: [USRP-users] RFNoC OOT Module Error with FPGA Image

2017-11-30 Thread Avila, Jose A via USRP-users
This fixed the issue thank you. From: John Medrano Sent: Thursday, November 30, 1:09 PM Subject: Re: [USRP-users] RFNoC OOT Module Error with FPGA Image To: Avila, Jose A Cc: usrp-users@lists.ettus.com Hello Jose, Based on the information you have posted I suspect it is an error in you

[USRP-users] RFNoC OOT Module Error with FPGA Image

2017-11-28 Thread Avila, Jose A via USRP-users
Hello we are getting the following error when probing the FPGA in X310 after installing the created bit file. Error:Runtime error: Cannot get() on an uninitialized (empty) property. The testbench runs successfully but after creating the bit file and uploading it into the SDR we get the error

Re: [USRP-users] Error creating RFNoC FPGA image with OOT module

2017-10-05 Thread Avila, Jose A via USRP-users
Editing the python file and pointing to the top OOT directory fixed the issue thank you. From: EJ Kreinar Sent: Wednesday, October 4, 2017 5:19:55 PM To: Nicolas Cuervo Cc: Avila, Jose A; usrp-users@lists.ettus.com Subject: Re: [USRP-users] Error creating

Re: [USRP-users] Error in RFNoC grc with OOT module

2017-10-05 Thread Avila, Jose A via USRP-users
: Avila, Jose A Cc: usrp-users@lists.ettus.com Subject: Re: [USRP-users] Error in RFNoC grc with OOT module Hello Jose, this might be an indentation problem at the XML that is located at your_oot/grc/your_block.xml. Do you mind sharing with us that file? Also, I remember seeing this error in earlier

[USRP-users] Error in RFNoC grc with OOT module

2017-10-04 Thread Avila, Jose A via USRP-users
Hello we are developing an OOT module following the tutorial, but similar to siggen, but are currently encountering an error that comes up with ./testtwochannel.py The error that comes up is the following File "./testtwochannel.py", line 97 self.siggen2ch_twochannelsiggen_0 = Template er

[USRP-users] Error creating RFNoC FPGA image with OOT module

2017-10-03 Thread Avila, Jose A via USRP-users
We are currently getting an error attempting to build a fpga image when running the following which points to the OOT module using the -I option ./uhd_image_builder.py twochannelsiggen duc fft -I /home/joseavila/Documents/gnuradio_source/rfnoc-siggen2ch/rfnoc/fpga-src/ -d x310 -t X310_RFNOC_H