I'm trying to take what I learned from GRCon2019 from Neel and company's
workshop, and I'm trying to perform the uhd_image_builder_gui.py script. It
fails with a message similar to:
[00:12:22] Starting DRC Task
ERROR: [DRC MDRV-1] Multiple Driver Nets: Net bus_clk_gen/inst/CLK_OUT4 has
multipl
Fabian,
thanks for the suggestion I will try the solution
Daniel, I am using the CDA-2990 device from national instruments
Marcus, Some feedbacks,
- what daughtercards are you using in your X310?
+==> the UBX 10-6000 MHz Rx/Tx (160 MHz)
- what do you mean by "hardware block" -- RFNo
Hello Jason:
My apologies for the delay. We were super busy with GNU Radio Conference.
Thanks for providing a stand-alone test program. I'll try to reproduce this
issue later today or tomorrow, and I'll get back to you with an update.
--Neel Pandeya
On Tue, 3 Sep 2019 at 10:20, Jason Roehm wr
It is a self build device using a 74LS125D as buffer. The level is 3.3V
digital.
As there were no specifications around for the required input levels at
the time we needed the device, we just measured the levels coming from
the 1PPS output and replicated them.
Am 26.09.2019 um 13:51 schrieb Da
Hi
> When I plug in the B205 and go to run it for the first time, it takes a
> minute or more to download the stock fpga image to the unit. From that point
> forward, each subsequent run it doesn't have to download the FPGA image. But
> when I disconnect it from USB and re-connect, it must be
When I plug in the B205 and go to run it for the first time, it takes a
minute or more to download the stock fpga image to the unit. From that
point forward, each subsequent run it doesn't have to download the FPGA
image. But when I disconnect it from USB and re-connect, it must be
downloaded aga
Hi Fabian, Cherif,
What is the external PPS device you are using?
-Daniel
On Thu, Sep 26, 2019 at 9:18 AM Fabian Schwartau via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Hi,
> I have very similar problem with X310. I am running a C++ application,
> so I have a bit more flexibility I gues
Hi,
I have very similar problem with X310. I am running a C++ application,
so I have a bit more flexibility I guess. After I do the
set_time_unknown_pps to sync to the 1PPS signal, I run the function
get_time_last_pps and it sometimes has an offset of 10ns (it was 5ns for
an old firmware due t
