Re: [USRP-users] X310 Register's Memory Capability

Hi Steve, As an addon to Jonathon's email, you haven't actually said that you want to store filter taps. If you are storing generic data then the embedded regs are unlikely to be helpful for you because you are not going to be using the data with DSP48s. Regards, Derek On Fri, Jun 8, 2018 at 6:0

Re: [USRP-users] USRP N310's schematics

Hello Jon, The schematics are still being readied for posting to the website. I'm sorry for the delay in having them available. Do you have any specific questions that I might be able to answer in the meanwhile? The files will be posted to the Knowledge Base when they are ready. https://kb.ettus.c

Re: [USRP-users] X310 Register's Memory Capability

Hi Steve, USE_EMBEDDED_REGS_COEFFS means that the filter will attempt to infer the DSP48's embedded registers (specifically register B) for storing coefficients. You should refer to Xilinx's DSP48 design doc https://www.xilinx.com/support/documentation/user_guides/ug479_7Series_DSP48E1.pdf. Using

[USRP-users] USRP N310's schematics

Hi all, Could you tell us where we can download USRP N310's schematics. Thank you. best regards Jon ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

Re: [USRP-users] About USRP Bandwidths and Sampling Rates

Hello Professor Mercado: I don't think that a row for the AD9361 belongs in that particular table, since that table is for daughterboards, but I see your overall point, and I do agree with you. I will add another table in that section that discusses the analog bandwidths for the USRP devices that

Re: [USRP-users] RFNoC Overrun Using Split Stream

Thanks Juan and Nick. Do you know if this is something RFNoC plans to address in the future? I put a DDC in front of the Split Stream block and now I don't see anymore overrun errors, but I have 2 new problems. First, I can only run the flow graph one time like Juan described. If I stop it and try

Re: [USRP-users] IQ Calibration - CPU Performance Impact?

Derek, I'm very happy to hear that it's the tiniest of additional overhead! Thanks! On Thu, Jun 7, 2018 at 2:32 PM Derek Kozel wrote: > Dave, > > It is most tunes (as often as needed when changing the frequency would > change the IQ correction value). The overhead is, I believe, just a sin

Re: [USRP-users] IQ Calibration - CPU Performance Impact?

Dave, It is most tunes (as often as needed when changing the frequency would change the IQ correction value). The overhead is, I believe, just a single write and thus completely inconsequential when compared to the usual length of synthesizer SPI writes and switch selection that tuning can cause.

Re: [USRP-users] IQ Calibration - CPU Performance Impact?

Ian, Thank you very much! That helps me out a lot! -Dave On Thu, Jun 7, 2018 at 2:17 PM Ian Buckley wrote: > Dave, from what I remember the overhead will be incurred each time a > (re)tune takes you to a different line of the IQ imbalance table…you can > see the granularity of that from s

Re: [USRP-users] IQ Calibration - CPU Performance Impact?

Dave, from what I remember the overhead will be incurred each time a (re)tune takes you to a different line of the IQ imbalance table…you can see the granularity of that from simply looking in the CSV file. The overhead is very minor I suspect, we are talking about updating two integer coefficie

Re: [USRP-users] IQ Calibration - CPU Performance Impact?

Robin, Thanks for your feedback! Marcus, And that overhead is just on the initial tune, or for all tunes? I do mostly timed commands, so should I allow for a little more time before the deadline to send the timed command out? Thanks all! On Thu, Jun 7, 2018 at 1:56 PM Marcus D. Leech

Re: [USRP-users] IQ Calibration - CPU Performance Impact?

On 06/07/2018 01:04 PM, Dave NotTelling via USRP-users wrote: Is there a processing requirement impact to using the calibration CSV file? Does using the cal data have any impact on tuning time for the radio itself? Thanks! The calibration values are stuffed into some machinery in the FPGA wh

Re: [USRP-users] IQ Calibration - CPU Performance Impact?

What I have noticed over the years is the only impact to tuning is the first time you tune, the file is read in and any disk IO is slow relatively speaking. Subsequent tunes after the first are much faster and consistent :) > On June 7, 2018 at 1:04 PM Dave NotTelling via USRP-users > wrote:

[USRP-users] IQ Calibration - CPU Performance Impact?

Is there a processing requirement impact to using the calibration CSV file? Does using the cal data have any impact on tuning time for the radio itself? Thanks! ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listin

Re: [USRP-users] [UHD] Announcing 3.12.0.0 Release

On 06/06/2018 08:26 AM, Martin Braun wrote: > - 3.12.0.0 removed some public API calls, it is thus an API-breaking > release (note that these were some obscure API calls, most users > won't see a difference. GNU Radio users certainly won't). > If you want to keep everything as stable as possi

[USRP-users] About USRP Bandwidths and Sampling Rates

Dear USRP community, Since I'm looking my USRP equipment from a didactic perspective, and I'm encouraging my students to find information for themselves, I would like to suggest an addition to the "About USRP Bandwidths and Sampling Rates

Re: [USRP-users] [UHD] Announcing 3.12.0.0 Release

On 06/06/2018 08:41 AM, Philip Balister wrote: >> Tag, FPGA images and github-auto-produced tarballs can be found here: >> https://github.com/EttusResearch/uhd/releases/tag/v3.12.0.0 > > If you are using tarball checksums to validate the tarball, github will > occasionally regenerate the tarball l

[USRP-users] Streaming results with X310 and UHD 3.9, 3.11, 3.12

Hi, I ran experiments using benchmark_rate using the latest versions of the 3.9.7 (UHD-3.9.LTS), 3.11.1 (maint), and 3.12.0 (master) branches. benchmark_rate --args="addr=192.168.50.2" --rx_rate=100e6 --tx_rate=100e6 --channels="0,1" Results - With 3.9.7, the command completes with no errors,

Re: [USRP-users] X310/SBX-120 Expected Level of Phase Noise

On 06/07/2018 10:03 AM, Kenneth Collier via USRP-users wrote: Hello All, I have an X310/WBX-120 transmitting a 500kHz tone @ 1.6GHz through a power divider to RF A Rx and RF B Rx on an X310/SBX-120. The 10MHz reference for both devices is sourced from an Octoclock-G using its internal referen

Re: [USRP-users] X310 Register's Memory Capability

After examining the files in depth, I realized I need some help understanding core concepts in FPGA programming: In "axi_fir_filter.v" there is a parameter named "USE_EMBEDDED_REGS_COEFFS", and explained in comment: " Reduce register usage by only using embedded registers in DSP slices". - What i

Re: [USRP-users] X310/SBX-120 Expected Level of Phase Noise

What is the Tx gain of your WBX? What is the Rx gain of your SBX? What is the power your signal is going out at in dbm? Assuming: 10MHz reference and 1PPS cables are all same length. Both USRPs have been recently calibrated with utilities. Splitters change phase, although I am not sure that

[USRP-users] X310/SBX-120 Expected Level of Phase Noise

Hello All, I have an X310/WBX-120 transmitting a 500kHz tone @ 1.6GHz through a power divider to RF A Rx and RF B Rx on an X310/SBX-120. The 10MHz reference for both devices is sourced from an Octoclock-G using its internal reference. The PPS reference for both devices is also sourced from the Oct

Re: [USRP-users] Consequences of late command

Hello Fabian, Commands which are late will be executed anyways and return the error notification which you are seeing. Commands after it are also executed. Depending on your application it is often possible to structure the commands such that get_time_now only needs to be called in the beginning a

[USRP-users] Consequences of late command

Hi everyone, I am currently working with timed commands to perform synchronized reception of multiple channels. As the timing is quite critilical I would like to use quite low delay I add to usrp->get_time_now() for the next command(s). However, sometimes it happens (even with quite high valu

Re: [USRP-users] Building the UHD for N3XX devices.

Hello Walter, The N310 uses MPMD as it's host side interface so the appropriate flag is -DENABLE_MPMD. I'll see about documenting that better. The E3xx build flag is entirely separate. http://files.ettus.com/manual/page_usrp_n3xx.html#n3xx_software_dev_uhd Regards, Derek On Thu, Jun 7, 2018 at 5

Re: [USRP-users] X310 Register's Memory Capability

It's going to depend on how much block RAM the image is already using, and how much more you can use while still getting the image to route. The easiest way to find out will be to try it. On Thu, Jun 7, 2018, 9:14 AM shachar J. brown wrote: > Thanks Nick, that's an excellent example. > Do you kn

Re: [USRP-users] X310 Register's Memory Capability

Thanks Nick, that's an excellent example. Do you know what are the memory size restrictions of the configuration data? On Thu, Jun 7, 2018 at 10:50 AM, Nick Foster wrote: > Look at the RFNoC FIR filter block for a good example of pushing > configuration data into a block via the settings bus. >

Re: [USRP-users] X310 Register's Memory Capability

Look at the RFNoC FIR filter block for a good example of pushing configuration data into a block via the settings bus. On Thu, Jun 7, 2018, 8:25 AM shachar J. brown via USRP-users < usrp-users@lists.ettus.com> wrote: > Hi all, > > I'm working on an X310. > > I have large data (tables of 1-3 K of

[USRP-users] X310 Register's Memory Capability

Hi all, I'm working on an X310. I have large data (tables of 1-3 K of variables) I would like to insert into the FPGA's memory registers while running. How much space is available in the FPGA? Seemingly, the Address for the "set_register" is only 8 bits long, and the first 128 addresses are rese

Re: [USRP-users] RFNoC Overrun Using Split Stream

The same solution that works for E310 won't work for X310. The easiest fix will be to use a DDC block to reduce the sample rate ahead of the Split Stream block. The RFNoC bus cannot handle two full-rate streams on a single NoC port. Nick On Thu, Jun 7, 2018, 2:44 AM Juan Francisco via USRP-users

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