Re: [USRP-users] Installing Python Modules into E310

2018-01-30 Thread Martin Braun via USRP-users
On 01/29/2018 10:35 PM, MASDR GS via USRP-users wrote: > Is there a specific method/process to install external modules into the > E310? For example, "python bit-array". We would need this module > installed to run a .grc file using GNUradio directly on the E310. I have > tired installing bitarray

Re: [USRP-users] Unamplified USRP transmission and FCC limits

2018-01-30 Thread Martin Braun via USRP-users
On 01/31/2018 04:27 AM, Bakshi, Arjun via USRP-users wrote: > Hi, > > > For a setup where the tx-rx are indoors, can I assume that the USRPs > transmit power will not cause any significant interference to licensed > users? I'm not planning on using an amplifier, but I will be sweeping > over a si

Re: [USRP-users] Unamplified USRP transmission and FCC limits

2018-01-30 Thread Ron Economos via USRP-users
You may want to consider obtaining an FCC experimental license. A new category called the "Program Experimental License" has been created. https://www.fcc.gov/news-events/blog/2017/04/14/open-business-fccs-new-experimental-licensing-system-accepting-new Ron On 01/30/2018 07:27 PM, Bakshi, A

[USRP-users] Unamplified USRP transmission and FCC limits

2018-01-30 Thread Bakshi, Arjun via USRP-users
Hi, For a setup where the tx-rx are indoors, can I assume that the USRPs transmit power will not cause any significant interference to licensed users? I'm not planning on using an amplifier, but I will be sweeping over a significant portion of TV white space. The room doesn't have RF specific

Re: [USRP-users] [RFNOC] [E310]: Runtime Error: On node 0/FIFO_0 when attempting to run \"rx_samples_to_file\" example

2018-01-30 Thread Carey, Samuel Craig via USRP-users
Howdy, I just managed to accidentally reproduce this exact error. Any updates please? Thanks, Sam ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

Re: [USRP-users] B210 USB power only

2018-01-30 Thread Michael West via USRP-users
Hi Jose, IIRC, the B210 can use up to ~800 mA and the GPSDO has a max of ~200 mA. Assuming the 2 USB 3.0 ports each supply 900 mA, it should work. Check the specs on the host system to make sure each port can deliver enough power. Some controllers limit the total power across ports. Regards, Mic

Re: [USRP-users] JTAG connector for B200mini

2018-01-30 Thread Michael West via USRP-users
Hi Jon, There are 2 cable kits available. One is 4" and the other is 24". They can be found here: https://www.ettus.com/product/details/JTAG-FX3-Cable-4 https://www.ettus.com/product/details/JTAG-FX3-Cable-24 Regards, Michael On Thu, Jan 11, 2018 at 5:18 PM, liu Jong via USRP-users < usrp-use

Re: [USRP-users] x310 simulating RFNoC block with Xilinx IP

2018-01-30 Thread Dang tien Vo-Huu via USRP-users
Hi Jonathon, Thank you for the hint. Actually your suggestion was the first thing I tried but it didn't work. It threw the error: tienvh@gl502vm:~/workspace/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/noc_block_fft_tb$ make xsim BUILDER: Checking tools... * GNU bash, version 4.3.48(1)-release (x86_64-pc-li

Re: [USRP-users] RFNoC: Synthesizing a block containing modules from uhd-fpga

2018-01-30 Thread Adam Parower via USRP-users
My testbench makefile (located at /rfnoc/testbenches/noc_block_DualDUC_tb/Makefile) was generated by RFNoC Modtool, and I have not modified it. Here are the contents, with some comments stripped for brevity: # Define BASE_DIR to point to the "top" dir BASE_DIR = $(FPGA_TOP_DIR)/usrp3/top # In

Re: [USRP-users] NI USRP / PCIe interface and RFNoC FPGA images

2018-01-30 Thread Derek Kozel via USRP-users
Hi Tarik, I'm glad you got that working. Yes, modifying UHD is certainly a way that you can specify a custom file. I didn't mention it because the device arguments method works in nearly all software. For instance, the path to the bitstream can certainly be supplied as a parameter in GNU Radio Com

[USRP-users] FPGA master branch issues (Windows)

2018-01-30 Thread Martin K via USRP-users
$ make X310_HG make -f Makefile.x300.inc bin NAME=X310_HG ARCH=kintex7 PART_ID=xc7k410t/ffg900/-2 BUILD_1G=1 BUILD_10G=1 SFP0_1GBE=1 SFP1_10GBE=1 X310=1 EXTRA_DEFS="BUILD_1G=1 BUILD_10G=1 SFP0_1GBE=1 SFP1_10GBE=1 X310=1" make[1]: Entering directory '/cygdrive/c/fpga/uhd/usrp3/top/x300' BUILDER: Ch

Re: [USRP-users] NI USRP / PCIe interface and RFNoC FPGA images

2018-01-30 Thread Tarik Kazaz via USRP-users
Hello Derek, I managed to specify custom bistream file by editing one of uhd source files ( “/rfnoc/src/uhd/host/build/lib/transport/nirio/lvbitx/x310_lvbitx.cpp”) Changing line 50 to std::string fpga_file = “usrp_x310_fpga_RFNOC_” + option + “.lvbitx”; and then calling in folder “/rfnoc/src/uhd

Re: [USRP-users] NI USRP / PCIe interface and RFNoC FPGA images

2018-01-30 Thread Derek Kozel via USRP-users
Hi Tarik, The USRP source in GNU Radio has a spot for specifying device arguments. The osmocom_fft application has a "--args" option the same as the UHD utilities. There is not currently the ability to specify a custom default FPGA image but it is a feature we agree would be useful. Regards, Dere

Re: [USRP-users] Installing Python Modules into E310

2018-01-30 Thread Philip Balister via USRP-users
On 01/29/2018 04:35 PM, MASDR GS via USRP-users wrote: > Is there a specific method/process to install external modules into the > E310? For example, "python bit-array". We would need this module installed > to run a .grc file using GNUradio directly on the E310. I have tired > installing bitarray

Re: [USRP-users] NI USRP / PCIe interface and RFNoC FPGA images

2018-01-30 Thread Tarik Kazaz via USRP-users
Hello Derek, I got you. Thank you. I have one more question, where can I specify default bit stream location? What happen now is that by calling uhd_usrp_probe –args =”fpga=/path/to/image.lvbitx” I am able to flash USRP with RFNoC design. However, after I run gnuradio fosphor program it again

Re: [USRP-users] NI USRP / PCIe interface and RFNoC FPGA images

2018-01-30 Thread Derek Kozel via USRP-users
Hi Tarik, Your steps are based on the misunderstanding of how the image loading occurs in each of these scenarios. When using PCIe the FPGA will always be reloaded from the host computer. Every program you run using the PCIe link needs the "fpga=/path/to/image.lvbitx" string added to the device a

Re: [USRP-users] NI USRP / PCIe interface and RFNoC FPGA images

2018-01-30 Thread Tarik Kazaz via USRP-users
Hello Martin, I hope I am replying now correctly (I am using reply all to you and mailing list). I am still not able to flash RFNoC bit stream on FPGA. Here is what I am doing: 1. First step - Check status of device Call: uhd_usrp_probe Output: [I