My testbench makefile (located at <my 
module>/rfnoc/testbenches/noc_block_DualDUC_tb/Makefile) was generated by RFNoC 
Modtool, and I have not modified it. Here are the contents, with some comments 
stripped for brevity:



# Define BASE_DIR to point to the "top" dir

BASE_DIR = $(FPGA_TOP_DIR)/usrp3/top
# Include viv_sim_preample after defining BASE_DIR
include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak

# Define only one toplevel module
SIM_TOP = noc_block_DualDUC_tb

# Add test bench, user design under test, and
# additional user created files
SIM_SRCS = \
$(abspath noc_block_DualDUC_tb.sv) \
$(abspath ../../fpga-src/noc_block_DualDUC.v)

MODELSIM_USER_DO =

# Include all simulator specific makefiles here
# Each should define a unique target to simulate
# e.g. xsim, vsim, etc and a common "clean" target
include $(BASE_DIR)/../tools/make/viv_simulator.mak


Adam Parower

________________________________
From: Jon Pendlum <jon.pend...@gmail.com>
Sent: Monday, January 29, 2018 7:52:47 PM
To: Adam Parower
Cc: usrp-users@lists.ettus.com
Subject: Re: [USRP-users] RFNoC: Synthesizing a block containing modules from 
uhd-fpga

Hi Adam,

Can you post your testbench makefile?

Jonathon

On Jan 10, 2018 5:07 PM, "Adam Parower via USRP-users" 
<usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com>> wrote:

Hello everyone,


I am trying to create a custom RFNoC block that is similar to the built-in DUC 
block. As such, it depends on the cordic_timed, axi_rate_change, and duc 
modules defined in uhd-fpga/usrp3/lib/rfnoc. When I attempt to run the 
testbench for my block, Vivado fails in synthesis. While Vivado is able to find 
cordic_timed.v, axi_rate_change.v, and duc.v, it is unable to find the 
submodules that these modules depend on (e.g. axi_rate_change requires 
setting_reg, axi_fifo_flop2, and axi_drop_partial_packet). What can I do to get 
Vivado to find these dependencies and synthesize my block?


Thank you in advance for your assistance.


Adam Parower

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