[U-Boot] Enabling D cache on Arm Cortex A8 in U-boot

Hi, I want to enable D/I Cache in ARM Cortex, whenever i enable cache bit in control register, system hangs. I feel i dont have to flush the cache since u-boot in single threaded app. Can u please let me know the steps to be followed to enable. I have enabled MMU and it is working fine. I have

[U-Boot] Why Cache flush required in some ARM Cortex boards to enable D cache?

Hi, I ran into problems when i enabled D cache. But later i found out that cache flush was required before enabling D Cache. What i dont understand is why is it required?. Since earlier D cache is never enabled and so nothing should be present in the cache. Flushing is only required during cont

Re: [U-Boot] Why Cache flush required in some ARM Cortex boards to enable D cache?

Hi Dirk, Thanks i got some useful information. Warm Regards, Akshay --- On Thu, 10/9/09, Dirk Behme wrote: > From: Dirk Behme > Subject: Re: [U-Boot] Why Cache flush required in some ARM Cortex boards to > enable D cache? > To: "akshay ts" > Cc: u-boot@lists.den

[U-Boot] CPU Sleep in ARM Cortex A8

Hi, I want to know what is the instruction for sleeping in ARM Cortex A8. I did execute a WFI instruction seems to be a NOP. void cpu_idle() { unsigned long tmp = 0; asm("b 1f\n\t" ".align 5\n\t" "1:\n\t" "mcr p15, 0, %0, c7, c10, 5\n\t" "mcr

[U-Boot] strex/ldrex compilation error while using atomic_inc u-boot

Hi all, I am getting the following error while building using ARMV7 toolchain. {standard input}:599: Error: selected processor does not support `ldrex r1,[r2]' {standard input}:601: Error: selected processor does not support `strex r3,r1,[r2]' For example the following code uses strex and ldrex

[U-Boot] How to get a interrupt in ARM in physical address space

Hi, I want to enable interrupts in ARM, Since the vectors are at fixed locations like 0x and 0x, and physical memory starts from 0x5000 , this is only possible if vitual MMU is enabled, without this is it possible like by using memory protection unit?.I am not sure can u plea

[U-Boot] Can I and/or D Cache work without MMU enabling in ARM11 or ARM cortex

Hi, I want to use i and/or D cache in ARM cortex on a OMAP3430 system without MMU. Is it possible? Warm Regards, Akshay Looking for local information? Find it on Yahoo! Local http://in.local.yahoo.com/ ___ U-Boot mailing list U-Boot@lists.denx

Re: [U-Boot] Can I and/or D Cache work without MMU enabling in ARM11 or ARM cortex

RM cortex > To: "akshay ts" > Cc: u-boot@lists.denx.de > Date: Monday, 13 July, 2009, 3:06 PM > I yes, D no. > > On Mon, Jul 13, 2009 at 9:04 AM, > akshay ts > wrote: > > > > Hi, > > I want to use i and/or D cache in ARM cortex on a OMAP3430