Hi,
I ran into problems when i enabled D cache. But later i found out that cache
flush was required before enabling D Cache. What i dont understand is why is it
required?. Since earlier D cache is never enabled and so nothing should be
present in the cache.
Flushing is only required during context switch/may be interrupts?.
I tried with omap3 board with Arm cortex A8 on it, it worked without a cache
flush. I tried with C110 with Arm cortex A8 on it, i had to do a cache flush to
make D cache work.
Also if possible please tell me what is a GP device, OMAP3 (CONTROL_STATUS
register) seems to be a GP device and hence they are skipping cache flush. I
dont know what is this.
Warm Regards,
Akshay
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