The Freescale LS1021AQDS share some pins, so Add the hwconfig option
that allows the user to choose which the function he wants.
The main pin mux IP is:
eSDHC, SAI, IIC2, RGMII, CAN, SAI.
Signed-off-by: Yuan Yao
---
board/freescale/ls1021aqds/ls1021aqds.c | 67
Added in v1:
- Add pin mux support for ls1021aqds.
Test log:
U-Boot 2014.07-01993-g052b512-dirty (Oct 20 2014 - 19:58:20)
CPU: Freescale LayerScape LS1020E, Version: 1.0, (0x87081010)
Clock Configuration:
CPU0(ARMV7):1000 MHz,
Bus:300 MHz, DDR:800 MHz (1600 MT/s data rate),
Affects: DDR
Description: Memory controller performance is not optimal with default
internal target queue register values.
Impact: Memory controller performance is not optimal.
Workaround: Write a value of 63b2_0002h to address: 157_020Ch.
Signed-off-by: Yuan Yao
---
arch/arm/include/asm/arch
EDDRTQCFG Registers are Integration Strap values which controls
performance parameters for DDR Controller.
The bit 25 is used to disable priorities within DDR since DDR
are connected backwards on silicon Rev2.0.
Signed-off-by: Yuan Yao
---
board/freescale/ls1021aqds/ls1021aqds.c | 13
For LS1021A Rev2.0 have already fixed the snoop silicon issue, So enable
snoop requests and DVM message requests for all the slave insterfaces.
Signed-off-by: Yuan Yao
---
board/freescale/ls1021aqds/ls1021aqds.c | 8 +++-
board/freescale/ls1021atwr/ls1021atwr.c | 8 +++-
2 files changed
Signed-off-by: Yuan Yao
---
arch/arm/cpu/armv7/ls102xa/soc.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 6036473..97ba6d5 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu
Enable the IP feature's snoop signal to support
hardware snoop for cache coherence.
SNPCNFGCR contains the bits to drive snoop signal
for various masters.
Signed-off-by: Yuan Yao
---
arch/arm/cpu/armv7/ls102xa/soc.c | 8
arch/arm/include/asm/arch-ls
This is a workaround for hardware erratum.
Write the value of 63b2_0002h to EDDRTQCFG will optimal the
memory controller performance.
The value: 63b2_0002h comes from the hardware team.
Signed-off-by: Yuan Yao
---
arch/arm/cpu/armv7/ls102xa/soc.c | 10 ++
arch/arm
Create a soc.c file to put the code for soc special settings.
Signed-off-by: Yuan Yao
---
arch/arm/cpu/armv7/ls102xa/Makefile | 1 +
arch/arm/cpu/armv7/ls102xa/soc.c| 66 +
arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h | 12 +
board
Both of the erratum:A008336 and A008514 are not apply to all the
soc like:LS1021A, LS1043A.
So it seems better to move those erratum codes form the general ddr
file to the private soc file.
Signed-off-by: Yuan Yao
---
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 37
Erratum number: ERR008514
EDDRTQCFG Registers are Integration Strap values which controls
performance parameters for DDR Controller.
The bit 25 is used to disable priorities within DDR since DDR
are connected backwards on Rev2.0 silicon for LS1021A.
Signed-off-by: Yuan Yao
---
arch/arm/cpu
Enable the IP feature's snoop signal to support
hardware snoop for cache coherence.
SNPCNFGCR contains the bits to drive snoop signal
for various masters.
Signed-off-by: Yuan Yao
---
arch/arm/cpu/armv7/ls102xa/soc.c | 8
arch/arm/include/asm/arch-ls
This is a workaround for hardware erratum.
Write the value of 63b2_0042h to EDDRTQCFG will optimal the
memory controller performance.
The value: 63b2_0042h comes from the hardware team.
Signed-off-by: Yuan Yao
---
Changed in v2:
squash both of the two patches into one patch to set EDDRTQCF
Signed-off-by: Yuan Yao
---
arch/arm/cpu/armv7/ls102xa/soc.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 6036473..97ba6d5 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu
Both of the erratum:A008336 and A008514 are not apply to all the
soc like:LS1021A, LS1043A.
So it seems better to move those erratum codes form the general ddr
file to the private soc file.
Signed-off-by: Yuan Yao
---
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 37
Create a soc.c file to put the code for soc special settings.
Signed-off-by: Yuan Yao
---
arch/arm/cpu/armv7/ls102xa/Makefile | 1 +
arch/arm/cpu/armv7/ls102xa/soc.c| 66 +
arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h | 12 +
board
Enable the IP feature's snoop signal to support
hardware snoop for cache coherence.
SNPCNFGCR contains the bits to drive snoop signal
for various masters.
Signed-off-by: Yuan Yao
---
arch/arm/cpu/armv7/ls102xa/soc.c | 8
arch/arm/include/asm/arch-ls
Signed-off-by: Yuan Yao
---
arch/arm/cpu/armv7/ls102xa/soc.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 6036473..97ba6d5 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu
Yuan Yao(5):
arm: ls1021a: merge SoC specific code in a separate file
arm: ls102xa: enable all the snoop signal for masters.
ls102xa: Enable snoop and DVM message requests.
armv7/fsl-ls102xa: Workaround for DDR erratum A008514
Changed in v2:
Update the write value to 63b2_0042h;
move
This is a workaround for hardware erratum.
Write the value of 63b2_0042h to EDDRTQCFG will optimal the
memory controller performance.
The value: 63b2_0042h comes from the hardware team.
Signed-off-by: Yuan Yao
---
Changed in v2:
Update the write value to 63b2_0042h;
---
arch/arm/cpu
Create a soc.c file to put the code for soc special settings.
Signed-off-by: Yuan Yao
---
arch/arm/cpu/armv7/ls102xa/Makefile | 1 +
arch/arm/cpu/armv7/ls102xa/soc.c| 66 +
arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h | 12 +
board
As the errata A008336 and A008514 do not apply to all LS series SoCs
(such as LS1021A, LS1043A) we move them to an soc specific file
Signed-off-by: Yuan Yao
---
Changed in v2:
Update the patch commit message.
---
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 37
Enable the IP feature's snoop signal to support
hardware snoop for cache coherence.
SNPCNFGCR contains the bits to drive snoop signal
for various masters.
Signed-off-by: Yuan Yao
---
arch/arm/cpu/armv7/ls102xa/soc.c | 8
arch/arm/include/asm/arch-ls
arm: ls1021a: merge SoC specific code in a separate file
arm: ls102xa: enable all the snoop signal for masters.
ls102xa: Enable snoop and DVM message requests.
armv7/fsl-ls102xa: Workaround for DDR erratum A008514
Changed in v2:
Update the write value to 63b2_0042h;
move erratum a008336 an
Create a soc.c file to put the code for soc special settings.
Signed-off-by: Yuan Yao
---
arch/arm/cpu/armv7/ls102xa/Makefile | 1 +
arch/arm/cpu/armv7/ls102xa/soc.c| 66 +
arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h | 12 +
board
Signed-off-by: Yuan Yao
---
arch/arm/cpu/armv7/ls102xa/soc.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 6036473..97ba6d5 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu
This is a workaround for hardware erratum.
Write the value of 63b2_0042h to EDDRTQCFG will optimal the
memory controller performance.
The value: 63b2_0042h comes from the hardware team.
Signed-off-by: Yuan Yao
---
Changed in v2:
Update the write value to 63b2_0042h;
---
arch/arm/cpu
As the errata A008336 and A008514 do not apply to all LS series SoCs
(such as LS1021A, LS1043A) we move them to an soc specific file
Signed-off-by: Yuan Yao
---
Changed in v3:
Fix a typo issue.
In function "erratum_a008514"
"#ifdef CONFIG_SYS_FSL_DCSR_DDR2_
For LS1021ATWR board in order to support SATA(Gen 3),
SerDes Lan B will be connect to SATA directly.
So SerDes 0x20 can't support 2SGMII at the same time.
In order to support two SGMII and one RGMII at the same time,
we used 0x30 to replace 0x20.
Signed-off-by: Yuan Yao
---
board/free
Erratum A-008022 has been fixed on LS1021A Rev2.0.
So we can use DSPI2 now, this patch enable DSPI2
in dts for LS1021ATWR.
Signed-off-by: Yuan Yao
---
arch/arm/dts/ls1021a-twr.dts | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/dts/ls1021a-twr.dts b/arch/arm/dts
AT26DF081A is the spi flash type of TWR-MEM(SCH-26248) card.
We can access the flash through DSPI2 on LS1021ATWR board.
Signed-off-by: Yuan Yao
---
drivers/mtd/spi/sf_params.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
index
DSPI2 can be verified when boot from QSPI now.
Signed-off-by: Yuan Yao
---
include/configs/ls1021atwr.h | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 7dcb719..a14277e 100644
--- a/include/configs
I2C1 can work on ls102xa rev2.0 SD boot, so add
ID EEPROM for SD boot.
Signed-off-by: Yuan Yao
---
include/configs/ls1021atwr.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 7dcb719..59e704e 100644
--- a/include/configs
The Freescale LS1021ATWR share some pins, so Add the hwconfig option
that allows the user to choose which the function he wants.
Signed-off-by: Yuan Yao
---
board/freescale/ls1021atwr/ls1021atwr.c | 78 +
1 file changed, 78 insertions(+)
diff --git a/board
Enable the IP feature's snoop signal to support
hardware snoop for cache coherence.
SNPCNFGCR contains the bits to drive snoop signal
for various masters.
Signed-off-by: Yuan Yao
---
arch/arm/cpu/armv7/ls102xa/soc.c | 8
arch/arm/include/asm/arch-ls
Create a soc.c file to put the code for soc special settings.
Signed-off-by: Yuan Yao
---
arch/arm/cpu/armv7/ls102xa/Makefile | 1 +
arch/arm/cpu/armv7/ls102xa/soc.c| 66 +
arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h | 12 +
board
Affects: DDR
Description: Memory controller performance is not optimal with default
internal target queue register values.
Impact: Memory controller performance is not optimal.
Workaround: Write a value of 63b2_0002h to address: 157_020Ch.
Signed-off-by: Yuan Yao
---
arch/arm/cpu/armv7/ls102xa
Signed-off-by: Yuan Yao
---
arch/arm/cpu/armv7/ls102xa/soc.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 6036473..97ba6d5 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu
EDDRTQCFG Registers are Integration Strap values which controls
performance parameters for DDR Controller.
The bit 25 is used to disable priorities within DDR since DDR
are connected backwards on Rev2.0.
Signed-off-by: Yuan Yao
---
arch/arm/cpu/armv7/ls102xa/soc.c | 13 -
1 file
Create a soc.c file to put the code for soc special settings.
Signed-off-by: Yuan Yao
---
Changes in v2:
update to the lastest base.
---
arch/arm/cpu/armv7/ls102xa/Makefile | 1 +
arch/arm/cpu/armv7/ls102xa/soc.c| 66 +
arch/arm/include/asm
Enable the IP feature's snoop signal to support
hardware snoop for cache coherence.
SNPCNFGCR contains the bits to drive snoop signal
for various masters.
Signed-off-by: Yuan Yao
---
arch/arm/cpu/armv7/ls102xa/soc.c | 8
arch/arm/include/asm/arch-ls
Signed-off-by: Yuan Yao
---
arch/arm/cpu/armv7/ls102xa/soc.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 6036473..97ba6d5 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu
This is a workaround for hardware erratum.
Write the value of 63b2_0002h to EDDRTQCFG will optimal the
memory controller performance.
The value: 63b2_0002h comes from the hardware team.
Signed-off-by: Yuan Yao
---
Changes in v2:
Rewrite the commit message to explain why and what this patch does
Erratum number: ERR008514
EDDRTQCFG Registers are Integration Strap values which controls
performance parameters for DDR Controller.
The bit 25 is used to disable priorities within DDR since DDR
are connected backwards on Rev2.0 silicon for LS1021A.
Signed-off-by: Yuan Yao
---
Changes in v2
From: Yuan Yao
Yuan Yao (12):
armv8: ls2080aqds: Select QSPI CLK div via SCFG
configs: ls2080a_common: Remove duplicate NOR configs
configs: ls2080aqds: Disable IFC NOR & QIXIS when QSPI
configs: ls2080aqds: Enable QSPI flash support
dm: dts: ls2080aqds: Add QSPI dts node
a
From: Yuan Yao
When QSPI is enabled, NOR Flash and QIXIS can’t be accessed through IFC
due to pin muxing.
Enable QIXIS accessing through I2C.
Signed-off-by: Yuan Yao
---
include/configs/ls2080aqds.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/include/configs/ls2080aqds.h
From: Yuan Yao
The Freescale QSPI driver has been converted to Driver Model.
This patch enable FSL_QSPI and its dependence options, DM, DM_SPI,
OF_CONTROL and so on.
Signed-off-by: Yuan Yao
---
configs/ls2080aqds_nand_defconfig | 9 +
1 file changed, 9 insertions(+)
diff --git a
From: Yuan Yao
This patch is used for fix the bug below:
/***/
"Synchronous Abort" handler, esr 0x86000210
ELR: fff6cfb4
LR: fff6d3f0
x0 : 0022 x1 : fff78c6f
x2 : ffd0ecb0 x3 :
x4 : f
From: Yuan Yao
Freescale QSPI and DSPI driver have been converted to Driver Mode.
This converting bring dtb file for u-boot and this increase the size
of u-boot image.
LS2080A nand boot use SPL framework.
This patch increase the size of image load from NAND to RAM in SPL.
Signed-off-by: Yuan
From: Yuan Yao
Enable QSPI flash related configure options.
Signed-off-by: Yuan Yao
---
include/configs/ls2080aqds.h | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 3edb0b9..3cba10a 100644
From: Yuan Yao
Signed-off-by: Yuan Yao
---
board/freescale/common/qixis.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c
index 113295f..de9daeb 100644
--- a/board/freescale/common/qixis.c
+++ b
From: Yuan Yao
This patch adds QSPI boot support for LS2080AQDS board.
The QSPI boot image need to be programmed into the QSPI flash
first. Then the booting will start from QSPI memory space.
Signed-off-by: Yuan Yao
---
configs/ls2080aqds_qspi_defconfig | 10 ++
include/configs
From: Yuan Yao
Add QSPI controller and slave dts node for LS2080AQDS board.
Signed-off-by: Yuan Yao
---
arch/arm/dts/fsl-ls2080a-qds.dts | 14 ++
arch/arm/dts/fsl-ls2080a.dtsi| 10 ++
2 files changed, 24 insertions(+)
diff --git a/arch/arm/dts/fsl-ls2080a-qds.dts b
From: Yuan Yao
Signed-off-by: Yuan Yao
---
include/configs/ls2080aqds.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 513a2e3..064e341 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
From: Yuan Yao
If we want to access QSPI flash when boot from NAND,
we need below board configuration:
Boot Source ISO1ISO2IBOOT
On-board NAND 1 0 0
IFCCARD NAND0 0 1
Signed-off-by: Yuan Yao
---
arch/arm/include/asm/arch-fsl-layerscape
From: Yuan Yao
The NOR flash related configure options also appear in ls2080aqds.h and
ls2080ardb.h, and the two files all have included ls2080a_common.h.
This patch remove the duplicated options in ls2080a_common.h.
Signed-off-by: Yuan Yao
---
include/configs/ls2080a_common.h | 7
From: Yuan Yao
QSPI module output SCLK divisor value is configured through SCFG.
Signed-off-by: Yuan Yao
---
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 +
board/freescale/ls2080aqds/ls2080aqds.c| 5 +
2 files changed, 6 insertions(+)
diff --git a/arch/arm
From: Yuan Yao
Freescale QSPI and DSPI driver have been converted to Driver Mode.
This converting bring dtb file for u-boot and this increase the size
of u-boot image.
LS2080A nand boot use SPL framework.
This patch increase the size of image load from NAND to RAM in SPL.
Signed-off-by: Yuan
From: Yuan Yao
The NOR flash related configure options also appear in ls2080aqds.h and
ls2080ardb.h, and the two files all have included ls2080a_common.h.
This patch remove the duplicated options in ls2080a_common.h.
Signed-off-by: Yuan Yao
---
include/configs/ls2080a_common.h | 7
From: Yuan Yao
This patch adds QSPI boot support for LS2080AQDS board.
The QSPI boot image need to be programmed into the QSPI flash
first. Then we can switch to booting from QSPI memory space.
Yuan Yao (11):
armv8: ls2080aqds: Select QSPI CLK div via SCFG
configs: ls2080a_common: Remove
From: Yuan Yao
Add early i2c init function with conservative divider when the exact
clock rate is not available.
Signed-off-by: Yuan Yao
---
New add in v3.
---
drivers/i2c/i2c_core.c | 5 +
drivers/i2c/mxc_i2c.c | 27 +++
include/i2c.h | 3 +++
3 files
From: Yuan Yao
When QSPI boot is used, board FPGA is not accessible from IFC.
To use I2C interface instead, i2c needs to be initialized before knowing
the exact clock rate.
Signed-off-by: Yuan Yao
---
New add in v3.
---
board/freescale/ls2080aqds/ls2080aqds.c | 3 +++
include/configs
From: Yuan Yao
The Freescale QSPI driver has been converted to Driver Model.
This patch enable FSL_QSPI and its dependence options, DM, DM_SPI,
OF_CONTROL and so on.
Signed-off-by: Yuan Yao
---
configs/ls2080aqds_nand_defconfig | 8
1 file changed, 8 insertions(+)
diff --git a
From: Yuan Yao
In order to access QSPI flash we must asserted ISO allowing
the DUT to access the full IFC domain.
But deasserted the unused ISO will allowing maximum performance.
Signed-off-by: Yuan Yao
---
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 2 ++
board/freescale
From: Yuan Yao
When QSPI is enabled, NOR flash and QIXIS can't be accessed through IFC
due to pin mux.
Signed-off-by: Yuan Yao
---
include/configs/ls2080aqds.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
From: Yuan Yao
QSPI module output SCLK divisor value is configured through SCFG.
Signed-off-by: Yuan Yao
---
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 +
board/freescale/ls2080aqds/ls2080aqds.c| 5 +
2 files changed, 6 insertions(+)
diff --git a/arch/arm
From: Yuan Yao
Add QSPI controller and slave dts node for LS2080AQDS board.
Signed-off-by: Yuan Yao
---
arch/arm/dts/fsl-ls2080a-qds.dts | 14 ++
arch/arm/dts/fsl-ls2080a.dtsi| 10 ++
2 files changed, 24 insertions(+)
diff --git a/arch/arm/dts/fsl-ls2080a-qds.dts b
From: Yuan Yao
Enable QSPI flash related configure options.
Signed-off-by: Yuan Yao
---
include/configs/ls2080aqds.h | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index a14b465..c0c2a97 100644
From: Yuan Yao
This patch adds QSPI boot support for LS2080AQDS board.
The QSPI boot image need to be programmed into the QSPI flash
first. Then we can switch to booting from QSPI memory space.
Signed-off-by: Yuan Yao
---
Changed in v3:
1, Rebase to lastest code.
2, Give up to
From: Yuan Yao
QSPI module output SCLK divisor value is configured through SCFG.
Signed-off-by: Yuan Yao
---
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 +
board/freescale/ls2080aqds/ls2080aqds.c| 5 +
2 files changed, 6 insertions(+)
diff --git a/arch/arm
From: Yuan Yao
This patch adds QSPI boot support for LS2080AQDS board.
The QSPI boot image need to be programmed into the QSPI flash
first. Then we can switch to booting from QSPI memory space.
Yuan Yao (10):
drivers: i2c: mxc: Add early init
armv8: ls2080aqds: Select QSPI CLK div via SCFG
From: Yuan Yao
Add early i2c init function with conservative divider when the exact
clock rate is not available.
Signed-off-by: Yuan Yao
---
drivers/i2c/i2c_core.c | 5 +
drivers/i2c/mxc_i2c.c | 27 +++
include/i2c.h | 3 +++
3 files changed, 35
From: Yuan Yao
The NOR flash related configure options also appear in ls2080aqds.h and
ls2080ardb.h, and the two files all have included ls2080a_common.h.
This patch remove the duplicated options in ls2080a_common.h.
Signed-off-by: Yuan Yao
---
include/configs/ls2080a_common.h | 7
From: Yuan Yao
Enable QSPI flash related configure options.
Signed-off-by: Yuan Yao
---
include/configs/ls2080aqds.h | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index a14b465..c0c2a97 100644
From: Yuan Yao
When QSPI is enabled, NOR flash and QIXIS can't be accessed through IFC
due to pin mux.
Signed-off-by: Yuan Yao
---
include/configs/ls2080aqds.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
From: Yuan Yao
Add QSPI controller and slave dts node for LS2080AQDS board.
Signed-off-by: Yuan Yao
---
arch/arm/dts/fsl-ls2080a-qds.dts | 14 ++
arch/arm/dts/fsl-ls2080a.dtsi| 10 ++
2 files changed, 24 insertions(+)
diff --git a/arch/arm/dts/fsl-ls2080a-qds.dts b
From: Yuan Yao
The Freescale QSPI driver has been converted to Driver Model.
This patch enable FSL_QSPI and its dependence options, DM, DM_SPI,
OF_CONTROL and so on.
Signed-off-by: Yuan Yao
---
configs/ls2080aqds_nand_defconfig | 8
1 file changed, 8 insertions(+)
diff --git a
From: Yuan Yao
In order to access QSPI flash we must asserted ISO allowing
the DUT to access the full IFC domain.
But deasserted the unused ISO will allowing maximum performance.
Signed-off-by: Yuan Yao
---
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 2 ++
board/freescale
From: Yuan Yao
Freescale QSPI and DSPI driver have been converted to Driver Mode.
This converting bring dtb file for u-boot and this increase the size
of u-boot image.
LS2080A nand boot use SPL framework.
This patch increase the size of image load from NAND to RAM in SPL.
Signed-off-by: Yuan
From: Yuan Yao
This patch adds QSPI boot support for LS2080AQDS board.
The QSPI boot image need to be programmed into the QSPI flash
first. Then we can switch to booting from QSPI memory space.
Signed-off-by: Yuan Yao
---
Changed in v3:
1, Rebase to lastest code.
2, Give up to
From: Yuan Yao
QSPI module output SCLK divisor value is configured through SCFG.
Signed-off-by: Yuan Yao
---
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 +
board/freescale/ls2080aqds/ls2080aqds.c| 5 +
2 files changed, 6 insertions(+)
diff --git a/arch/arm
From: Yuan Yao
The NOR flash related configure options also appear in ls2080aqds.h and
ls2080ardb.h, and the two files all have included ls2080a_common.h.
This patch remove the duplicated options in ls2080a_common.h.
Signed-off-by: Yuan Yao
---
include/configs/ls2080a_common.h | 7
From: Yuan Yao
This patch adds QSPI boot support for LS2080AQDS board.
The QSPI boot image need to be programmed into the QSPI flash
first. Then we can switch to booting from QSPI memory space.
Yuan Yao (10):
drivers: i2c: mxc: Add early init
armv8: ls2080aqds: Select QSPI CLK div via SCFG
From: Yuan Yao
Add early i2c init function with conservative divider when the exact
clock rate is not available.
Signed-off-by: Yuan Yao
---
New add in v3.
---
drivers/i2c/i2c_core.c | 5 +
drivers/i2c/mxc_i2c.c | 27 +++
include/i2c.h | 3 +++
3 files
From: Yuan Yao
Enable QSPI flash related configure options.
Signed-off-by: Yuan Yao
---
include/configs/ls2080aqds.h | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 99b0551..f917484 100644
From: Yuan Yao
When QSPI is enabled, NOR flash and QIXIS can't be accessed
through IFC due to pin mux.
So enable I2C QIXIS access and I2C early init to read the
sysclk and ddrclk.
Signed-off-by: Yuan Yao
---
Changed in v5:
Use I2C to read the clocks instead of the hard-coded c
From: Yuan Yao
In order to access QSPI flash we must asserted ISO allowing
the DUT to access the full IFC domain.
But deasserted the unused ISO will allowing maximum performance.
Signed-off-by: Yuan Yao
---
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 2 ++
board/freescale
From: Yuan Yao
Add QSPI controller and slave dts node for LS2080AQDS board.
Signed-off-by: Yuan Yao
---
arch/arm/dts/fsl-ls2080a-qds.dts | 14 ++
arch/arm/dts/fsl-ls2080a.dtsi| 10 ++
2 files changed, 24 insertions(+)
diff --git a/arch/arm/dts/fsl-ls2080a-qds.dts b
From: Yuan Yao
This patch adds QSPI boot support for LS2080AQDS board.
The QSPI boot image need to be programmed into the QSPI flash
first. Then we can switch to booting from QSPI memory space.
Signed-off-by: Yuan Yao
---
Changed in v4:
Merged the below patch into one:
board
From: Yuan Yao
Freescale QSPI and DSPI driver have been converted to Driver Mode.
This converting bring dtb file for u-boot and this increase the size
of u-boot image.
LS2080A nand boot use SPL framework.
This patch increase the size of image load from NAND to RAM in SPL.
Signed-off-by: Yuan
From: Yuan Yao
The Freescale QSPI driver has been converted to Driver Model.
This patch enable FSL_QSPI and its dependence options, DM, DM_SPI,
OF_CONTROL and so on.
Signed-off-by: Yuan Yao
---
configs/ls2080aqds_nand_defconfig | 8
1 file changed, 8 insertions(+)
diff --git a
From: Yuan Yao
This patch adds QSPI boot support for LS2080AQDS board.
The QSPI boot image need to be programmed into the QSPI flash
first. Then we can switch to booting from QSPI memory space.
Yuan Yao (10):
drivers: i2c: mxc: Add early init
armv8: ls2080aqds: Select QSPI CLK div via SCFG
From: Yuan Yao
Add early i2c init function with conservative divider when the exact
clock rate is not available.
Signed-off-by: Yuan Yao
---
New add in v3.
---
drivers/i2c/i2c_core.c | 5 +
drivers/i2c/mxc_i2c.c | 27 +++
include/i2c.h | 3 +++
3 files
From: Yuan Yao
QSPI module output SCLK divisor value is configured through SCFG.
Signed-off-by: Yuan Yao
---
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 +
board/freescale/ls2080aqds/ls2080aqds.c| 5 +
2 files changed, 6 insertions(+)
diff --git a/arch/arm
From: Yuan Yao
The NOR flash related configure options also appear in ls2080aqds.h and
ls2080ardb.h, and the two files all have included ls2080a_common.h.
This patch remove the duplicated options in ls2080a_common.h.
Signed-off-by: Yuan Yao
---
include/configs/ls2080a_common.h | 7
From: Yuan Yao
Enable QSPI flash related configure options.
Signed-off-by: Yuan Yao
---
Changed in v6:
remove CONFIG_CMD_SF.
---
include/configs/ls2080aqds.h | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/include/configs/ls2080aqds.h b/include
From: Yuan Yao
Freescale QSPI and DSPI driver have been converted to Driver Mode.
This converting bring dtb file for u-boot and this increase the size
of u-boot image.
LS2080A nand boot use SPL framework.
This patch increase the size of image load from NAND to RAM in SPL.
Signed-off-by: Yuan
From: Yuan Yao
This patch adds QSPI boot support for LS2080AQDS board.
The QSPI boot image need to be programmed into the QSPI flash
first. Then we can switch to booting from QSPI memory space.
Signed-off-by: Yuan Yao
---
Changed in v6:
Add CONFIG_CMD_SF in defconfig.
Changed in v4
From: Yuan Yao
In order to access QSPI flash we must asserted ISO allowing
the DUT to access the full IFC domain.
But deasserted the unused ISO will allowing maximum performance.
Signed-off-by: Yuan Yao
---
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 2 ++
board/freescale
From: Yuan Yao
Add QSPI controller and slave dts node for LS2080AQDS board.
Signed-off-by: Yuan Yao
---
arch/arm/dts/fsl-ls2080a-qds.dts | 14 ++
arch/arm/dts/fsl-ls2080a.dtsi| 10 ++
2 files changed, 24 insertions(+)
diff --git a/arch/arm/dts/fsl-ls2080a-qds.dts b
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