On 13.09.2023 07:56, Ilias Apalodimas wrote:
On Fri, Sep 08, 2023 at 07:53:08PM +0600, Maxim Uvarov wrote:
U-Boot recently got support for an alternative network stack using LWIP.
Replace dns command with the LWIP variant while keeping the output and
error messages identical.
Signed-off-by:
On 13.09.2023 08:07, Ilias Apalodimas wrote:
On Fri, Sep 08, 2023 at 07:53:09PM +0600, Maxim Uvarov wrote:
+
+#include
+#include
+#include
+
+#include
+#include
+#include "lwip/timeouts.h"
+
+#include
+#include
+
+#define DHCP_WAIT_MS 2000
Is this the time we wait for a dhcp reply? I
On 13.09.2023 08:15, Ilias Apalodimas wrote:
+
+/*
+ * (C) Copyright 2023 Linaro Ltd.
+ */
+
+#include
+#include
+#include
+#include
+
+#include "tftp_client.h"
+#include "tftp_server.h"
+#include
+
+#include
+
+#include
+
+static ulong daddr;
+static ulong size;
+
+static void *tftp_o
On 13.09.2023 09:53, Ilias Apalodimas wrote:
Hi Maxim,
On Wed, 13 Sept 2023 at 10:32, Maxim Uvarov wrote:
On Wed, 13 Sept 2023 at 01:27, Simon Glass wrote:
Hi Maxim,
On Tue, 12 Sept 2023 at 05:42, Maxim Uvarov wrote:
On Fri, 8 Sept 2023 at 19:59, Tom Rini wrote:
On Fri, Sep 08,
On 21.09.2023 18:29, Simon Glass wrote:
Hi,
On Wed, 13 Sept 2023 at 07:35, Maxim Uvarov wrote:
On Wed, 13 Sept 2023 at 19:14, Tom Rini wrote:
On Wed, Sep 13, 2023 at 11:06:13AM +0100, Peter Robinson wrote:
Then if for development you need to pull he history of lwip, you can do it
w
On 21.09.2023 09:09, Maxim Uvarov wrote:
On Thu, 21 Sept 2023 at 07:06, Simon Glass wrote:
Hi Maxim,
On Thu, 14 Sept 2023 at 10:20, Maxim Uvarov
wrote:
add external lwIP library as a git submodule.
Oh dear...what is the motivation for using a submodule?
Our current stack is nicely in
Am 4. Oktober 2023 10:29:54 MESZ schrieb Maxim Uvarov :
>On Wed, 4 Oct 2023 at 08:12, Simon Glass wrote:
>
>> Hi Sean,
>>
>> On Tue, 3 Oct 2023 at 11:58, Sean Edmond
>> wrote:
>> >
>> >
>> > On 2023-09-26 2:41 a.m., Maxim Uvarov wrote:
>> > > Replace original commands: ping, tftp, dhcp and wge
On 10.08.2023 13:28, Maxim Uvarov wrote:
On Thu, 3 Aug 2023 at 12:42, Ilias Apalodimas
wrote:
On Wed, Aug 02, 2023 at 08:06:50PM +0600, Maxim Uvarov wrote:
Signed-off-by: Maxim Uvarov
---
lib/lwip/Makefile | 1 +
lib/lwip/apps/tftp/Makefile| 16 +
lib/lwip/apps
Hi all,
could you please remove the lwip-devel list from CC? I am interested in these
mails, but the more you dive into U-Boot specific things here, the less people
on our lwip list will be interested in this topic.
Thanks,
Simon
Am 18. August 2023 14:53:43 MESZ schrieb Maxim Uvarov :
>On Wed
On 02.04.2020 21:49, Simon Glass wrote:
Hi Marek,
On Thu, 2 Apr 2020 at 13:45, Marek Vasut wrote:
On 4/2/20 8:50 PM, Simon Glass wrote:
Hi.
Hi,
[...]
I suspect we could change this, so that
device_ofdata_to_platdata() first calls itself on its parent.
I can think of various reasons
On 02.04.2020 21:54, Marek Vasut wrote:
On 4/2/20 9:53 PM, Simon Goldschmidt wrote:
On 02.04.2020 21:49, Simon Glass wrote:
Hi Marek,
On Thu, 2 Apr 2020 at 13:45, Marek Vasut wrote:
On 4/2/20 8:50 PM, Simon Glass wrote:
Hi.
Hi,
[...]
I suspect we could change this, so that
Am 06.04.2020 um 11:18 schrieb Ley Foon Tan:
> Adding "u-boot,dm-pre-reloc" and enable CONFIG_SPL_CACHE
> to enable cache driver in SPL.
>
> This fixed error below in SPL:
> cache controller driver NOT found!
>
> Signed-off-by: Ley Foon Tan
> ---
> arch/arm/dts/socfpga_arria10-u-boot.dtsi | 4 +
On Tue, Apr 7, 2020 at 9:43 AM Ley Foon Tan wrote:
>
> Adding "u-boot,dm-pre-reloc" and enable CONFIG_SPL_CACHE
> to enable cache driver in SPL.
>
> This fixed error below in SPL:
> cache controller driver NOT found!
>
> Signed-off-by: Ley Foon Tan
Reviewed-by
On Tue, Apr 7, 2020 at 9:43 AM Ley Foon Tan wrote:
>
> Move Uboot specific properties to *u-boot.dtsi files.
> Preparation to sync Arria 10 device tree from Linux.
>
> Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt
> ---
> arch/arm/dts/socfpga_arria10-u
socfpga_arria10.dtsi:
> - Add clkmgr label, so that can reference to it in u-boot.dtsi.
>
> Change in socfpga_arria10-u-boot.dtsi:
> - Add compatible and altr,sysmgr-syscon for uboot.
>
> Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt
>
> ---
> v2: Update
Sorry if it seems I ignored this mail yesterday, I just found it now :)
On Wed, Feb 12, 2020 at 10:05 AM Stefan Roese wrote:
>
> On 12.02.20 09:57, Weijie Gao wrote:
>
>
>
> >> And more general: why do we need to code this in every loader? I think it
> >> would
> >> be preferrable to have the l
On Thu, Feb 13, 2020 at 3:53 AM Weijie Gao wrote:
>
> On Wed, 2020-02-12 at 11:18 +0100, Simon Goldschmidt wrote:
> > On Wed, Feb 12, 2020 at 9:57 AM Weijie Gao wrote:
> > >
> > > On Wed, 2020-02-12 at 09:22 +0100, Simon Goldschmidt wrote:
> > > >
On Wed, Feb 12, 2020 at 10:43 AM Weijie Gao wrote:
>
> This patch series are divided into two parts:
>
> The main part is to rewrite the whole architecture code of mt7628:
> * Lock parts of the d-cache for initial stack so the rest of the code can
> be reimplemented in C.
> * Memory controller &
On Wed, Feb 12, 2020 at 10:46 AM Weijie Gao wrote:
>
> This patch adds support for decompressing LZMA compressed u-boot payload in
> legacy uImage format.
>
> Using this patch together with u-boot-lzma.img is useful for NOR flashes as
> they can reduce the size and load time of u-boot payload.
>
>
On Thu, Feb 13, 2020 at 8:53 AM Stefan wrote:
>
> Hi Simon,
>
> On 13.02.20 08:40, Simon Goldschmidt wrote:
> > Sorry if it seems I ignored this mail yesterday, I just found it now :)
> >
> > On Wed, Feb 12, 2020 at 10:05 AM Stefan Roese wrote:
> >>
&
On Thu, Feb 13, 2020 at 9:42 AM Weijie Gao wrote:
>
> On Thu, 2020-02-13 at 08:48 +0100, Simon Goldschmidt wrote:
> > On Wed, Feb 12, 2020 at 10:43 AM Weijie Gao wrote:
> > >
> > > This patch series are divided into two parts:
> > >
> > > The mai
On Wed, Feb 12, 2020 at 6:14 PM Simon Glass wrote:
>
> Hi Masahiro,
>
> On Wed, 12 Feb 2020 at 06:14, Masahiro Yamada wrote:
> >
> > On Mon, Jan 13, 2020 at 4:08 AM Simon Glass wrote:
> > >
> > > This function name conflicts with our desire to #define free() to
> > > something else on sandbox. S
yes, I still haven't found the time to fight those size problems I
have... :-(
>
> Signed-off-by: Marek Vasut
> Cc: Ley Foon Tan
> Cc: Simon Goldschmidt
> ---
> include/configs/socfpga_common.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/include/c
On Sat, Feb 15, 2020 at 10:40 PM Marek Vasut wrote:
>
> On 2/15/20 8:39 PM, Simon Goldschmidt wrote:
> > Am 15.02.2020 um 15:02 schrieb Marek Vasut:
> >> The default timer rate may be different than 25 MHz, permit overriding
> >> the default rate in board configu
> Signed-off-by: Marek Vasut
> Cc: Ley Foon Tan
> Cc: Simon Goldschmidt
Reviewed-by: Simon Goldschmidt
> ---
> V2: Drop misleading comment
> ---
> include/configs/socfpga_common.h | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/include/
On Tue, Feb 18, 2020 at 6:53 PM Marek Vasut wrote:
>
> On 2/18/20 9:34 AM, Patrick Delaunay wrote:
> >
> > In this serie I update the DWC2 host driver to use the device tree
> > information and the associated PHY and CLOCK drivers when they are
> > availables.
> >
> > The V4 is rebased on latest m
etter solution is to define the allocation functions as 'static inline'.
This should go in before the release, as it's a regression not seen before
the last release.
A side-effect is that exports.h may not declare malloc/free. I'm not really
sure if this is correct, but for sa
etter solution is to define the allocation functions as 'static inline'.
As a side effect, exports.h must not export malloc/free for sandbox.
Signed-off-by: Simon Goldschmidt
---
A side-effect is that exports.h may not declare malloc/free. I'm not really
sure if this is correct, but
This reverts commit aae95882232a24ee49c89d0356febf3685a87c8a.
Signed-off-by: Simon Goldschmidt
---
drivers/dma/dma-uclass.c | 4 ++--
drivers/dma/sandbox-dma-test.c | 4 ++--
drivers/dma/ti/k3-udma.c | 4 ++--
include/dma-uclass.h | 4 ++--
4 files changed, 8 insertions
This reverts commit 4f51188e47921b17e6b3ce9606c8e71234c9f2df.
Signed-off-by: Simon Goldschmidt
---
drivers/power/domain/bcm6328-power-domain.c | 2 +-
drivers/power/domain/imx8-power-domain-legacy.c | 2 +-
drivers/power/domain/imx8-power-domain.c| 2 +-
drivers/power/domain/imx8m
This reverts commit fb8c0d595f1ad83bee5dd398b59b0ee16d8d15a9.
Signed-off-by: Simon Goldschmidt
---
drivers/clk/clk-ti-sci.c | 2 +-
drivers/clk/clk-uclass.c | 4 ++--
drivers/clk/clk_sandbox.c | 2 +-
drivers/clk/tegra/tegra-car-clk.c | 2 +-
include/clk-uclass.h
This reverts commit 8d38a8459b0de45f5ff41f3e11c278a5cf395fd0.
Signed-off-by: Simon Goldschmidt
---
drivers/mtd/mtdcore.c | 4 ++--
drivers/mtd/nand/raw/denali.c | 2 +-
drivers/mtd/nand/spi/core.c | 2 +-
drivers/mtd/nand/spi/gigadevice.c | 2 +-
drivers/mtd/nand/spi
This reverts commit 093152f275e036e54d48b3d9fc0adbc1ca4cc5b0.
Signed-off-by: Simon Goldschmidt
---
drivers/gpio/gpio-rcar.c | 2 +-
drivers/gpio/gpio-uclass.c | 8
include/asm-generic/gpio.h | 2 +-
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpio/gpio
This reverts commit cc92c3cc68a9053f53b2814e9233d86553cc998e.
Signed-off-by: Simon Goldschmidt
---
drivers/mailbox/k3-sec-proxy.c | 2 +-
drivers/mailbox/mailbox-uclass.c | 4 ++--
drivers/mailbox/sandbox-mbox.c | 2 +-
drivers/mailbox/stm32-ipcc.c | 2 +-
drivers/mailbox/tegra-hsp.c
This reverts commit 94474b25c3a60a746bf641a975c3db239dae29b9.
Signed-off-by: Simon Goldschmidt
---
drivers/reset/reset-bcm6345.c | 2 +-
drivers/reset/reset-hisilicon.c | 2 +-
drivers/reset/reset-hsdk.c | 2 +-
drivers/reset/reset-imx7.c | 2 +-
drivers/reset/reset-mediatek.c | 2
Am 20.02.2020 um 17:45 schrieb Marek Vasut:
> On 2/20/20 3:15 AM, Ang, Chee Hong wrote:
>>> On 2/19/20 1:25 PM, chee.hong@intel.com wrote:
From: Chee Hong Ang
SPL now loads ATF (BL31), U-Boot proper and DTB from FIT image. The
new boot flow with ATF support is as follow:
>>
Ang, Chee Hong schrieb am Sa., 22. Feb. 2020,
06:30:
> > From: Chee Hong Ang
> >
> > Allow clock manager driver to access the System Manager's Boot Scratch
> > Register 0 in non-secure mode (EL2) on SoC 64bits platform.
> >
> > Signed-off-by: Chee Hong Ang
> > ---
> > arch/arm/mach-socfpga/clo
Ang, Chee Hong schrieb am Mo., 24. Feb. 2020,
10:12:
>
>
>
>
> *From:* Ang, Chee Hong
> *Sent:* Saturday, February 22, 2020 6:00 PM
> *To:* Simon Goldschmidt
> *Cc:* U-Boot Mailing List ; Marek Vasut <
> ma...@denx.de>; See, Chin Liang ; Tan, Ley Foon
> ;
;
>
> Acked-by: Vignesh Raghavendra
>
Fine by me. I actually moved it there after someone requested me to :-) I
first had it in the set_rate function...
Acked-by: Simon Goldschmidt
>
> Regards
> Vignesh
>
> > Signed-off-by: Pratyush Yadav
> > ---
> > d
Ang, Chee Hong schrieb am Fr., 28. Feb. 2020,
03:53:
> > > On 2/24/20 3:21 AM, Ang, Chee Hong wrote:
> > > [...]
> > >
> > > > Currently, we have like 20+ secure registers allowed access by
> > > > drivers running in non-secure mode (U-Boot proper / Linux).
> > > > I don't think we wa
Am 02.03.2020 um 01:39 schrieb Jack Frye:
> I am trying to build uboot-socfpga for Terasic DE1-SoC board (Cyclone V),
> booting from SDMMC. I am unable to get u-boot to program the FPGA.
First question: which version of U-Boot are you using? Upstream sources
or Altera sources?
> I am following t
Am 18.02.2020 um 09:34 schrieb Patrick Delaunay:
> Add stub for functions clk_...() when CONFIG_CLK is desactivated.
>
> This patch avoids compilation issues for driver using these API
> without protection (#if CONFIG_IS_ENABLED(CLK))
>
> For example, before this patch we have undefined reference
;
> + }
> +
> + return 0;
> +}
> +
> +static int dwc2_shutdown_phy(struct udevice *dev)
> +{
> + struct dwc2_priv *priv = dev_get_priv(dev);
> + int ret;
> +
> + if (!generic_phy_valid(&priv->phy))
A comment saying that this is fo
Am 18.02.2020 um 09:35 schrieb Patrick Delaunay:
> Add support for clock with driver model.
>
> This patch don't added dependency because when CONFIG_CLK
> is not activated the clk function are stubbed.
>
> Signed-off-by: Patrick Delaunay
Reviewed-by: Simon Goldschmidt
Am 19.02.2020 um 08:27 schrieb Simon Goldschmidt:
> On Tue, Feb 18, 2020 at 6:53 PM Marek Vasut wrote:
>>
>> On 2/18/20 9:34 AM, Patrick Delaunay wrote:
>>>
>>> In this serie I update the DWC2 host driver to use the device tree
>>> information and the
st to be a number of milliseconds.
Fix this by dividing PHY_ANEG_TIMEOUT by 50 in this loop. This gets us
back to a 4 seconds timeout for the default value (instead of 200s).
Fixes: net: phy: Increase link up delay in genphy_update_link() ("27c3f70f3b50")
Signed-off-by: Simon Goldschmidt
Am 19.02.2020 um 21:04 schrieb Fabio Estevam:
> On Wed, Feb 19, 2020 at 4:40 PM Simon Goldschmidt
> wrote:
>>
>> This reverts commit 8d38a8459b0de45f5ff41f3e11c278a5cf395fd0.
>
> You missed to explain the reason for the revert.
Yes, I'll fix that in v2.
Regards,
Simon
Am 20.02.2020 um 04:05 schrieb Simon Glass:
> On Wed, 19 Feb 2020 at 12:39, Simon Goldschmidt
> wrote:
>>
>> Commit cfda60f99ae2 ("sandbox: Use a prefix for all allocation functions")
>> introduced preprocessor macros for malloc/free etc.
>>
>> This
On Thu, Mar 5, 2020 at 5:40 AM Stefan Roese wrote:
>
> Hi Simon,
>
> On 04.03.20 21:12, Simon Goldschmidt wrote:
> > Recently, genphy_update_link() has been changed to use a 50ms polling
> > interval instead of the previous 1ms. However, the timeout to give up
> &g
on by that factor of 50 to bring the
> >> timeout back to the intended value.
> >>
> >> Signed-off-by: Andre Przywara
A "Fixes:" tag would have been nice...
Anyway:
Tested-by: Simon Goldschmidt
> >
> > I tested this on RPi4 with the genet patche
On Fri, Mar 6, 2020 at 11:01 AM Patrick Delaunay
wrote:
>
> Add stub for functions clk_...() when CONFIG_CLK is deactivated.
>
> This patch avoids compilation issues for driver using these API
> without protection (#if CONFIG_IS_ENABLED(CLK))
>
> For example, before this patch we have undefined re
On Mon, Mar 9, 2020 at 1:57 PM Marek Vasut wrote:
>
> On 3/9/20 9:50 AM, Ley Foon Tan wrote:
> > On Thu, Feb 13, 2020 at 2:52 AM Dalon L Westergreen
> > wrote:
> >>
> >> I am reading through this thread, and want to point out that it is not
> >> that the
> >> FPGA bridge need be actively used in
On Mon, Mar 9, 2020 at 3:15 PM Marek Vasut wrote:
>
> On 3/9/20 3:10 PM, Simon Goldschmidt wrote:
> > On Mon, Mar 9, 2020 at 1:57 PM Marek Vasut wrote:
> >>
> >> On 3/9/20 9:50 AM, Ley Foon Tan wrote:
> >>> On Thu, Feb 13, 2020 at 2:52 AM Dalon L We
Am 09.03.2020 um 10:07 schrieb chee.hong@intel.com:
> From: Chee Hong Ang
>
> This driver (misc uclass) handle the read/write access to
> System Manager. For 64 bits platforms, processor needs to be
> in secure mode to has write access to most of the System Manager's
> registers (except boot
Am 10.03.2020 um 17:42 schrieb Ang, Chee Hong:
>> -Original Message-
>> From: Simon Goldschmidt
>> Sent: Wednesday, March 11, 2020 12:17 AM
>> To: Ang, Chee Hong
>> Cc: u-boot@lists.denx.de; Marek Vasut ; See, Chin Liang
>> ; Tan, Ley Foon ;
&
Am 09.03.2020 um 10:07 schrieb chee.hong@intel.com:
> From: "Ang, Chee Hong"
>
> v4 changes:
> [PATCH v4 11/21] misc: altera_sysmgr: Add Altera System Manager
> - Add System Manager driver (UCLASS_MISC) to handle secure access for SoC64
>
> [PATCH v4 13/21] mmc: dwmmc: socfpga: MMC driver ac
Am 09.03.2020 um 10:07 schrieb chee.hong@intel.com:
> From: Chee Hong Ang
>
> Enable this misc driver model for 'altera_sysmgr' driver for
> socfpga platforms.
>
> Signed-off-by: Chee Hong Ang
> ---
> arch/arm/Kconfig | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/Kco
Am 09.03.2020 um 10:07 schrieb chee.hong@intel.com:
> From: Chee Hong Ang
>
> In device tree for all socfpga platforms, a phandle to System Manager
> ('altr,sysmgr-syscon') is needed for MMC node to enable the MMC driver
> to configure the SDMMC's clock phase shift via System Manager driver
>
Am 10.03.2020 um 17:42 schrieb Ang, Chee Hong:
>> -Original Message-
>> From: Simon Goldschmidt
>> Sent: Wednesday, March 11, 2020 12:17 AM
>> To: Ang, Chee Hong
>> Cc: u-boot@lists.denx.de; Marek Vasut ; See, Chin Liang
>> ; Tan, Ley Foon ;
&
o execute
> the usb start command).
>
> Signed-off-by: Patrick Delaunay
Reviewed-by: Simon Goldschmidt
> ---
>
> Changes in v6: None
> Changes in v5: None
> Changes in v4: None
> Changes in v3: None
> Changes in v2:
> - add clk_disable_bulk in dwc2_usb_remove
&g
ndefined reference to
> `clk_disable_bulk') for code:
> clk_disable_bulk(&priv->clks);
> clk_release_bulk(&priv->clks);
>
> Signed-off-by: Patrick Delaunay
Reviewed-by: Simon Goldschmidt
> ---
>
> Changes in v6:
> - return success
().
>
> Fixes: c3c863880479 ("add FIT data-position & data-offset property support")
> Signed-off-by: Heinrich Schuchardt
Reviewed-by: Simon Goldschmidt
> ---
> common/image-fit.c | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/commo
Am 16.03.2020 um 19:04 schrieb Dalon L Westergreen:
>
>
> On Thu, 2020-03-12 at 16:57 +0100, Marek Vasut wrote:
>> On 3/12/20 4:54 PM, Dalon L Westergreen wrote:
>> [...]
>>
>> (thanks for fixing your mailer :))
>>
The problem was that this was causing weird sporadic hangs on
Ge
Am 16.03.2020 um 20:06 schrieb Marek Vasut:
> On 3/16/20 8:04 PM, Simon Goldschmidt wrote:
>> Am 16.03.2020 um 19:04 schrieb Dalon L Westergreen:
>>>
>>>
>>> On Thu, 2020-03-12 at 16:57 +0100, Marek Vasut wrote:
>>>> On 3/12/20 4:54 PM, Dalon L Wes
Am 16.03.2020 um 20:55 schrieb Dalon L Westergreen:
>
>
> On Mon, 2020-03-16 at 20:06 +0100, Marek Vasut wrote:
>> On 3/16/20 8:04 PM, Simon Goldschmidt wrote:
>>> Am 16.03.2020 um 19:04 schrieb Dalon L Westergreen:
>>>>
>>>> On Thu, 2020-03-12 at
On Wed, Oct 30, 2019 at 10:48 AM Ley Foon Tan wrote:
>
> On Tue, Oct 29, 2019 at 6:31 PM Simon Goldschmidt
> wrote:
> >
> >
> >
> > Ley Foon Tan schrieb am Di., 29. Okt. 2019, 11:16:
> >>
> >> On Fri, Oct 25, 2019 at 5:37 PM Simon Goldschmidt
Am 04.11.2019 um 20:34 schrieb Heinrich Schuchardt:
struct ip_udp_hdr is naturally packed. There is no point in adding a
__packed attribute. With the attribute the network stack does not compile
using GCC 9.2.1:
Is this commit message correct? In lwIP, we *do* need to pack all these
network he
Am 30.10.2019 um 21:34 schrieb richard.g...@linux.intel.com:
From: Richard Gong
This is 2nd submission of Intel Remote System Update patches.
Ok, so what has changed since v1? You'd normally add a changelog
(ideally to both this cover-letter and to each patch). Have a look at
patman in tool
Tom Rini schrieb am Mo., 4. Nov. 2019, 22:15:
> On Mon, Nov 04, 2019 at 09:28:51PM +0100, Simon Goldschmidt wrote:
> > Am 04.11.2019 um 20:34 schrieb Heinrich Schuchardt:
> > > struct ip_udp_hdr is naturally packed. There is no point in adding a
> > > __packed attrib
d GCC 9.2 shows this. I don't know why other
versions don't issue this warning.
This new commit message might still concentrate too much on the GCC version,
but I think it's ok. I just wanted to prevent someone reading this in the
future and taking it as a hint that the attr
Am 05.11.2019 um 17:33 schrieb Simon Glass:
Hi Jean-Jacques,
On Mon, 4 Nov 2019 at 08:41, Jean-Jacques Hiblot wrote:
On 30/10/2019 02:48, Simon Glass wrote:
On Mon, 30 Sep 2019 at 10:15, Jean-Jacques Hiblot wrote:
Add managed functions to get a reset_ctl from the device-tree, based on a
n
Hi Vignesh,
On Thu, Oct 17, 2019 at 2:31 PM Vignesh Raghavendra wrote:
>
> Hi Simon,
>
> On 17/10/19 4:50 PM, Simon Goldschmidt wrote:
> > On Mon, Oct 14, 2019 at 3:27 PM Vignesh Raghavendra wrote:
> >>
> >> Current Cadence QSPI driver has few limitations. It
On Thu, Nov 7, 2019 at 9:33 AM Marek Vasut wrote:
>
> On 11/7/19 4:31 AM, Ley Foon Tan wrote:
> > On Thu, Nov 7, 2019 at 10:49 AM Marek Vasut wrote:
> >>
> >> On 11/7/19 3:10 AM, Ley Foon Tan wrote:
> >> [...]
> >>> diff --git a/arch/arm/dts/socfpga-common-u-boot.dtsi
> >>> b/arch/arm/dts/socfpga
On Thu, Nov 7, 2019 at 9:40 AM Marek Vasut wrote:
>
> On 11/7/19 9:36 AM, Simon Goldschmidt wrote:
> > On Thu, Nov 7, 2019 at 9:33 AM Marek Vasut wrote:
> >>
> >> On 11/7/19 4:31 AM, Ley Foon Tan wrote:
> >>> On Thu, Nov 7, 2019 at 10:49 AM Marek Vasut wr
: Chin Liang See
Cc: Dalon Westergreen
Cc: Dinh Nguyen
Cc: Jagan Teki
Cc: Ley Foon Tan
Cc: Philipp Tomisch
Cc: Simon Goldschmidt
Cc: Tien Fong Chee
Reviewed-by: Simon Goldschmidt
---
V2: Use non-DM watchdog in SPL on S10
---
configs/socfpga_stratix10_defconfig | 1 +
configs
Westergreen
Cc: Dinh Nguyen
Cc: Jagan Teki
Cc: Ley Foon Tan
Cc: Philipp Tomisch
Cc: Simon Goldschmidt
Cc: Tien Fong Chee
---
V2: - Support both DM and non-DM probing
- Fix watchdog stop handling by setting CR bit
---
configs/socfpga_stratix10_defconfig | 2 +
configs
Marek Vasut schrieb am Fr., 8. Nov. 2019, 16:46:
> On 11/8/19 3:47 PM, Patrick Delaunay wrote:
> >
> > In this serie I update the DWC2 host driver to use the device tree
> > information and the associated PHY and CLOCK drivers when they are
> > available.
>
> I'm kinda on the fence whether to add
Vignesh Raghavendra schrieb am So., 10. Nov. 2019, 12:41:
> Hi Simon,
>
> On 24-Oct-19 11:53 PM, Simon Goldschmidt wrote:
> > From: Simon Goldschmidt
> >
> > Support loading clk speed via DM instead of requiring ad-hoc code.
> >
> > Signed-off-by: Simo
Heiko Schocher schrieb am Sa., 9. Nov. 2019, 05:02:
> Enable the new Kconfig option ENV_SPI_EARLY if you want
> to use Environment in SPI flash before relocation.
> Call env_init() and than you can use env_get_f() for
> accessing Environment variables.
>
> Signed-off-by: Heiko Schocher
>
> ---
>
uot; than without this patch).
Regards,
Simon
>
> Sorry.
>
> Patrick.
>
>
>
> Le ven. 8 nov. 2019 à 16:55, Simon Goldschmidt
> a écrit :
>>
>> Marek Vasut schrieb am Fr., 8. Nov. 2019, 16:46:
>>
>> > On 11/8/19 3:47 PM, Patrick Delaunay wrote:
Vignesh Raghavendra schrieb am Mo., 11. Nov. 2019, 05:22:
>
>
> On 10/11/19 5:11 PM, Vignesh Raghavendra wrote:
> > Hi Simon,
> >
> > On 24-Oct-19 11:53 PM, Simon Goldschmidt wrote:
> >> From: Simon Goldschmidt
> >>
> >> Support loa
On Mon, Nov 11, 2019 at 7:15 AM Heiko Schocher wrote:
>
> Hello Simon,
>
> Am 10.11.2019 um 15:51 schrieb Simon Goldschmidt:
> >
> >
> > Heiko Schocher mailto:h...@denx.de>> schrieb am Sa., 9. Nov.
> > 2019, 05:02:
> >
> > Enable the n
usage check")
Signed-off-by: Simon Goldschmidt
---
common/init/board_init.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/common/init/board_init.c b/common/init/board_init.c
index e52106966d..3bc7994586 100644
--- a/common/init/board_init.c
+++ b/common/init/board_init.c
Support loading clk speed via DM instead of requiring ad-hoc code.
Signed-off-by: Simon Goldschmidt
---
Changes in v3:
- load ref_clk_hz only once in cadence_spi_ofdata_to_platdata instead
of loading it every time in cadence_spi_write_speed
Changes in v2:
- check return value of clk_get_rate
On Tue, Nov 12, 2019 at 9:59 AM Tan, Ley Foon wrote:
>
>
>
> > -Original Message-
> > From: Simon Goldschmidt
> > Sent: Tuesday, November 12, 2019 5:43 AM
> > To: Jagan Teki
> > Cc: Marek Vasut ; Tan, Ley Foon
> > ; Vignesh Raghavendra ;
On Tue, Nov 12, 2019 at 10:22 AM Vignesh Raghavendra wrote:
>
>
>
> On 12/11/19 2:44 PM, Simon Goldschmidt wrote:
> > On Tue, Nov 12, 2019 at 9:59 AM Tan, Ley Foon
> > wrote:
> >>
> >>
> >>
> >>> -Original Message-
> >
Patrick Delaunay schrieb am Di., 12. Nov. 2019,
10:42:
> Add stub for clk_disable_bulk() when CONFIG_CLK is desactivated.
>
> That avoid compilation issue (undefined reference to
> `clk_disable_bulk') for code:
>
> clk_disable_bulk(&priv->clks);
> clk_release_bulk(&priv->clks);
>
> Signed-off-by:
On Tue, Nov 12, 2019 at 10:30 AM Tan, Ley Foon wrote:
>
>
>
> > -Original Message-
> > From: Simon Goldschmidt
> > Sent: Tuesday, November 12, 2019 5:27 PM
> > To: Vignesh Raghavendra
> > Cc: Tan, Ley Foon ; Jagan Teki
> > ; Marek Vasu
On Tue, Nov 12, 2019 at 12:40 PM Vignesh Raghavendra wrote:
>
>
>
> On 12/11/19 4:57 PM, Simon Goldschmidt wrote:
> > On Tue, Nov 12, 2019 at 10:30 AM Tan, Ley Foon
> > wrote:
> >>
> [...]
> >>>> But, unfortunately, such stub does not ex
Since upgrading to gcc9, warnings are issued:
"taking address of packed member of ‘...’ may result in an unaligned
pointer value"
Fix this by converting two functions to use unaligned access since packed
structures may be on an unaligned address, depending on USB hardware.
Signed-off
Since upgrading to gcc9, warnings are issued:
"taking address of packed member of ‘...’ may result in an unaligned
pointer value"
Fix this by converting dwc2_fifo_read to use unaligned access since packed
structures may be on an unaligned address, depending on USB hardware.
Signed-off
function and before get base address from DT.
Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt
---
v6:
- Call to socfpga_get_rstmgr_addr() function, instead of access to global
variable directly.
- Update socfpga_get_base_addr() to return error code, instead of return 0.
v5
Am 08.11.2019 um 03:38 schrieb Ley Foon Tan:
Convert system manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.
Change to get system manager base address from DT node instead of
using #define.
Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt
---
v6:
- Call to
Am 08.11.2019 um 03:38 schrieb Ley Foon Tan:
Convert clock manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.
Change to get clock manager base address from DT node instead of using
#define.
Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt
---
v6:
- Call to
Am 08.11.2019 um 05:11 schrieb Ley Foon Tan:
Move Stratix10 and Agilex clock manager common code to new header file.
Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt
---
v6:
- Move #include to top of header file.
v5:
- Revert CLKMGR_INTOSC_HZ to 460MHz.
---
.../include/mach
Am 08.11.2019 um 05:11 schrieb Ley Foon Tan:
CLKMGR_INTOSC_HZ should be 400MHz, instead of 460MHz.
Removed also unused macros CLKMGR_EOSC1_HZ and CLKMGR_FPGA_CLK_HZ.
Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt
---
v6:
- Remove unused macros CLKMGR_EOSC1_HZ and
Am 08.11.2019 um 05:11 schrieb Ley Foon Tan:
Restructure Stratix 10 SDRAM driver. Move common code to separate
file, in preparation to support SDRAM driver for Agilex.
Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt
---
v6:
- Remove compatible "intel,sdr-ctl-agilex"
Am 08.11.2019 um 05:11 schrieb Ley Foon Tan:
Add device tree files for Agilex SoC platform.
Based on Linux Commit ID4b36daf9ada30.
Based on? Why is this not a copy of the Linux devicetree files? The
single difference should be in *-u-boot.dtsi. Being like this, I don't
know what good
Am 08.11.2019 um 05:11 schrieb Ley Foon Tan:
Add build support for Agilex SoC.
Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt
---
v6:
- Include socfpga_soc64_common.h.
v5:
- Enable NCORE_CACHE
v3:
- Disable CONFIG_USE_TINY_PRINTF
v2:
- Remove IC_CLK define, use clock DM method
Ley Foon Tan (2):
> arm: dts: Stratix10: Fix memory node address and size cells
> configs: Stratix10: Disable CONFIG_SPL_USE_TINY_PRINTF
>
> Simon Goldschmidt (4):
> ddr: socfpga: gen5: constify altera_gen5_sdram_ops
> socfpga: fix include guard in mi
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