Use a default RCW of protocol 0x2A_0x98, and a PBI configure file which
uses CPC1 as 512KB SRAM, then PBL tool can be used on B4860 to build a
pbl boot image.
Signed-off-by: Shaohui Xie
---
board/freescale/b4860qds/b4_pbi.cfg | 27 +++
board/freescale/b4860qds/b4_rcw.cfg
From: Shaohui Xie
Provides a tool to build boot Image for PBL(Pre boot loader) which is
used on Freescale CoreNet SoCs, PBL can be used to load some instructions
and/or data for pre-initialization. The default output image is u-boot.pbl,
for more details please refer to doc/README.pblimage
ge.cfg
b/board/freescale/corenet_ds/pblimage.cfg
new file mode 100644
index 000..01003ce
--- /dev/null
+++ b/board/freescale/corenet_ds/pblimage.cfg
@@ -0,0 +1,60 @@
+#
+# Copyright 2012 Freescale Semiconductor, Inc.
+# Written-by: Shaohui Xie
+#
+# See file CREDITS for list of people who contr
000
+09010104 fffb
+09010f00 0800
+0901 8000
+#Configure LAW for CPC1
+09000d00
+09000d04 fff0
+09000d08 8113
+0910
+0914 ff00
+0918 8100
+#Initialize eSPI controller
+0911 8403
+09110020 2d170008
+09110024 0018
+09110028
Please ignore this patch. Will send a new version.
Best Regards,
Shaohui Xie
> -Original Message-
> From: shh@gmail.com [mailto:shh@gmail.com]
> Sent: Saturday, March 22, 2014 4:08 PM
> To: u-boot@lists.denx.de
> Cc: Xie Shaohui-B21989
> Subject: [PATCH] powe
Hi, York,
There is already a patch sent upstream to fix this bug, the state is under
review.
http://patchwork.ozlabs.org/patch/364807/
Best Regards,
Shaohui Xie
> -Original Message-
> From: Sun York-R58495
> Sent: Wednesday, July 23, 2014 5:16 AM
> To: Xie Shaohui-B21989
Please ignore this patch, it has some info only meaningful for Freescale.
Best Regards,
Shaohui Xie
> -Original Message-
> From: shh@gmail.com [mailto:shh@gmail.com]
> Sent: Friday, July 25, 2014 4:55 PM
> To: u-boot@lists.denx.de
> Cc: Xie Shaohui-B21989
&g
ut this information into a README file?
[S.H] OK. I'll put these information include 'hwconfig' settings into README
files of
T4QDS & T2QDS respectively.
Thanks!
Best Regards,
Shaohui Xie
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le/corenet_ds/eth_p4080.c
not necessary to add private stuff here.
Best Regards,
Shaohui Xie
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at the relocation address is always 64 KiB
> aligned even if the pre-relocation address was not.
>
> Use the GOT to get the proper post-relocation offsets.
>
> Fixes: 96d2bb952bb ("powerpc/mpc85xx: Don't relocate exception vectors")
> Signed-off-by
Tested on T4240QDS_NAND and T4240QDS_SDCARD, the hang issue fixed.
Thanks!
Best Regards,
Shaohui Xie
> -Original Message-
> From: Wood Scott-B07421
> Sent: Friday, April 24, 2015 9:02 AM
> To: u-boot@lists.denx.de; Sun York-R58495
> Cc: Wood Scott-B07421; Alexander Gr
> On 04/27/2015 12:28 AM, shh@gmail.com wrote:
> > From: Shaohui Xie
> >
> > 1. board/freescale/t4qds/t4_rcw.cfg
> > 1.8GHz support is requested as default frequency, so update the rcw.
> >
> > 2. remove un-used configs
> > co
the
<10g_mac_name> of the port in hwconfig, otherwise, fiber cable will be
assumed to be used for the port.
For ex. if four XFI ports will both use copper cable, the hwconfig
should contain:
fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm1_10g3,fm1_10g4
Signed-off-by: Shaohui Xie
---
changes for V2
Hz for SGMII mode
right setting of SERDES Reference Clocks Bank2:
SW2[5:6] = OFF OFF =>100MHz for PCI mode
SW2[5:6] = OFF ON =>125MHz for SGMII mode
SW2[5:6] = ON OFF =>156.25MHZ
Signed-off-by: Shaohui Xie
---
board/freescale/p2041rdb/p2041rdb.c | 25 +++
ENV location compile logic is wrong, and when CONFIG_SYS_NO_FLASH is defined
and non-NOR u-boot is building, it will cause compile error. Also, add
CONFIG_SYS_FLASH_USE_BUFFER_WRITE for p2041, which will improve NOR flash
write performance.
Signed-off-by: Shaohui Xie
---
include/configs
fsl_ddr_get_dimm_params() should be wrapped by
CONFIG_SYS_DDR_RAW_TIMING, otherwise, when using fixed_sdram() instead of
using SPD, it will cause compile error.
Signed-off-by: Shaohui Xie
Acked-by: York Sun
---
arch/powerpc/cpu/mpc8xxx/ddr/main.c |2 +-
1 files changed, 1 insertions(+), 1
ned-off-by: Shaohui Xie
Acked-by: Timur Tabi
---
board/freescale/p2041rdb/eth.c | 39 +++
1 files changed, 39 insertions(+), 0 deletions(-)
diff --git a/board/freescale/p2041rdb/eth.c b/board/freescale/p2041rdb/eth.c
index 4b0d577..fec9777 100644
--- a/board
hould be a NAND partition, the file 'file-jffs2' should be
page aligned.
Signed-off-by: Shaohui Xie
---
resent due to patch work did not capture the patch.
arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 +++
arch/powerpc/cpu/mpc85xx/cpu_init.c | 10 ++
arch/powerpc/include/
hould be a NAND partition, the file 'file-jffs2' should be
page aligned.
Signed-off-by: Shaohui Xie
---
Sorry!
I have to resent since I still cannot find the patch in patch work.
arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 +++
arch/powerpc/cpu/mpc85xx/cpu_init.c | 10 ++
That the pblimage can be built according to the SYS_TEXT_BASE, then building a
different size of pblimage is available.
Signed-off-by: Shaohui Xie
---
tools/pblimage.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/tools/pblimage.c b/tools/pblimage.c
index 508a747
which allow a device have mutilple liodns.
Reported-and-tested-by: Diana CRACIUN
Signed-off-by: Shaohui Xie
---
arch/powerpc/cpu/mpc85xx/liodn.c | 20 +---
arch/powerpc/cpu/mpc85xx/p2041_ids.c |8
arch/powerpc/cpu/mpc85xx/p3041_ids.c |8
arch/power
CPLD 2.0 provides a new register which bit[0] is set to '1' will reset board
with initializing the CPLD registers to default values. And add bit[6] of
register at offset 0x5 to use to enable flash bank selection .
Signed-off-by: Shaohui Xie
---
board/freescale/p2041rdb/cpl
P2041RDB supports 3 sysclk frequencies, it's selected by SW1[6~8], software
need to read the SW1 status to decide what the sysclk needs.
SW1[8~6] : frequency
0 0 1 : 83.3MHz
0 1 0 : 100MHz
others: 66.667MHz
Signed-off-by: Shaohui Xie
---
board/freescale/p2041rdb/cpld.h |3 +++
This table covers DDR frequencies from 666 to 1666. Frequencies 666, 833, 1000,
1066 and 1333 were verified on this board with SO-DIMM (UG51U6400N8SU-ACF).
Signed-off-by: Shaohui Xie
---
board/freescale/p2041rdb/ddr.c |5 -
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a
013
+0910
+0914 ff00
+0918 8100
+#Initialize eSPI controller
+0911 8403
+09110020 2d170008
+09110024 0018
+09110028 0018
+0911002c 0018
+#Flush PBL data
+09138000
+091380c0
+
+
+Author:
Lanes mux currently is configured in eth.c when initializing FMAN ethernet
ports, but SRIO and PCIe also need lanes mux, so we move the lanes mux to
p2041rdb.c which implements a board-specific initialization and will be
called at early stage.
Signed-off-by: Shaohui Xie
---
board/freescale
TN80xx has same PHY ID as TN2020, but it needs different setting to register
30.93 which used to select line, so we read register 30.32 which has
bit 15:12 to indicate PHY hardware version, for TN20xx we will get 3 or 2,
for TN80xx we will get 5 or 4.
Signed-off-by: Shaohui Xie
---
drivers/net
Signed-off-by: Shaohui Xie
---
boards.cfg |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/boards.cfg b/boards.cfg
index 8cf4936..314afa2 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -856,6 +856,7 @@ P5020DS_SPIFLASH powerpc mpc85xx corenet_ds
Signed-off-by: Shaohui Xie
---
boards.cfg |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/boards.cfg b/boards.cfg
index e4b0d44..8cf4936 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -855,6 +855,7 @@ P5020DS_SECURE_BOOT powerpc mpc85xx
corenet_ds
Signed-off-by: Shaohui Xie
---
boards.cfg |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/boards.cfg b/boards.cfg
index 314afa2..710942f 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -857,6 +857,7 @@ P5020DS_SRIO_PCIE_BOOT powerpc mpc85xx
corenet_ds
Provided a default RCW for P5040, then it can use PBL to build
ramboot image.
Signed-off-by: Shaohui Xie
---
board/freescale/corenet_ds/rcw_p5040ds.cfg | 11 +++
include/configs/corenet_ds.h |2 ++
2 files changed, 13 insertions(+), 0 deletions(-)
create mode 100644
Also update README.pblimage for p5040.
Signed-off-by: Shaohui Xie
---
changes for v2:
1. merge NAND/SD/SPI to one patch;
2. update README.pblimage for p5040;
boards.cfg |3 +++
doc/README.pblimage |6 +++---
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a
From: shaohui xie
TBI PHY address (TBIPA) register is set in general frame manager
phy init funciton dtsec_init_phy() in drivers/net/fm/eth.c, and
it is supposed to set TBIPA on FM1@DTSEC1 in case of FM1@DTSEC1
isn't used directly, which provides MDIO for other ports. So
following code is
ngth check for write command is not
necessary for SPANSION, though it's harmless for SPANSION, it will stop write
operation on flashes like SST, so we remove the check.
Signed-off-by: Shaohui Xie
---
drivers/spi/fsl_espi.c |6 ++
1 files changed, 2 insertions(+), 4 deletions(-)
diff --git
Add env in NAND support when boot from NAND.
Signed-off-by: Shaohui Xie
---
include/configs/P2041RDB.h |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 501726c..fe39d4e 100644
--- a/include/configs
New P2041RDB board will add a NAND chip, so add support for NAND and
NAND boot.
Signed-off-by: Shaohui Xie
---
boards.cfg |1 +
include/configs/P2041RDB.h | 54 +--
2 files changed, 52 insertions(+), 3 deletions(-)
diff --git a
PC board has different serdes clock setting with PB board, it uses same
serdes frequency setting on bank2 as on bank1. PC board can be distingushed
from PB board by checking CPLD version, if running on PC board, then fix
the serdes reference clock frequency of bank2.
Signed-off-by: Shaohui Xie
When CONFIG_SYS_FSL_QORIQ_CHASSIS2 is not defined, QMAN frequency will not
be initialized, and QMAN will have a wrong frequency display.
Signed-off-by: Shaohui Xie
---
arch/powerpc/cpu/mpc85xx/speed.c |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/cpu
PC board has different serdes clock setting with PB board, it uses same
serdes frequency setting on bank2 as on bank1. PC board can be distingushed
from PB board by checking CPLD version, if running on PC board, then fix
the serdes reference clock frequency of bank2.
Signed-off-by: Shaohui Xie
hould be a NAND partition, the file 'file-jffs2' should be
page aligned.
Signed-off-by: Shaohui Xie
---
arch/powerpc/cpu/mpc85xx/cmd_errata.c |3 +++
arch/powerpc/cpu/mpc85xx/cpu_init.c | 10 ++
arch/powerpc/include/asm/config_mpc85xx.h |4
3 files changed, 17 i
we use dynamic index for 10G ports instead of hardcoded enum value
when doing mdio mux for 10G ports.
Signed-off-by: Shaohui Xie
---
board/freescale/corenet_ds/eth_superhydra.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/board/freescale/corenet_ds
, we change the default setting to peripheral mode. Ideally,
we'd set it to OTG mode, but currently there is no OTG support for
these boards.
Setting the hwconfig variable will also update the device tree, and so
Linux will configure the port for peripheral mode as well.
Signed-off-by: Sh
T4240QDS uses a SST instead of SPANSION SPI flash.
Signed-off-by: Shaohui Xie
---
include/configs/t4qds.h |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h
index d58c24c..b3eaf5d 100644
--- a/include/configs/t4qds.h
+++ b
Signed-off-by: Shaohui Xie
Signed-off-by: Roy Zang
---
include/configs/t4qds.h |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h
index b3eaf5d..5f0286d 100644
--- a/include/configs/t4qds.h
+++ b/include/configs
1. use Payload length check disable when enable MAC;
2. add XGMII support for setting MAC interface mode;
3. only enable auto negotiation for Non-XGMII mode;
4. return 0x if clause 22 is used to read 10G phy_id;
Signed-off-by: Shaohui Xie
Signed-off-by: Roy Zang
---
arch/powerpc/include
The VSC8574 is a quad-port Gigabit Ethernet transceiver with four SerDes
interfaces for quad-port dual media capability. This driver supports SGMII
and QSGMII MAC mode. For now SGMII mode is tested.
Signed-off-by: Roy Zang
Signed-off-by: Shaohui Xie
---
drivers/net/phy/vitesse.c | 67
-off-by: Mingkai Hu
Signed-off-by: Shaohui Xie
---
Use CONFIG_RAMBOOT_PBL instead of CONFIG_PBL_BOOT_INDIRECT according to Kumar's
comment.
arch/powerpc/cpu/mpc85xx/cpu_init.c | 19 +++
board/freescale/corenet_ds/config.mk |6 ++
board/freescale/corenet_ds/
From: Mingkai Hu
Signed-off-by: Mingkai Hu
Singed-off-by: Jerry Huang
Signed-off-by: Shaohui Xie
Cc: Mike Frysinger
---
changes for v2:
remove #ifdef wrapper and refactor spi_xfer by use SPI_XFER(BEGIN | END).
remove 'volatile' use I/O accessors instead.
drivers/spi/Makefil
espi flash read returns invalid data if the read length is more than 0xFFFA
bytes, it supports maximum transaction of 2^16 bytes at a time, resister
spcom[TRANLEN] is 16 bits. If the transaction length is greater than 0x,
it need to be split into multiple transactions.
Signed-off-by: Shaohui
Signed-off-by: Shaohui Xie
Cc: Mike Frysinger
---
drivers/mtd/spi/spansion.c |9 +
1 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/spi/spansion.c b/drivers/mtd/spi/spansion.c
index a3401b3..8835e96 100644
--- a/drivers/mtd/spi/spansion.c
+++ b/drivers/mtd
From: Mingkai Hu
Signed-off-by: Mingkai Hu
Singed-off-by: Jerry Huang
Signed-off-by: Shaohui Xie
Cc: Mike Frysinger
---
changes for v2:
remove #ifdef wrapper and refactor spi_xfer by use SPI_XFER(BEGIN | END).
remove 'volatile' use I/O accessors instead.
changes for v3:
mo
espi flash read returns invalid data if the read length is more than 0xFFFA
bytes, it supports maximum transaction of 2^16 bytes at a time, resister
spcom[TRANLEN] is 16 bits. If the transaction length is greater than 0x,
it need to be split into multiple transactions.
Signed-off-by: Shaohui
From: Mingkai Hu
Signed-off-by: Mingkai Hu
Singed-off-by: Jerry Huang
Signed-off-by: Shaohui Xie
Cc: Mike Frysinger
changes for v2:
remove #ifdef wrapper and refactor spi_xfer by use SPI_XFER(BEGIN | END).
remove 'volatile' use I/O accessors instead.
changes for v3:
mo
From: Mingkai Hu
Signed-off-by: Mingkai Hu
Singed-off-by: Jerry Huang
Signed-off-by: Shaohui Xie
Cc: Mike Frysinger
---
changes for v2:
remove #ifdef wrapper and refactor spi_xfer by use SPI_XFER(BEGIN | END).
remove 'volatile' use I/O accessors instead.
changes for v3:
mo
Signed-off-by: Shaohui Xie
Signed-off-by: Kumar Gala
---
include/configs/corenet_ds.h | 10 ++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index d1cda15..561f3c2 100644
--- a/include/configs/corenet_ds.h
Signed-off-by: Shaohui Xie
---
board/freescale/common/Makefile |2 ++
boards.cfg |7 ++-
include/configs/corenet_ds.h| 30 ++
3 files changed, 30 insertions(+), 9 deletions(-)
diff --git a/board/freescale/common/Makefile b/board
When booting from NAND we get the environment from NAND.
Signed-off-by: Shaohui Xie
Signed-off-by: Kumar Gala
---
boards.cfg |2 ++
include/configs/corenet_ds.h | 29 +++--
2 files changed, 25 insertions(+), 6 deletions(-)
diff --git a
When booting from NAND we get the environment from NAND.
Signed-off-by: Shaohui Xie
Signed-off-by: Kumar Gala
---
changes for v2:
move _NAND up to sorted by alpha.
boards.cfg |2 ++
include/configs/corenet_ds.h | 29 +++--
2 files changed, 25
Signed-off-by: Shaohui Xie
---
arch/powerpc/cpu/mpc8xxx/fdt.c |3 ++-
board/freescale/corenet_ds/corenet_ds.c |1 +
include/configs/corenet_ds.h|2 ++
3 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu
to make USB2 worked in gadget mode, we need to set it's 'dr_mode' to
'peripheral' in hwconfig, but driver starts scan from 'usb1', it'll break
if it cannot find 'usb1', so we need to tell driver do not break until it
scaned all the 'usb
to make USB2 worked in gadget mode, we need to set it's 'dr_mode' to
'peripheral' in hwconfig, but driver starts scan from 'usb1', it'll break
out if it cannot find 'usb1', so drop the 'else' clause to make driver scan
all the 'usbx
B controllers,
hardcoded compat is limited to handle this, so add compat "fsl-usb2-mph"
handle in the API.
Signed-off-by: Shaohui Xie
---
arch/powerpc/cpu/mpc8xxx/fdt.c | 40 +++-
1 files changed, 19 insertions(+), 21 deletions(-)
diff --git a/a
d bank2,
RevC(x) board has different clock setting on two banks, PCBA can
be used to distinguish the boards, PCBA could be increased on
RevD(x) board in future, but RevC(x) board will never has PCBA > 4.
Signed-off-by: Shaohui Xie
---
board/freescale/p2041rdb/p2041rdb.c | 15 ++-
d bank2,
RevC(x) board has different clock setting on two banks, PCBA can
be used to distinguish the boards, PCBA could be increased on
RevD(x) board in future, but RevC(x) board will never has PCBA > 4.
Signed-off-by: Shaohui Xie
---
board/freescale/p2041rdb/p2041rdb.c | 15 ++-
nstalled on board is 8514.
Best Regards,
Shaohui Xie
> -Original Message-
> From: Sharma Bhupesh-B45370
> Sent: Wednesday, November 20, 2013 4:31 PM
> To: 'shh@gmail.com'; 'u-boot@lists.denx.de'; sun york-R58495
> Cc: Xie Shaohui-B21989; Goel Arpit
00 AM, shh@gmail.com wrote:
> > From: Shaohui Xie
> >
> > fixed-link is used in kernel for PHY-less MAC, so introduce this
> > structure that U-boot can use it to fixup dtb dynamically.
> >
> > Signed-off-by: Shaohui Xie
> > ---
> > include/phy.
Since the parameters need to be modified according to different Serdes
protocols at runtime, the const will block this.
Signed-off-by: Shaohui Xie
---
board/freescale/common/vsc3316_3308.c | 2 +-
board/freescale/common/vsc3316_3308.h | 2 +-
board/freescale/t4qds/t4qds.c | 8
Since the parameters need to be modified according to different Serdes
protocols at runtime, the const will block this.
Signed-off-by: Shaohui Xie
---
board/freescale/common/vsc3316_3308.c | 2 +-
board/freescale/common/vsc3316_3308.h | 2 +-
board/freescale/t4qds/t4qds.c | 8
Since the parameters need to be modified according to different Serdes
protocols at runtime, the const will block this.
Signed-off-by: Shaohui Xie
---
board/freescale/common/vsc3316_3308.c | 2 +-
board/freescale/common/vsc3316_3308.h | 2 +-
board/freescale/t4qds/t4qds.c | 8
Since the parameters need to be modified according to different Serdes
protocols at runtime, the const will block this. Also remove const from
arrays define used by vsc3316_config.
Signed-off-by: Shaohui Xie
---
changes for V2:
1. changed subject;
2. fix broken on B4xxx boards;
board/freescale
When using QSGMII protocols, the first lane and third lane on each slot
need to be swapped.
Signed-off-by: Shaohui Xie
---
board/freescale/t4qds/t4qds.c | 39 +--
1 file changed, 37 insertions(+), 2 deletions(-)
diff --git a/board/freescale/t4qds/t4qds.c b
Also some fix for QSGMII.
1. fix QSGMII configure of Serdes2.
2. fix PHY address of QSGMII MAC9 & MAC10 for each FMAN.
3. fix dtb for QSGMII interface.
Signed-off-by: Shaohui Xie
---
arch/powerpc/cpu/mpc85xx/t4240_serdes.c | 14 +++---
board/freescale/t4qds/eth.c |
Since the parameters need to be modified according to different Serdes
protocols at runtime, the const will block this. Also remove const from
arrays define used by vsc3316_config.
Signed-off-by: Shaohui Xie
---
changes for V3:
1. rebased on top of master branch.
changes for V2:
1. changed
From: Shaohui Xie
Since the parameters need to be modified according to different Serdes
protocols at runtime, the const will block this. Also remove const from
arrays define used by vsc3316_config.
Signed-off-by: Shaohui Xie
---
changes for V3:
1. rebased on top of master branch.
changes for
From: Shaohui Xie
When using QSGMII protocols, the first lane and third lane on each slot
need to be swapped.
Signed-off-by: Shaohui Xie
---
resend for patchwork to catch.
board/freescale/t4qds/t4240qds.c | 39 -
1 files changed, 37 insertions(+), 2
From: Shaohui Xie
Also some fix for QSGMII.
1. fix QSGMII configure of Serdes2.
2. fix PHY address of QSGMII MAC9 & MAC10 for each FMAN.
3. fix dtb for QSGMII interface.
Signed-off-by: Shaohui Xie
---
resend for patchwork to catch.
arch/powerpc/cpu/mpc85xx/t4240_serdes.c | 14 +++---
b
Without this patch, SPD access will fail which leads to DDR init fail.
Signed-off-by: Shaohui Xie
---
include/configs/P2041RDB.h |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 905bacf..862614b 100644
-off-by: Mingkai Hu
Signed-off-by: Shaohui Xie
Signed-off-by: Roy Zang
---
arch/powerpc/cpu/mpc85xx/cpu_init.c | 19 +++
board/freescale/corenet_ds/tlb.c| 12 +++-
boards.cfg |1 +
include/configs/corenet_ds.h| 27
The tool can build u-boot image which can be used by PBL,
run "make P4080DS_RAMBOOT_PBL" can make all works done,
the default output image is u-boot.pbl, for more details
please refer to doc/README.pblimage.
Signed-off-by: Shaohui Xie
---
Makefile|
From: Mingkai Hu
This patch add espi support which is from MPC8536, and fixed some hunk
failed error, and rebased on Mike's sf unify patches.
Signed-off-by: Mingkai Hu
Singed-off-by: Jerry Huang
Signed-off-by: Shaohui Xie
Cc: Mike Frysinger
---
this patch is rebased on Mike'
espi flash read returns invalid data if the read length is more than 0xFFFA
bytes, it supports maximum transaction of 2^16 bytes at a time, resister
spcom[TRANLEN] is 16 bits. If the transaction length is greater than 0x,
it need to be split into multiple transactions.
Signed-off-by: Shaohui
Signed-off-by: Shaohui Xie
---
drivers/mtd/spi/eon.c |8
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/spi/eon.c b/drivers/mtd/spi/eon.c
index 806b44e..4c64494 100644
--- a/drivers/mtd/spi/eon.c
+++ b/drivers/mtd/spi/eon.c
@@ -41,6 +41,14 @@ static const
Please ignore this patch, I just saw some Freescale internal changes, the patch
is obsolete.
Best Regards,
Shaohui Xie
> -Original Message-
> From: shh@gmail.com [mailto:shh@gmail.com]
> Sent: Tuesday, November 10, 2015 7:12 PM
> To: u-boot@lists.denx.de; Sun York
> -Original Message-
> From: York Sun [mailto:york...@freescale.com]
> Sent: Thursday, November 26, 2015 1:03 AM
> To: Xie Shaohui-B21989; Ciubotariu Codrin Constantin-B43658
> Cc: Yuanzheng Li; u-boot@lists.denx.de; Liu Dave-R63238
> Subject: Re: [PATCH] eth: dtsec: fix TBI ANA setting bug
ubject: Re: [Patch v2 07/16] net/fm: fix MDIO controller base on FMAN2
>
> On Thu, 2015-09-17 at 15:06 +0800, Gong Qianyu wrote:
> > From: Shaohui Xie
> >
> > MDIO controller base on FMAN2 was defined as CONFIG_SYS_FSL_FM2_ADDR
> > plus offset, but CONFIG_SYS_FSL_FM2
istinguish SGMII from other connections should be the way to program TBI
ANA,
This is also follow the AN3869.
Best Regards,
Shaohui Xie
> -Original Message-
> From: York Sun [mailto:york...@freescale.com]
> Sent: Monday, December 14, 2015 11:55 AM
> To: 李远正; Xie Shaohui-B
> -Original Message-
> From: Gong Qianyu [mailto:qianyu.g...@nxp.com]
> Sent: Thursday, December 24, 2015 4:40 PM
> To: u-boot@lists.denx.de
> Cc: Mingkai Hu; r58...@freescale.com; b48...@freescale.com;
> shaohui@freescale.com; wenbin.s...@freescale.com;
> b07...@freescale.com; Gong Qia
Signed-off-by: Shaohui Xie
---
doc/README.espi-boot-p4080ds | 82 ++
1 files changed, 82 insertions(+), 0 deletions(-)
create mode 100644 doc/README.espi-boot-p4080ds
diff --git a/doc/README.espi-boot-p4080ds b/doc/README.espi-boot-p4080ds
new file
Signed-off-by: Mingkai Hu
Signed-off-by: Shaohui Xie
---
arch/powerpc/cpu/mpc85xx/cpu_init.c | 25 +
board/freescale/corenet_ds/config.mk | 6 ++
board/freescale/corenet_ds/tlb.c |9 +
boards.cfg |1 +
include/configs
PBL: SPI flash used as RCW and PBI source, CPC used as 1M SRAM
where PBL will copy whole U-BOOT image to, U-boot can boot from CPC
after PBL completes RCW and PBI phases.
Signed-off-by: Chunhe Lan
Signed-off-by: Mingkai Hu
Signed-off-by: Shaohui Xie
---
arch/powerpc/cpu/mpc85xx/cpu_init.c
Signed-off-by: Shaohui Xie
---
doc/README.espi-boot-p4080ds | 85 ++
1 files changed, 85 insertions(+), 0 deletions(-)
create mode 100644 doc/README.espi-boot-p4080ds
diff --git a/doc/README.espi-boot-p4080ds b/doc/README.espi-boot-p4080ds
new file
Hello Joe,
Thank you for reviewing this patch!
Please see inline.
Best Regards,
Shaohui Xie
From: Joe Hershberger [mailto:joe.hershber...@gmail.com]
Sent: Friday, March 20, 2015 2:04 AM
To: Sun York-R58495
Cc: u-boot; Joe Hershberger; Xie Shaohui-B21989
Subject: Re: [U-Boot] [PATCH 15/28] net
> > /* IFC */
> > #define CONFIG_SYS_FSL_IFC_LE
> > +#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
>
> It seems tedious to have to define this. Can't you just use the functions
> available?
>
> [S.H] To use a define is based on a concern that we cannot assume the I/O
> access of an IP share same end
> On 08/25/2015 01:30 AM, shh@gmail.com wrote:
> > From: Shaohui Xie
> >
> > A U-boot CMD vdd_read is implemented to read Core voltage.
>
> Can you explain why you need this command? You already get the voltage if
> you run bdinfo. If you override vdd, you al
Hi Ying,
The commit message should be more clear about what is wrong.
Like when using protocols to support 10G on MAC9 and MAC10, these
MACs should not be identified as 1G interface, otherwise, one MAC will be
Listed as two Ethernet ports, for ex. MAC9 will be listed as FM1@TGEC1
And FM1@DTSEC9.
This patch series are based on patch:
http://patchwork.ozlabs.org/patch/409932/
Best Regards,
Shaohui Xie
> -Original Message-
> From: shh@gmail.com [mailto:shh@gmail.com]
> Sent: Thursday, November 13, 2014 11:26 AM
> To: u-boot@lists.denx.de; Sun York-R58495
>
> -Original Message-
> From: york sun
> Sent: Saturday, August 27, 2016 12:08 AM
> To: Qianyu Gong ; u-boot@lists.denx.de
> Cc: Prabhakar Kushwaha ; Mingkai Hu
> ; Shaohui Xie ; Zhiqiang Hou
> ; Wenbin Song
> Subject: Re: [PATCH 7/8] armv8: ls1046a: disable SATA E
> On 08/26/2016 04:40 AM, Gong Qianyu wrote:
> > From: Shaohui Xie
> >
> > The CONFIG_STANDALONE_LOAD_ADDR is set to 0x8030 by default.
> >
> > Signed-off-by: Shaohui Xie
> > Signed-off-by: Gong Qianyu
> > ---
> > arch/arm/include/asm/arch
> -Original Message-
> From: Joe Hershberger [mailto:joe.hershber...@gmail.com]
> Sent: Wednesday, January 27, 2016 11:37 PM
> To: shaohui 谢
> Cc: u-boot ; Joe Hershberger ;
> Shaohui Xie ; York Sun
> Subject: Re: [U-Boot] [PATCH 1/2] net: phy: introduce a quirk PHY
The settings for 2.5G SGMII are wrong, which the 2.5G case is missed in
set_if_mode(), and the serdes PCS configuration are wrong, this patch uses
the correct settings took from Linux.
Signed-off-by: Shaohui Xie
---
not sure what was wrong, the patch did not show in patchwork, so resend it
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