On Mon, 2023-11-06 at 12:56 +0100, Michal Simek wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
>
> MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP.
> It is hardware compatible with classic MicroBlaze processor.
>
> The patc
From: Padmarao Begari
This patch adds Microchip MPFS Icicle Kit support. For now, only
NS16550 Serial, Microchip clock, Cadence eMMC and MACB drivers are
only enabled. The Microchip MPFS Icicle defconfig by default builds
U-Boot for S-Mode because U-Boot on Microchip PolarFire SoC will run
in S-M
From: Padmarao Begari
Add device tree for Microchip PolarFire SoC Icicle Kit.
Signed-off-by: Padmarao Begari
---
arch/riscv/dts/Makefile | 1 +
arch/riscv/dts/microchip-icicle-kit-a000.dts | 419 +++
2 files changed, 420 insertions(+)
create mode 100644
From: Padmarao Begari
This patch set adds Microchip PolarFire SoC Icicle Kit support
to RISC-V U-Boot.
The patches are based upon latest U-Boot tree
(https://gitlab.denx.de/u-boot/u-boot.git) at commit id
9dc6aef8c963ae17e1263b89c692792fce0c7198
All drivers namely: NS16550 Serial, Microchip clo
From: Padmarao Begari
Add indexes for reset and clock control signals within the system register
module of the Microchip PolarFire SoC.
Signed-off-by: Padmarao Begari
---
.../dt-bindings/clock/microchip,pfsoc-clock.h | 45 +++
1 file changed, 45 insertions(+)
create mode 10064
From: Padmarao Begari
Read phy address from device tree and use it to find the phy device
if not found then search in the range of 0 to 31.
Signed-off-by: Padmarao Begari
---
drivers/net/macb.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/net/macb.c b/drivers/ne
From: Padmarao Begari
Enable 64-bit DMA support in the macb driver when CONFIG_DMA_ADDR_T_64BIT
is enabled. 32-bit DMA is enabled by default.
Signed-off-by: Padmarao Begari
---
drivers/net/macb.c | 42 +++---
drivers/net/macb.h | 6 ++
2 files changed,
From: Padmarao Begari
dma_addr_t holds any valid DMA address. If the DMA API only uses 32/64-bit
addresses, dma_addr_t need only be 32/64 bits wide.
Signed-off-by: Padmarao Begari
---
arch/riscv/Kconfig | 5 +
arch/riscv/include/asm/types.h | 4
2 files changed, 9 insertio
From: Padmarao Begari
Add clock driver code for the Microchip PolarFire SoC. This driver
handles reset and clock control of the Microchip PolarFire SoC device.
Signed-off-by: Padmarao Begari
---
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 1 +
Hi Conor,
> On Wed, 2022-10-19 at 16:57 +0100, Conor Dooley wrote:
>
> On Wed, Oct 19, 2022 at 08:23:19PM +0530, Padmarao Begari wrote:
> > In the v2022.10 Icicle reference design, the seg registers are
> > going to be
> > changed, resulting in a required change to the memory map.
> > A small 4MB
Hi Tudor,
> On Wed, 2022-10-19 at 15:28 +, Tudor Ambarus - M18064 wrote:
> On 10/19/22 17:53, Padmarao Begari wrote:
> > + flash0: spi-nand@0 {
>
> the node should have generic name according to the dt specification,
> so please s/spi-nand/flash.
>
Ok, will use "flash"
Regards
Padmar
Hi Conor,
> On Wed, 2022-10-19 at 16:59 +0100, Conor Dooley wrote:
>
> On Wed, Oct 19, 2022 at 08:23:20PM +0530, Padmarao Begari wrote:
>
> > riscv: dts: Add QSPI NAND device node
>
> I didn't notice this on 1/3, but I think we need to mention which
> board
> that this is being added for in the
Hi Conor,
> On Wed, 2022-10-19 at 16:47 +0100, Conor Dooley wrote:
>
> On Wed, Oct 19, 2022 at 03:16:01PM +, tudor.amba...@microchip.com
> wrote:
> > Hi!
> >
> > On 10/19/22 17:53, Padmarao Begari wrote:
> > > drivers/spi/microchip_qspi.c | 504
> > > +++
> >
Hi Conor,
> On Wed, 2022-10-19 at 17:20 +0100, Conor Dooley wrote:
>
> On Wed, Oct 19, 2022 at 08:23:22PM +0530, Padmarao Begari wrote:
> > Add QSPI driver code for the Microchip PolarFire SoC.
> > This driver supports the qspi standard, dual and quad
> > mode interfaces.
> >
> > Signed-off-by:
On Sat, 2022-10-22 at 12:21 +0100, Conor Dooley wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
>
> On Fri, Oct 21, 2022 at 12:29:19PM +0530, Padmarao Begari wrote:
> > In the v2022.10 Icicle reference design, the seg registers are
> > going to
Hi Conor,
> On Tue, 2022-10-25 at 19:50 +, Conor Dooley - M52691 wrote:
> On 22/10/2022 12:21, Conor Dooley wrote:
> >
> > On Fri, Oct 21, 2022 at 12:29:19PM +0530, Padmarao Begari wrote:
> > > In the v2022.10 Icicle reference design, the seg registers are
> > > going to be
> >
> > Hey Padma
On Sat, 2022-10-22 at 12:46 +0100, Conor Dooley wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
>
> On Fri, Oct 21, 2022 at 12:29:21PM +0530, Padmarao Begari wrote:
> > Add QSPI driver code for the Microchip PolarFire SoC.
> > This driver suppo
> On Wed, 2022-10-26 at 08:49 +0100, Conor Dooley wrote:
> A late ack is currently being sent at the end of a transfer due to
> incorrect logic in mchp_corei2c_empty_rx(). Currently the Assert Ack
> bit is being written to the controller's control reg after the last
> byte has been received, causin
> On Wed, 2022-10-26 at 08:49 +0100, Conor Dooley wrote:
> "Master receive mode" was not correctly sending ACKs/NACKs in the
> interrupt handler. Bring the handling of M_SLAR_ACK, M_RX_DATA_ACKED
> &
> M_RX_DATA_NACKED in line with the Linux driver.
>
> Fixes: 0dc0d1e094 ("i2c: Add Microchip Polar
Hi Conor,
> On Wed, 2022-10-26 at 07:54 +, Conor Dooley - M52691 wrote:
> On 26/10/2022 08:49, Conor Dooley wrote:
> > A late ack is currently being sent at the end of a transfer due to
> > incorrect logic in mchp_corei2c_empty_rx(). Currently the Assert
> > Ack
> > bit is being written to the
> On Tue, 2022-10-25 at 08:58 +0100, Conor Dooley wrote:
> When this binding header was initally upstreamed, the PLL clocking
> the
> microprocessor subsystem (MSS) and the RTC reference clocks were
> omitted. Add them now, matching the IDs used in Linux.
>
> Signed-off-by: Conor Dooley
> ---
>
Hi Conor,
> On Tue, 2022-10-25 at 08:58 +0100, Conor Dooley wrote:
> Currently the clock driver for PolarFire SoC takes a very naive
> approach
> to the relationship between clocks. It reads the dt to get an input
> clock, assumes that that is fixed frequency, reads the "clock-
s/that that/that
>
> On Tue, 2022-10-25 at 08:58 +0100, Conor Dooley wrote:
> The original devicetrees for PolarFire SoC messed up & defined the
> msspll's output as a fixed-frequency, 600 MHz clock & used that as
> the
> input for the clock controller node. The msspll is not a fixed
> frequency clock and later devic
> On Tue, 2022-10-25 at 08:58 +0100, Conor Dooley wrote:
> Not all "periph" clocks are children of the AHB clock, some have the
> AXI
> clock as their parent & the mtimer clock is derived from the external
> reference clock directly. Stop assuming the AHB clock to be the
> parent
> of all "periph"
> On Tue, 2022-10-25 at 08:58 +0100, Conor Dooley wrote:
> Sync the critical clocks in the U-Boot driver with those marked as
> critical in Linux. The Linux driver has an explanation of why each
> clock
> is considered to be critical, so import that too.
>
> Fixes: 2f27c9219e ("clk: Add Microchip
> On Tue, 2022-10-25 at 08:58 +0100, Conor Dooley wrote:
> The initial devicetree for PolarFire SoC incorrectly created a fixed
> frequency clock in the devicetree to represent the msspll, but the
> msspll is not a fixed frequency clock. The actual reference clock on
> a
> board is either 125 or 10
> On Mon, 2022-11-07 at 10:55 +0100, Heinrich Schuchardt wrote:
>
> HSS 2022.10 provides support for resetting the board.
>
> Signed-off-by: Heinrich Schuchardt >
> ---
> configs/microchip_mpfs_icicle_defconfig | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/configs/microchip_mpfs_i
> On Sat, 2022-11-05 at 14:02 +0800, Yu Chien Peter Lin wrote:
>
> We should check the string until it hits underscore, in case it
> searches for the letters in the custom extension. For example,
> "rv64imac_xandes" will be treated as D extension support since
> there is a "d" in "andes", resultin
> On Wed, 2022-11-30 at 18:03 +0100, Heinrich Schuchardt wrote:
> %s/GIUD/GUID/
>
> Fixes: 9e550e18305f ("doc: board: Add Microchip MPFS Icicle Kit doc")
> Signed-off-by: Heinrich Schuchardt >
> ---
> doc/board/microchip/mpfs_icicle.rst | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Hi Eugen,
This series of patches break my side of work(patches) so you need to create
patches after my patches are going into master branch because my patches are
already reviewed and tested.
Regards
Padmarao
From: Eugen Hristev - M18282
Sent: Wednesday, Decemb
From: Padmarao Begari
This doc describes the procedure to build, flash and
boot Linux using U-boot on Microchip MPFS Icicle Kit.
Signed-off-by: Padmarao Begari
---
doc/board/index.rst | 1 +
doc/board/microchip/index.rst | 9 +
doc/board/microchip/mpfs_icicle.rst | 60
> On Wed, 2023-06-07 at 11:06 +0100, Conor Dooley wrote:
> The original names picked for the DT doesn't match Linux's naming
> scheme
> and it was renamed there a while ago. Rename it in U-Boot to allow
> easily syncing dts between the two projects.
>
> Signed-off-by: Conor Dooley
> ---
> arch/r
> On Wed, 2023-06-07 at 11:06 +0100, Conor Dooley wrote:
> The "notable" disappearances are:
> - the pac193x stanza - there's nothing in mainline linux w.r.t.
> bindings
> for this & what is going to appear in mainline linux is going to be
> incompatible with what is currently in U-Boot.
> - op
> On Wed, 2023-06-07 at 11:06 +0100, Conor Dooley wrote:
> The dts sync from Linux leaves mac0/ethernet1 enabled on icicle, but
> U-Boot does not currently set a mac address for it. Expand on the
> code
> which currently sets the mac for mac1/ethernet0 to optionally set the
> mac address for the se
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