From: Padmarao Begari <padmarao.beg...@microchip.com> Add indexes for reset and clock control signals within the system register module of the Microchip PolarFire SoC.
Signed-off-by: Padmarao Begari <padmarao.beg...@microchip.com> --- .../dt-bindings/clock/microchip,pfsoc-clock.h | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 include/dt-bindings/clock/microchip,pfsoc-clock.h diff --git a/include/dt-bindings/clock/microchip,pfsoc-clock.h b/include/dt-bindings/clock/microchip,pfsoc-clock.h new file mode 100644 index 0000000000..527cff1a28 --- /dev/null +++ b/include/dt-bindings/clock/microchip,pfsoc-clock.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Microchip Technology Inc. + * Padmarao Begari <padmarao.beg...@microchip.com> + */ + +#ifndef _DT_BINDINGS_CLK_MICROCHIP_PFSOC_H_ +#define _DT_BINDINGS_CLK_MICROCHIP_PFSOC_H_ + +#define CLK_CPU 0 +#define CLK_AXI 1 +#define CLK_AHB 2 + +#define CLK_ENVM 3 +#define CLK_MAC0 4 +#define CLK_MAC1 5 +#define CLK_MMC 6 +#define CLK_TIMER 7 +#define CLK_MMUART0 8 +#define CLK_MMUART1 9 +#define CLK_MMUART2 10 +#define CLK_MMUART3 11 +#define CLK_MMUART4 12 +#define CLK_SPI0 13 +#define CLK_SPI1 14 +#define CLK_I2C0 15 +#define CLK_I2C1 16 +#define CLK_CAN0 17 +#define CLK_CAN1 18 +#define CLK_USB 19 +#define CLK_RESERVED 20 +#define CLK_RTC 21 +#define CLK_QSPI 22 +#define CLK_GPIO0 23 +#define CLK_GPIO1 24 +#define CLK_GPIO2 25 +#define CLK_DDRC 26 +#define CLK_FIC0 27 +#define CLK_FIC1 28 +#define CLK_FIC2 29 +#define CLK_FIC3 30 +#define CLK_ATHENA 31 +#define CLK_CFM 32 + +#endif /* _DT_BINDINGS_CLK_MICROCHIP_PFSOC_H_ */ -- 2.17.1
