Re: [PATCH v5 27/33] riscv: Fix race conditions when initializing IPI

On Mon, 2020-03-02 at 10:43 -0500, Sean Anderson wrote: > On 3/2/20 4:08 AM, Rick Chen wrote: > > Hi Sean > > > > > The IPI code could have race conditions in several places. > > > * Several harts could race on the value of gd->arch->clint/plic > > > * Non-boot harts could race with the main hart

Re: [PATCH v5 27/33] riscv: Fix race conditions when initializing IPI

On Fri, 2020-02-28 at 16:05 -0500, Sean Anderson wrote: > The IPI code could have race conditions in several places. > * Several harts could race on the value of gd->arch->clint/plic > * Non-boot harts could race with the main hart on the DM subsystem In > addition, if an IPI was pending when U-

Re: [PATCH v5 27/33] riscv: Fix race conditions when initializing IPI

On Mon, 2020-03-02 at 18:43 -0500, Sean Anderson wrote: > On 3/2/20 6:17 PM, Lukas Auer wrote: > > On Fri, 2020-02-28 at 16:05 -0500, Sean Anderson wrote: > > > > > The IPI code could have race conditions in several places. > > > * Several harts could race on

Re: [PATCH v5 27/33] riscv: Fix race conditions when initializing IPI

On Tue, 2020-03-03 at 16:57 -0500, Sean Anderson wrote: > On 3/3/20 4:53 PM, Lukas Auer wrote: > > On Mon, 2020-03-02 at 18:43 -0500, Sean Anderson wrote: > > > On 3/2/20 6:17 PM, Lukas Auer wrote: > > > > Don't move this. It is intended to be run before the IPI

Re: [PATCH 2/2] riscv: Avoid calling sbi_clear_ipi()

nged, 2 insertions(+), 1 deletion(-) > Reviewed-by: Lukas Auer

Re: [PATCH 1/2] riscv: Fix sbi_remote_sfence_vma{,_asid}

t; Signed-off-by: Bin Meng > --- > > arch/riscv/include/asm/sbi.h | 19 --- > 1 file changed, 12 insertions(+), 7 deletions(-) > Reviewed-by: Lukas Auer

[PATCH] Revert "riscv: qemu: clear kernel-start/-end in device tree as workaround for BBL"

. Signed-off-by: Lukas Auer --- board/emulation/qemu-riscv/Kconfig | 1 - board/emulation/qemu-riscv/qemu-riscv.c | 39 - 2 files changed, 40 deletions(-) diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig index 7ce12018e7

[U-Boot] [PATCH] riscv: increase stack size to avoid a stack overflow during distro boot

the secondary hart overwriting the return address in the stack frame of the main hart with an address that does not include valid code. Increase the default stack size of each hart to 16KiB to avoid this problem. Reported-by: Aurelien Jarno Signed-off-by: Lukas Auer Tested-by: David

Re: [PATCH] riscv: Try to get cpu frequency from device tree

ev_read_u32(dev, "clock-frequency", (u32 *)&info->cpu_freq); > + > + /* First try getting the frequency from the assigned clock */ > + err = clk_get_by_index(dev, 0, &clk); Usually, ret is used as a variable name here. I think it would actually make the code a bit

Re: [PATCH v2 06/11] riscv: Fix incorrect cpu frequency on RV64

| 2 ++ > 1 file changed, 2 insertions(+) > Reviewed-by: Lukas Auer

Re: [PATCH v2 03/11] riscv: Add headers for asm/global_data.h

Hi Sean, On Wed, 2020-01-15 at 17:50 -0500, Sean Anderson wrote: > This header depended on bd_t and ulong, but did not include the appropriate > headers. > > Signed-off-by: Sean Anderson > --- > arch/riscv/include/asm/global_data.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/ar

Re: [PATCH v2 05/11] riscv: Add option to disable writes to mcounteren

+ Bin, Anup, Atish On Wed, 2020-01-15 at 17:53 -0500, Sean Anderson wrote: > On the kendryte k210, writes to mcounteren result in an illegal instruction > exception. > > Signed-off-by: Sean Anderson > --- > Changes for v2: > Moved forward in the patch series > > arch/riscv/Kconfig | 3 +++

Re: [PATCH v2 07/11] riscv: Add initial Sipeed Maix support

Hi Sean, On Wed, 2020-01-15 at 18:04 -0500, Sean Anderson wrote: > The Sipeed Maix series is a collection of boards built around the RISC-V > Kendryte K210 processor. This processor contains several peripherals to > accelerate neural network processing and other "ai" tasks. This includes a > "KP

Re: [PATCH v2 03/11] riscv: Add headers for asm/global_data.h

On Sun, 2020-01-26 at 17:12 -0500, Sean Anderson wrote: > On 1/26/20 5:04 PM, Lukas Auer wrote: > > asm/u-boot.h is usually included with common.h. ulong is defined in > > linux/types.h (also included in common.h). It should be sufficient to > > include common.h

Re: [PATCH] riscv: Try to get cpu frequency from device tree

On Sun, 2020-01-26 at 13:20 -0500, Sean Anderson wrote: > On 1/26/20 11:34 AM, Lukas Auer wrote: > > Hi Sean, > > Usually, ret is used as a variable name here. I think it would actually > > make the code a bit nicer to read here, because the clock rate is not > > read fr

Re: [PATCH v2 05/11] riscv: Add option to disable writes to mcounteren

On Sun, 2020-01-26 at 17:24 -0500, Sean Anderson wrote: > On 1/26/20 5:09 PM, Lukas Auer wrote: > > + Bin, Anup, Atish > > > > > > On Wed, 2020-01-15 at 17:53 -0500, Sean Anderson wrote: > > > On the kendryte k210, writes to mcounteren result in an illega

Re: [PATCH v2 07/11] riscv: Add initial Sipeed Maix support

On Sun, 2020-01-26 at 20:09 -0500, Sean Anderson wrote: > On 1/26/20 5:17 PM, Lukas Auer wrote: > > Hi Sean, > > > > > > On Wed, 2020-01-15 at 18:04 -0500, Sean Anderson wrote: > > > The Sipeed Maix series is a collection of boards built around the RISC-V

Re: [PATCH 3/3] riscv: sifive: fu540: add SPL configuration

+Troy On Mon, 2020-01-13 at 14:32 +, Pragnesh Patel wrote: > > > > +#include > > > > + > > > > +u32 DENALI_PHY_DATA[1215] = { > > > > + DENALI_PHY_00_DATA, DENALI_PHY_01_DATA, > > > DENALI_PHY_02_DATA, > > > > + DENALI_PHY_03_DATA, DENALI_PHY_04_DATA, > > > DENALI_PHY_05_DATA, > >

Re: [PATCH 3/3] riscv: sifive: fu540: add SPL configuration

On Tue, 2020-01-14 at 23:12 -0600, Troy Benjegerdes wrote: > > On Jan 13, 2020, at 4:31 PM, Lukas Auer wrote: > > > > +Troy > > > > On Mon, 2020-01-13 at 14:32 +, Pragnesh Patel wrote: > > > > > > +#include >

[U-Boot] [PATCH 0/7] SMP support for RISC-V

://patchwork.ozlabs.org/project/uboot/list/?series=91125 [2]: https://patchwork.ozlabs.org/patch/1039493/ [3]: https://patchwork.ozlabs.org/patch/1039082/ Lukas Auer (7): riscv: add infrastructure for calling functions on other harts riscv: import the supervisor binary interface header file riscv

[U-Boot] [PATCH 1/7] riscv: add infrastructure for calling functions on other harts

has its own data structure in global data. While this is not required at the moment (all harts are expected to boot Linux), this does allow future expansion, where other harts may be used for monitoring or other tasks. Signed-off-by: Lukas Auer --- arch/riscv/Kconfig | 19

[U-Boot] [PATCH 2/7] riscv: import the supervisor binary interface header file

Import the supervisor binary interface (SBI) header file from Linux (arch/riscv/include/asm/sbi.h). The last change to it was in commit 6d60b6ee0c97 ("RISC-V: Device, timer, IRQs, and the SBI"). Signed-off-by: Lukas Auer --- arch/riscv/include/asm/

[U-Boot] [PATCH 3/7] riscv: implement IPI platform functions using SBI

mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer --- arch/riscv/Kconfig | 5 + arch/riscv/lib/Makefile | 1 + arch/riscv/lib/sbi_ipi.c | 25 + 3 files changed, 31 insertions(+) create mode 100644 arch/riscv/lib

[U-Boot] [PATCH 7/7] riscv: qemu: enable SMP

Signed-off-by: Lukas Auer --- board/emulation/qemu-riscv/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig index 0d865acf10..b3300c64a8 100644 --- a/board/emulation/qemu-riscv/Kconfig +++ b/board/emulation/qemu

[U-Boot] [PATCH 6/7] riscv: boot images passed to bootm on all harts

Signed-off-by: Lukas Auer --- arch/riscv/lib/bootm.c | 13 - 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index f36b8702ef..efbd3e23e7 100644 --- a/arch/riscv/lib/bootm.c +++ b/arch/riscv/lib/bootm.c @@ -13,6 +13,7

[U-Boot] [PATCH 5/7] riscv: add support for multi-hart systems

functions to them using smp_call_function(). Every hart has a valid pointer to the global data structure and a 8KiB stack by default. The stack size is set with CONFIG_STACK_SIZE_SHIFT. Signed-off-by: Lukas Auer --- arch/riscv/Kconfig | 12 + arch/riscv/cpu/start.S | 102

[U-Boot] [PATCH 4/7] riscv: delay initialization of caches and debug UART

. Signed-off-by: Lukas Auer --- arch/riscv/cpu/start.S | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 81ea52b170..a30f6f7194 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -45,10 +45,6

[U-Boot] [PATCH] riscv: fu540: enable SMP

Hart 0 on the SiFive FU540 is meant for monitoring tasks. It is a E51 core, whereas all other cores are U54 cores. Select hart 1 as the main hart to run U-Boot. Signed-off-by: Lukas Auer --- This patch depends on the SMP support [1] and the SiFive FU540 support patch series [2]. I have submitted

[U-Boot] [PATCH 0/6] Small fixes for RISC-V

it to run standalone applications. Lukas Auer (6): riscv: clarify error message on undefined exceptions riscv: remove invalid dcache flush implementation riscv: remove RISC-V standalone linker script riscv: replace use of callee-saved register in standalone riscv: support standalone

[U-Boot] [PATCH 2/6] riscv: remove invalid dcache flush implementation

implementation and its use in all dcache-specific functions in lib/cache.c. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer --- This patch only removes the implementation itself and its use in dcache-specific functions in lib/cache.c

[U-Boot] [PATCH 1/6] riscv: clarify error message on undefined exceptions

Undefined exceptions are treated as reserved. This is not clearly communicated to the user. Adjust the error message to clarify that a reserved exception has occurred and add additional details. Fixes: e8b522b ("riscv: treat undefined exception codes as reserved") Signed-off-by:

[U-Boot] [PATCH 4/6] riscv: replace use of callee-saved register in standalone

pointer to global data. Signed-off-by: Lukas Auer --- examples/standalone/stubs.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/examples/standalone/stubs.c b/examples/standalone/stubs.c index fadde669fa..f37d209da6 100644 --- a/examples/standalone/stubs.c +++ b

[U-Boot] [PATCH 6/6] riscv: qemu: define standalone load address

We need to define the standalone load address to use standalone application on qemu-riscv. Define it and set it equal to CONFIG_SYS_LOAD_ADDR. To not overwrite it, change the assigned of CONFIG_STANDALONE_LOAD_ADDR in arch/riscv/config.mk to a conditional one. Signed-off-by: Lukas Auer

[U-Boot] [PATCH 5/6] riscv: support standalone applications on RV64I systems

Add an implementation of EXPORT_FUNC() for RV64I systems to support them in standalone applications. Signed-off-by: Lukas Auer --- examples/standalone/stubs.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/examples/standalone/stubs.c b/examples/standalone/stubs.c index

[U-Boot] [PATCH 3/6] riscv: remove RISC-V standalone linker script

Standalone applications do not require a separate linker script and can use the default linker script of the compiler instead. Remove the RISC-V standalone linker script. Signed-off-by: Lukas Auer --- arch/riscv/config.mk | 1 - examples/standalone/riscv.lds | 40

[U-Boot] [PATCH v2 1/7] riscv: clarify error message on undefined exceptions

Undefined exceptions are treated as reserved. This is not clearly communicated to the user. Adjust the error message to clarify that a reserved exception has occurred and add additional details. Fixes: e8b522b ("riscv: treat undefined exception codes as reserved") Signed-off-by:

[U-Boot] [PATCH v2 0/7] Small fixes for RISC-V

it to run standalone applications. Changes in v2: - Replace patch "riscv: remove invalid dcache flush implementation" with new patch "riscv: move the AX25-specific implementation of flush_dcache_all" - New patch "riscv: use invalidate/flush_*cache_range functions i

[U-Boot] [PATCH v2 3/7] riscv: use invalidate/flush_*cache_range functions in cache.c

implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer --- Changes in v2: - New patch "riscv: use invalidate/f

[U-Boot] [PATCH v2 2/7] riscv: move the AX25-specific implementation of flush_dcache_all

ystem coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer --- Changes

[U-Boot] [PATCH v2 5/7] riscv: replace use of callee-saved register in standalone

pointer to global data. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested-by: Bin Meng --- Changes in v2: None examples/standalone/stubs.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/examples/standalone/stubs.c b/examples/standalone/stubs.c index fadde669fa

[U-Boot] [PATCH v2 4/7] riscv: remove RISC-V standalone linker script

Standalone applications do not require a separate linker script and can use the default linker script of the compiler instead. Remove the RISC-V standalone linker script. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested-by: Bin Meng --- Changes in v2: None arch/riscv/config.mk

[U-Boot] [PATCH v2 6/7] riscv: support standalone applications on RV64I systems

Add an implementation of EXPORT_FUNC() for RV64I systems to support them in standalone applications. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested-by: Bin Meng --- Changes in v2: None examples/standalone/stubs.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a

[U-Boot] [PATCH v2 7/7] riscv: qemu: define standalone load address

We need to define the standalone load address to use standalone application on qemu-riscv. Define it and set it equal to CONFIG_SYS_LOAD_ADDR. To not overwrite it, change the assigned of CONFIG_STANDALONE_LOAD_ADDR in arch/riscv/config.mk to a conditional one. Signed-off-by: Lukas Auer Reviewed

[U-Boot] [PATCH 00/30] General fixes / cleanup for RISC-V and improvements to qemu-riscv

://github.com/riscv/riscv-qemu/pull/175 [2]: https://github.com/lukasauer/riscv-pk/tree/riscv-u-boot Lukas Auer (30): tools: .gitignore: add prelink-riscv riscv: ignore device tree binaries dts: riscv: update makefile to also clean the RISC-V dts directory riscv: rename CPU_RISCV_32/64 to

[U-Boot] [PATCH 01/30] tools: .gitignore: add prelink-riscv

Ignore tools/prelink-riscv. Signed-off-by: Lukas Auer --- tools/.gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/.gitignore b/tools/.gitignore index c8cdaef90c..e5ede22842 100644 --- a/tools/.gitignore +++ b/tools/.gitignore @@ -24,6 +24,7 @@ /mksunxiboot /mxsboot /ncb

[U-Boot] [PATCH 02/30] riscv: ignore device tree binaries

Ignore all device tree binaries in arch/riscv/dts. Signed-off-by: Lukas Auer --- arch/riscv/dts/.gitignore | 1 + 1 file changed, 1 insertion(+) create mode 100644 arch/riscv/dts/.gitignore diff --git a/arch/riscv/dts/.gitignore b/arch/riscv/dts/.gitignore new file mode 100644 index

[U-Boot] [PATCH 04/30] riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I

RISC-V defines the base integer instruction sets as RV32I and RV64I. Rename CPU_RISCV_32 and CPU_RISCV_64 to ARCH_RV32I and ARCH_64I to match this convention. Signed-off-by: Lukas Auer --- arch/riscv/Kconfig | 16 arch/riscv/lib/setjmp.S | 2 +- configs

[U-Boot] [PATCH 03/30] dts: riscv: update makefile to also clean the RISC-V dts directory

Signed-off-by: Lukas Auer --- dts/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/dts/Makefile b/dts/Makefile index 9a9a3d5c98..cd6e9a968e 100644 --- a/dts/Makefile +++ b/dts/Makefile @@ -61,4 +61,4 @@ dtbs: $(obj)/dt.dtb $(obj)/dt-spl.dtb clean-files := dt.dtb.S

[U-Boot] [PATCH 05/30] riscv: select CONFIG_PHYS_64BIT on RV64I systems

CONFIG_PHYS_64BIT should be enabled on RV64I systems. Select it. Signed-off-by: Lukas Auer --- arch/riscv/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 7c76b4d664..b81e0d990a 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig

[U-Boot] [PATCH 06/30] riscv: add Kconfig entries for the C and A ISA extensions

Kconfig configuration. Signed-off-by: Lukas Auer --- arch/riscv/Kconfig | 9 + 1 file changed, 9 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index b81e0d990a..e15329c35e 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -38,6 +38,15 @@ config ARCH_RV64I

[U-Boot] [PATCH 13/30] riscv: do not reimplement generic io functions

RISC-V u-boot reimplements the generic io functions from asm-generic/io.h. Remove the redundant implementation and include the generic io.h instead. Signed-off-by: Lukas Auer --- arch/riscv/include/asm/io.h | 31 +++ 1 file changed, 3 insertions(+), 28 deletions

[U-Boot] [PATCH 07/30] riscv: set -march and -mabi based on the Kconfig configuration

reports a decrease in binary size of 71590 bytes. Signed-off-by: Lukas Auer --- arch/riscv/Makefile | 13 + arch/riscv/config.mk | 4 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 8fb6a889d8..6fb292d0b4 100644

[U-Boot] [PATCH 18/30] riscv: invalidate the instruction cache before jumping to Linux

Signed-off-by: Lukas Auer --- arch/riscv/lib/bootm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index a7a9fb921b..bc1d4b2864 100644 --- a/arch/riscv/lib/bootm.c +++ b/arch/riscv/lib/bootm.c @@ -38,6 +38,7 @@ int do_bootm_linux(int flag

[U-Boot] [PATCH 28/30] riscv: align bootm implementation with that of other architectures

* Call the remove function on devices with the removal flag set before booting Linux * Force disconnect USB devices from the host before booting Linux * Print and add bootstage information to the device tree before booting Linux Signed-off-by: Lukas Auer --- arch/riscv/lib/bootm.c | 94

[U-Boot] [PATCH 10/30] riscv: enable -fdata-sections

Enable the -fdata-sections compiler option for RISC-V. Buildman reports the binary size decrease from this as 8365.3 bytes. Signed-off-by: Lukas Auer --- arch/riscv/config.mk | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/riscv/config.mk b/arch/riscv/config.mk index

[U-Boot] [PATCH 09/30] riscv: move target selection into separate file

Move the target selection into a separate file (Kconfig.board) to avoid clutter once we support more boards. Signed-off-by: Lukas Auer --- arch/riscv/Kconfig | 17 ++--- arch/riscv/Kconfig.board | 14 ++ 2 files changed, 16 insertions(+), 15 deletions(-) create

[U-Boot] [PATCH 27/30] riscv: qemu: support booting Linux

Support booting Linux (as payload of BBL) from FIT images. For this, the default CONFIG_SYS_BOOTM_LEN is increased to 16 MB, and the environment variables fdt_high and initrd_high are set to mark the device tree and initrd as in-place. Signed-off-by: Lukas Auer --- configs/qemu

[U-Boot] [PATCH 20/30] riscv: align mtvec on a 4-byte boundary

The machine trap-vector base address (mtvec) must be aligned on a 4-byte boundary. Add the necessary align directive to trap_entry. This patch also removes the global directive for trap_entry, which is not required. Signed-off-by: Lukas Auer --- arch/riscv/cpu/start.S | 2 +- 1 file changed

[U-Boot] [PATCH 11/30] riscv: fix use of incorrectly sized variables

The RISC-V arch incorrectly uses 32-bit instead of 64-bit variables in several places. Fix this. In addition, BITS_PER_LONG is set to 64 on RV64I systems. Signed-off-by: Lukas Auer --- arch/riscv/include/asm/io.h | 6 +++--- arch/riscv/include/asm/posix_types.h | 6 +++--- arch

[U-Boot] [PATCH 17/30] riscv: implement the invalidate_icache_* functions

as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer --- arch/riscv/lib/cache.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c index 1d67c49c2c

[U-Boot] [PATCH 16/30] riscv: hang on unhandled exceptions

Hang on unhandled exceptions to prevent execution in a faulty state. Signed-off-by: Lukas Auer --- arch/riscv/lib/interrupts.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c index 32d0598750..3b74b76c70 100644 --- a/arch/riscv

[U-Boot] [PATCH 14/30] riscv: complete the list of exception codes

Only the first four exception codes are defined. Add the missing exception codes from the definition in RISC-V Privileged Architecture Version 1.10. Signed-off-by: Lukas Auer --- arch/riscv/lib/interrupts.c | 13 - 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch

[U-Boot] [PATCH 15/30] riscv: treat undefined exception codes as reserved

Undefined exception codes currently lead to an out-of-bounds array access. Prevent this by treating undefined exception codes as "reserved". Signed-off-by: Lukas Auer --- arch/riscv/lib/interrupts.c | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch

[U-Boot] [PATCH 21/30] riscv: remove CONFIG_INIT_CRITICAL

CONFIG_INIT_CRITICAL is deprecated and not used for RISC-V. Remove it. Signed-off-by: Lukas Auer --- arch/riscv/cpu/start.S | 11 --- 1 file changed, 11 deletions(-) diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 88b4aaa1c0..f375a9316e 100644 --- a/arch/riscv/cpu

[U-Boot] [PATCH 08/30] riscv: add Kconfig entries for the code model

and medany on 64-bit systems. This matches the configuration in Linux. The -mcmodel compiler flag is selected according to the Kconfig configuration. Signed-off-by: Lukas Auer --- arch/riscv/Kconfig | 19 +++ arch/riscv/Makefile | 7 +-- 2 files changed, 24 insertions(+), 2

[U-Boot] [PATCH 30/30] riscv: qemu: detect and boot the kernel passed by QEMU

QEMU embeds the location of the kernel image in the device tree. Store this address in the environment as variable kernel_start and use it in CONFIG_BOOTCOMMAND to boot the kernel. Signed-off-by: Lukas Auer --- board/emulation/qemu-riscv/Kconfig | 1 + board/emulation/qemu-riscv/qemu

[U-Boot] [PATCH 19/30] riscv: fix inconsistent use of spaces and tabs in start.S

Start.S uses both tabs and spaces after instructions. Fix this by only using tabs after instructions. Signed-off-by: Lukas Auer --- arch/riscv/cpu/start.S | 322 - 1 file changed, 161 insertions(+), 161 deletions(-) diff --git a/arch/riscv/cpu/start.S b

[U-Boot] [PATCH 25/30] riscv: qemu: use device tree passed by prior boot stage

QEMU provides a device tree, which is passed to u-boot using register a1. We are now able to directly select the device tree with the configuration CONFIG_OF_PRIOR_STAGE. Replace the hard-coded address in qemu-riscv with it. Signed-off-by: Lukas Auer --- board/emulation/qemu-riscv/qemu-riscv.c

[U-Boot] [PATCH 29/30] dm: core: add missing prototype for ofnode_read_u64

Signed-off-by: Lukas Auer --- include/dm/ofnode.h | 10 ++ 1 file changed, 10 insertions(+) diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h index 2fc9fa39a3..a7b8609cf4 100644 --- a/include/dm/ofnode.h +++ b/include/dm/ofnode.h @@ -216,6 +216,16 @@ static inline int

[U-Boot] [PATCH 23/30] riscv: do not blindly modify the mstatus CSR

zero as an immediate. RISC-V has the zero register for this purpose. Replace the immediates with the zero register. Signed-off-by: Lukas Auer --- arch/riscv/cpu/start.S | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index

[U-Boot] [PATCH 24/30] riscv: save hart ID and device tree passed by prior boot stage

: Lukas Auer --- arch/riscv/cpu/cpu.c | 6 ++ arch/riscv/cpu/start.S | 12 ++-- 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index ae57fb8313..d9f820c44c 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -6,6

[U-Boot] [PATCH 26/30] bdinfo: riscv: print fdt_blob address

Print the address of the u-boot device tree. Signed-off-by: Lukas Auer --- cmd/bdinfo.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c index 60b438766d..a9692f7662 100644 --- a/cmd/bdinfo.c +++ b/cmd/bdinfo.c @@ -430,6 +430,8 @@ int do_bdinfo(cmd_tbl_t *cmdtp

[U-Boot] [PATCH 12/30] riscv: make use of the barrier functions from Linux

Replace the barrier functions in arch/riscv/include/asm/io.h with those defined in barrier.h, which is imported from Linux. This version is modified to remove the include statement of asm-generic/barrier.h, which is not available in u-boot or required. Signed-off-by: Lukas Auer --- Checkpatch

[U-Boot] [PATCH 22/30] riscv: remove unused labels in start.S

is therefore no reason for saving a2. Signed-off-by: Lukas Auer --- arch/riscv/cpu/start.S | 11 --- 1 file changed, 11 deletions(-) diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index f375a9316e..851a1d0870 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S

[U-Boot] [PATCH v2 01/29] tools: .gitignore: add prelink-riscv

Ignore tools/prelink-riscv. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Reviewed-by: Rick Chen --- Changes in v2: None tools/.gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/.gitignore b/tools/.gitignore index c8cdaef90c..e5ede22842 100644 --- a/tools/.gitignore

[U-Boot] [PATCH v2 02/29] dts: riscv: update makefile to also clean the RISC-V dts directory

Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Reviewed-by: Rick Chen --- Changes in v2: None dts/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/dts/Makefile b/dts/Makefile index 9a9a3d5c98..cd6e9a968e 100644 --- a/dts/Makefile +++ b/dts/Makefile @@ -61,4 +61,4

[U-Boot] [PATCH v2 03/29] riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I

RISC-V defines the base integer instruction sets as RV32I and RV64I. Rename CPU_RISCV_32 and CPU_RISCV_64 to ARCH_RV32I and ARCH_RV64I to match this convention. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Reviewed-by: Rick Chen --- Changes in v2: None arch/riscv/Kconfig

[U-Boot] [PATCH v2 04/29] riscv: select CONFIG_PHYS_64BIT on RV64I systems

CONFIG_PHYS_64BIT should be enabled on RV64I systems. Select it. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Reviewed-by: Rick Chen --- Changes in v2: None arch/riscv/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 7c76b4d664

[U-Boot] [PATCH v2 19/29] Drop CONFIG_INIT_CRITICAL

From: Bin Meng This is now deprecated and no board is using it. Drop it. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer Signed-off-by: Lukas Auer --- Changes in v2: - New patch to replace patch "riscv: remove CONFIG_INIT_CRITICAL" arch/nds32/cpu/n1213/star

[U-Boot] [PATCH v2 22/29] riscv: save hart ID and device tree passed by prior boot stage

: Lukas Auer Reviewed-by: Bin Meng Reviewed-by: Rick Chen --- Changes in v2: None arch/riscv/cpu/cpu.c | 6 ++ arch/riscv/cpu/start.S | 12 ++-- 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index ae57fb8313..d9f820c44c

[U-Boot] [PATCH v2 09/29] riscv: fix use of incorrectly sized variables

The RISC-V arch incorrectly uses 32-bit instead of 64-bit variables in several places. Fix this. In addition, BITS_PER_LONG is set to 64 on RV64I systems. Signed-off-by: Lukas Auer --- Changes in v2: - Remove 0-padding in the format string to avoid printing 16 digits on RV32I systems arch

[U-Boot] [PATCH v2 21/29] riscv: do not blindly modify the mstatus CSR

zero as an immediate. RISC-V has the zero register for this purpose. Replace the immediates with the zero register. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Reviewed-by: Rick Chen --- Changes in v2: None arch/riscv/cpu/start.S | 8 1 file changed, 4 insertions(+), 4 deletions

[U-Boot] [PATCH v2 15/29] riscv: implement the invalidate_icache_* functions

as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Reviewed-by: Rick Chen --- Changes in v2: None arch/riscv/lib/cache.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch

[U-Boot] [PATCH v2 23/29] riscv: qemu: use device tree passed by prior boot stage

QEMU provides a device tree, which is passed to U-Boot using register a1. We are now able to directly select the device tree with the configuration CONFIG_OF_PRIOR_STAGE. Replace the hard-coded address in qemu-riscv with it. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Reviewed-by: Rick Chen

[U-Boot] [PATCH v2 14/29] riscv: hang on unhandled exceptions

Hang on unhandled exceptions to prevent execution in a faulty state. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Reviewed-by: Rick Chen --- Changes in v2: None arch/riscv/lib/interrupts.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib

[U-Boot] [PATCH v2 08/29] riscv: enable -fdata-sections

Enable the -fdata-sections compiler option for RISC-V. Buildman reports the binary size decrease from this as 8365.3 bytes. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Reviewed-by: Rick Chen --- Changes in v2: None arch/riscv/config.mk | 3 ++- 1 file changed, 2 insertions(+), 1

[U-Boot] [PATCH v2 13/29] riscv: treat undefined exception codes as reserved

Undefined exception codes currently lead to an out-of-bounds array access. Prevent this by treating undefined exception codes as "reserved". Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Reviewed-by: Rick Chen --- Changes in v2: None arch/riscv/lib/interrupts.c | 8 ++

[U-Boot] [PATCH v2 25/29] riscv: qemu: support booting Linux

Support booting Linux (as payload of BBL) from FIT images. For this, the default CONFIG_SYS_BOOTM_LEN is increased to 16 MB, and the environment variables fdt_high and initrd_high are set to mark the device tree and initrd as in-place. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng

[U-Boot] [PATCH v2 18/29] riscv: align mtvec on a 4-byte boundary

The machine trap-vector base address (mtvec) must be aligned on a 4-byte boundary. Add the necessary align directive to trap_entry. This patch also removes the global directive for trap_entry, which is not required. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng --- Changes in v2: None

[U-Boot] [PATCH v2 07/29] riscv: add Kconfig entries for the code model

and medany on 64-bit systems. This matches the configuration in Linux. The -mcmodel compiler flag is selected according to the Kconfig configuration. Signed-off-by: Lukas Auer --- Changes in v2: - Change ISA string construction, as suggested by Bin Meng arch/riscv/Kconfig | 19

[U-Boot] [PATCH v2 12/29] riscv: complete the list of exception codes

Only the first four exception codes are defined. Add the missing exception codes from the definition in RISC-V Privileged Architecture Version 1.10. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Reviewed-by: Rick Chen --- Changes in v2: None arch/riscv/lib/interrupts.c | 13

[U-Boot] [PATCH v2 16/29] riscv: invalidate the instruction cache before jumping to Linux

RISC-V does not guarantee that stores to instruction memory are visible to instruction fetches (i.e. incoherent instruction caches). Invalidate the instruction cache to ensure the kernel function pointer points to the correct memory location. Signed-off-by: Lukas Auer --- Changes in v2

[U-Boot] [PATCH v2 06/29] riscv: set -march and -mabi based on the Kconfig configuration

reports a decrease in binary size of 71590 bytes. Signed-off-by: Lukas Auer --- Changes in v2: - Change ISA string construction, as suggested by Bin Meng arch/riscv/Makefile | 20 arch/riscv/config.mk | 4 2 files changed, 20 insertions(+), 4 deletions(-) diff --git

[U-Boot] [PATCH v2 26/29] riscv: align bootm implementation with that of other architectures

* Call the remove function on devices with the removal flag set before booting Linux * Force disconnect USB devices from the host before booting Linux * Print and add bootstage information to the device tree before booting Linux Signed-off-by: Lukas Auer Reviewed-by: Bin Meng --- Changes in v2

[U-Boot] [PATCH v2 27/29] dm: core: add missing prototype for ofnode_read_u64

Signed-off-by: Lukas Auer --- Changes in v2: - Move prototype location to match the location of the function in ofnode.c include/dm/ofnode.h | 10 ++ 1 file changed, 10 insertions(+) diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h index 2fc9fa39a3..92539b8b5f 100644 --- a

[U-Boot] [PATCH v2 05/29] riscv: add Kconfig entries for the C and A ISA extensions

Kconfig configuration. Signed-off-by: Lukas Auer --- Changes in v2: - Replace the description of RISCV_ISA_C with that of the Linux kernel, as suggested by Bin Meng arch/riscv/Kconfig | 11 +++ 1 file changed, 11 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index

[U-Boot] [PATCH v2 29/29] riscv: qemu: clear kernel-start/-end in device tree as workaround for BBL

detects the kernel properties in the device tree and ignores the Linux payload as a result. Work around this issue by clearing the kernel properties in the device tree before booting Linux. Signed-off-by: Lukas Auer --- Changes in v2: - New patch board/emulation/qemu-riscv/Kconfig | 1

[U-Boot] [PATCH v2 11/29] riscv: do not reimplement generic io functions

RISC-V U-Boot reimplements the generic io functions from asm-generic/io.h. Remove the redundant implementation and include the generic io.h instead. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Reviewed-by: Rick Chen --- Changes in v2: None arch/riscv/include/asm/io.h | 31

[U-Boot] [PATCH v2 20/29] riscv: remove unused labels in start.S

The labels nmi_vector, trap_vector and handle_reset in start.S are not used for RISC-V. Remove them. Signed-off-by: Lukas Auer --- Changes in v2: - Drop removal of code that stores the contents of a2; this broke the board ax25-ae350. The code will be removed again in a future patch. arch

[U-Boot] [PATCH v2 28/29] riscv: qemu: detect and boot the kernel passed by QEMU

QEMU embeds the location of the kernel image in the device tree. Store this address in the environment as variable kernel_start and use it in CONFIG_BOOTCOMMAND to boot the kernel. Use the device tree passed by the prior boot stage to boot Linux. Signed-off-by: Lukas Auer --- Changes in v2

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