Re: [PATCH 1/2] Revert "riscv: Allow use of reset drivers"

; > #include > > #include > > > > -#ifndef CONFIG_SYSRESET > > int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) > > { > > printf("resetting ...\n"); > > @@ -17,4 +16,3 @@ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, > > char *const argv[]) > > > > return 0; > > } > > -#endif > > > > Reviewed-by: Sean Anderson Reviewed-by: Leo Liang

Re: [PATCH 4/4] ram: sifive: Avoid using hardcoded ram base and size

Hi Bin, This whole patch set looks pretty good to me. Just out of curiosity and as being rather new to the u-boot community, would the following fix be more direct and avoid modifying general code? On Wed, Jul 15, 2020 at 08:23:03PM -0700, Bin Meng wrote: > From: Bin Meng > > At present the Si

Re: [PATCH] riscv: ae350: Use fdtdec_get_addr_size_auto_noparent to parse smc reg

ddr_size_auto_noparent(blob, node, > + "reg", 0, NULL, false); > > if (addr == FDT_ADDR_T_NONE) > return -EINVAL; > -- > 2.7.4 > Acked-by: Leo Liang

Re: [PATCH] riscv: ae350: Use fdtdec_get_addr_size_auto_noparent to parse smc reg

crease the compatibility > > of dtb parsing. > > > > Signed-off-by: Rick Chen > > --- > > board/AndesTech/ax25-ae350/ax25-ae350.c | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > Reviewed-by: Bin Meng Tested-by: Leo Liang

Re: [PATCH v2 2/2] ram: sifive: Avoid using hardcoded ram base and size

efined(CONFIG_SPL_BUILD) > struct regmap *map; > int ret; > @@ -368,14 +373,9 @@ static int fu540_ddr_probe(struct udevice *dev) > priv->phy = regmap_get_range(map, 1); > priv->physical_filter_ctrl = regmap_get_range(map, 2); > > - priv->info.base = CONFIG_SYS_SDRAM_BASE; > - > - priv->info.size = 0; > return fu540_ddr_setup(dev); > -#else > - priv->info.base = CONFIG_SYS_SDRAM_BASE; > - priv->info.size = DDR_MEM_SIZE; > #endif > + > return 0; > } > > -- > 2.7.4 > Reviewed-by: Leo Liang

Re: [PATCH v4] riscv: Make SiFive HiFive Unleashed board boot again

c b/common/spl/spl_opensbi.c > index 3440bc0..14f335f 100644 > --- a/common/spl/spl_opensbi.c > +++ b/common/spl/spl_opensbi.c > @@ -79,11 +79,6 @@ void spl_invoke_opensbi(struct spl_image_info *spl_image) > invalidate_icache_all(); > > #ifdef CONFIG_SPL_SMP > - /* Initialize the IPI before we use it */ > - ret = riscv_init_ipi(); > - if (ret) > - hang(); > - > /* >* Start OpenSBI on all secondary harts and wait for acknowledgment. >* > -- > 2.7.4 > Tested-by: Leo Liang

Re: [PATCH v2] serial: Fix SIFIVE debug serial dependency

uot;SiFive UART" > - depends on PL01X_SERIAL > + depends on SIFIVE_SERIAL > help > Select this to enable a debug UART using the serial_sifive driver. You > will need to provide parameters to make this work. The driver will > -- > 2.27.0 > Reviewed-by: Leo Liang

Re: [PATCH 2/2] configs: migrate CONFIG_SPL_LOAD_FIT_ADDRESS to defconfigs

Hi Peng, I assume the purpose of these patches is try to move all the configuration into one single file, right? However with this patch, uboot will fail on AndesCore, and I'm guessing other platforms may also have the same problem. If you could elaborate more on the purpose of the patchset, ma

Re: [PATCH 1/1] cmd: exception: unaligned data access on RISC-V

Hi Heinrich, On Thu, Aug 06, 2020 at 10:15:28AM +0800, Rick Chen wrote: > Hi Heinrich > > > >> From: Heinrich Schuchardt [mailto:xypron.g...@gmx.de] > > >> Sent: Tuesday, August 04, 2020 7:10 PM > > >> To: Rick Jian-Zhi Chen(陳建志) > > >> Cc: u-boot@lists.denx.de; Heinrich Schuchardt > > >> Subject

Re: [PATCH 5/6] riscv: sifive/fu540: Drop NET_RANDOM_ETHADDR

/sifive/fu540/Kconfig > @@ -41,7 +41,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy > imply EFI_PARTITION > imply IP_DYN > imply ISO_PARTITION > - imply NET_RANDOM_ETHADDR > imply PHY_LIB > imply PHY_MSCC > imply SPI_FLASH > -- > 2.7.4 > Reviewed-by: Leo Liang

Re: [PATCH 6/6] riscv: sifive/fu540: Move SPL related functions to spl.c

t: > + debug("Unsupported boot device 0x%x but trying MMC1\n", > + boot_device); > + return BOOT_DEVICE_MMC1; > + } > +} > + > +#ifdef CONFIG_SPL_LOAD_FIT > +int board_fit_config_name_match(const char *name) > +{ > + /* boot using first FIT config */ > + return 0; > +} > +#endif > -- > 2.7.4 > Reviewed-by: Leo Liang

Re: [PATCH] riscv: Only enable OF_BOARD_FIXUP for S-Mode

ted my reasoning behind this patch at [1]. In my testing, I > >> could only trigger a "periodic-32" bug. > >> > >> In any case, this behavior could still cause problems in the future. > >> From my testing, on the k210, a1 usually holds some address on the ROM's > >> stack. However, if it (for instance) instead held an address which > > > > So U-Boot on K210 boots with M-mode from the K210 ROM, and the ROM > > code does not hold DTB address in a1 before jumping to U-Boot, right? > > > >> raised a load access fault, or was misaligned, then booting would fail. > >> In the general case, I was very surpised that U-Boot was using the value > >> of a1 on entry even with OF_SEPARATE specified. I would expect it only > >> to use that value if configured with OF_PRIOR_STAGE. > > > > Because U-Boot S-mode needs to fix up the DT when OF_SEPERATE is used. > > Right. It's just unexpected because OF_SEPARATE appears to imply to both > use a separate device tree and to not use the passed-in device tree. > This is because it is mutually exclusive with OF_PRIOR_STAGE. However, > with OF_BOARD_FIXUP, it's as if one has selected both OF_SEPARATE and > OF_PRIOR_STAGE at once. I think defaulting OF_BOARD_FIXUP to y only > S-Mode is more likely to result in unsurprising behavior on new boards. > > --Sean Reviewed-by: Leo Liang

Re: [PATCH v2 2/7] riscv: Match memory barriers between send_ipi_many and handle_ipi

ipi_data *ipi, int wait) > gd->arch.ipi[reg].arg0 = ipi->arg0; > gd->arch.ipi[reg].arg1 = ipi->arg1; > > + __smp_mb(); > + > ret = riscv_send_ipi(reg); > if (ret) { > pr_err("Cannot send IPI to hart %d\n", reg); Reviewed-by: Leo Liang

Re: [PATCH v2 3/7] riscv: Use a valid bit to ignore already-pending IPIs

not set, then U-Boot has not requested the IPI. The > + * IPI device may not be initialized, so all we can do is wait for > + * U-Boot to initialize it and send an IPI > + */ > + if (!__smp_load_acquire(&gd->arch.ipi[hart].valid)) > + return; > > smp_function = (void (*)(ulong, ulong, ulong))gd->arch.ipi[hart].addr; > invalidate_icache_all(); Reviewed-by: Leo Liang

Re: [PATCH v2 7/7] riscv: Add some comments to start.S

abled globally, but they can still be read from m/sip. > The > + * wfi function will wake us up if we get an IPI, even if we do not trap. > + */ > secondary_hart_loop: > wfi > Reviewed-by: Leo Liang

Re: [PATCH v6 12/12] riscv: Add FPIOA and GPIO support for Kendryte K210

Hi Sean, On Mon, Sep 14, 2020 at 11:02:06AM -0400, Sean Anderson wrote: > This patch adds the necessary configs and docs for FPIOA and GPIO support > on the K210. > > Signed-off-by: Sean Anderson > --- > > Changes in v6: > - Add dependency on "riscv: Clean up timer drivers", which fixes the bug

Re: [PATCH 1/1] riscv: support building double-float modules

Hi Heinrich, On Sat, Oct 08, 2022 at 11:17:57AM +0200, Heinrich Schuchardt wrote: > The riscv32 toolchain for GCC-12 provided by kernel.org contains libgcc.a > compiled for double-float. To link to it we have to adjust how we build > U-Boot. > > As U-Boot actually does not use floating point at a

Re: [PATCH] riscv: ae350: Check firmware_fdt_addr header

Hi Rick, On Thu, Oct 13, 2022 at 01:24:20PM +0800, Rick Chen wrote: > Check firmware_fdt_addr header to see if it is a valid > fdt blob. > > Signed-off-by: Rick Chen > --- > board/AndesTech/ax25-ae350/ax25-ae350.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) LGTM! Could you send it

[PULL] u-boot-riscv/master

Hi Tom, The following changes since commit 3724ddf157aab3bd009c1da234b9a1af1621b544: Merge branch '2022-10-18-TI-platform-updates' (2022-10-18 18:13:39 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to b3

Re: [PATCH v1 1/6] dt-bindings: clk: add missing clk ids for microchip mpfs

On Tue, Oct 25, 2022 at 08:58:44AM +0100, Conor Dooley wrote: > When this binding header was initally upstreamed, the PLL clocking the > microprocessor subsystem (MSS) and the RTC reference clocks were > omitted. Add them now, matching the IDs used in Linux. > > Signed-off-by: Conor Dooley > ---

Re: [PATCH v1 2/6] clk: microchip: mpfs: convert parent rate acquistion to get_get_rate()

On Tue, Oct 25, 2022 at 08:58:45AM +0100, Conor Dooley wrote: > Currently the clock driver for PolarFire SoC takes a very naive approach > to the relationship between clocks. It reads the dt to get an input > clock, assumes that that is fixed frequency, reads the "clock-frequency" > property & uses

Re: [PATCH v1 3/6] clk: microchip: mpfs: fix reference clock handling

On Tue, Oct 25, 2022 at 08:58:46AM +0100, Conor Dooley wrote: > The original devicetrees for PolarFire SoC messed up & defined the > msspll's output as a fixed-frequency, 600 MHz clock & used that as the > input for the clock controller node. The msspll is not a fixed > frequency clock and later de

Re: [PATCH v1 4/6] clk: microchip: mpfs: fix periph clk parentage

On Tue, Oct 25, 2022 at 08:58:47AM +0100, Conor Dooley wrote: > Not all "periph" clocks are children of the AHB clock, some have the AXI > clock as their parent & the mtimer clock is derived from the external > reference clock directly. Stop assuming the AHB clock to be the parent > of all "periph"

Re: [PATCH v1 5/6] clk: microchip: mpfs: fix criticality of peripheral clocks

On Tue, Oct 25, 2022 at 08:58:48AM +0100, Conor Dooley wrote: > Sync the critical clocks in the U-Boot driver with those marked as > critical in Linux. The Linux driver has an explanation of why each clock > is considered to be critical, so import that too. > > Fixes: 2f27c9219e ("clk: Add Microch

Re: [PATCH v1 6/6] riscv: dts: fix the mpfs's reference clock frequency

On Tue, Oct 25, 2022 at 08:58:49AM +0100, Conor Dooley wrote: > The initial devicetree for PolarFire SoC incorrectly created a fixed > frequency clock in the devicetree to represent the msspll, but the > msspll is not a fixed frequency clock. The actual reference clock on a > board is either 125 or

[PULL] u-boot-riscv/master

Hi Tom, The following changes since commit c8d9ff634fc429db5acf2f5386ea937f0fef1ae7: Merge branch '2022-10-31-FWU-add-FWU-multi-bank-update-feature-support' (2022-11-01 09:32:21 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for y

Re: [PULL] u-boot-riscv/master

Hi Tom, On Thu, Nov 03, 2022 at 12:57:05PM -0400, Tom Rini wrote: > On Thu, Nov 03, 2022 at 07:04:33AM +0000, Leo Liang wrote: > > > Hi Tom, > > > > The following changes since commit c8d9ff634fc429db5acf2f5386ea937f0fef1ae7: > > > > Merge branch '

Re: [PATCH] riscv: Fix build against binutils 2.38

Hi Alex, On Tue, Apr 12, 2022 at 11:14:32AM +0200, Alexandre Ghiti wrote: > Hi Leo, > > A gentle ping. > > > > Any comments? > > Or should we spin a patch for updating the toolchain used for 32 bit build? > > Sorry for being very slow here, if the patch is too much of a burden, > maybe you should

Re: [PATCH 1/1] cmd/sbi: add implementation ID 6 - Coffer

On Sat, May 07, 2022 at 02:42:10PM +0200, Heinrich Schuchardt wrote: > The sbi command displays the ID of the implementation of the RISC-V > Supervisor Binary Interface Specification. A new ID for Coffer has recently > been added. > > Signed-off-by: Heinrich Schuchardt > --- > cmd/riscv/sbi.c |

[PULL] u-boot-riscv/master

Hi Tom, The following changes since commit 59bffec43a657598b194b9eb30dc01eec06078c7: Merge branch '2022-04-04-platform-updates' (2022-04-05 13:45:22 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 776e8

Re: [PATCH] riscv: Fix build against binutils 2.38

Hi Alex, On Thu, Mar 10, 2022 at 09:03:08AM +0100, Alexandre Ghiti wrote: > Hi Leo, > > On Wed, Mar 9, 2022 at 7:31 AM Leo Liang wrote: > > > > Hi Alex, > > On Thu, Mar 03, 2022 at 11:06:18AM +, Leo Liang wrote: > > > Hi Alex, > > > On Tue, Mar

Re: [RFC PATCH] riscv: cpu: check U-Mode before counteren write

On Wed, Dec 14, 2022 at 08:58:43AM +0300, Nikita Shubin wrote: > From: Nikita Shubin > > The Priv ISA states: > "In systems without U-mode, the mcounteren register should > not exist." > > Check U-Mode is present in MISA before writing to counteren, otherwise > we endup with Illegal Instruction

[PULL] u-boot-riscv/master

Hi Tom, The following changes since commit 73a3f5139182a0389d505bf29b0ad4bc29424cf8: Merge https://source.denx.de/u-boot/custodians/u-boot-mmc (2023-01-31 18:28:07 -0500) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch cha

Re: Docs for RISC-V

Hi Simon, On Thu, Feb 02, 2023 at 10:25:36AM -0700, Simon Glass wrote: > Hi, > > On Thu, 2 Feb 2023 at 10:18, Simon Glass wrote: > > > > Hi Rick & Leo, > > > > I see docs for one board at [1] but I'm not sure what to do with unleashed. > > > > It seems to need a 'genimage' tool, going on what I

Re: [PATCH v2] riscv: cancel the limitation that NR_CPUS is less than or equal to 32

Hi David, On Fri, Feb 03, 2023 at 03:24:37PM +0100, David Abdurachmanov wrote: > On Mon, Jan 3, 2022 at 1:13 PM Leo Liang wrote: > > > > On Thu, Dec 30, 2021 at 01:55:15AM +0800, Xiang W wrote: > > > 在 2021-12-29星期三的 17:23 +0800，Leo Liang写道： > > > > Hi Xiang

Re: [PATCH v2] riscv: cancel the limitation that NR_CPUS is less than or equal to 32

Hi Xiang, On Fri, Feb 03, 2023 at 03:24:37PM +0100, David Abdurachmanov wrote: > On Mon, Jan 3, 2022 at 1:13 PM Leo Liang wrote: > > > > On Thu, Dec 30, 2021 at 01:55:15AM +0800, Xiang W wrote: > > > 在 2021-12-29星期三的 17:23 +0800，Leo Liang写道： > > > > Hi Xiang

Re: [PATCH v2] riscv: cancel the limitation that NR_CPUS is less than or equal to 32

Hi Xiang, On Sat, Feb 11, 2023 at 10:11:31PM +0800, Xiang W wrote: > 在 2023-02-10星期五的 07:25 +0000，Leo Liang写道： > > Hi Xiang, > > > > On Fri, Feb 03, 2023 at 03:24:37PM +0100, David Abdurachmanov wrote: > > > On Mon, Jan 3, 2022 at 1:13 PM Leo Liang wrote: > &g

Re: [PATCH] riscv: binman: Add help message for missing blobs

Hi Rick, On Thu, Feb 16, 2023 at 09:19:45AM +0800, Rick Chen wrote: > Add the 'missing-msg' for more detailed output > on missing system firmware. > > Signed-off-by: Rick Chen > --- > arch/riscv/dts/binman.dtsi | 1 + > tools/binman/missing-blob-help | 4 > 2 files changed, 5 insertion

[PULL] u-boot-riscv/master

Hi Tom, The following changes since commit faac9dee8e0629326dc122f4624fc4897e3f38b0: Prepare v2023.04-rc2 (2023-02-13 18:39:15 -0500) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 7574b6476afc1fd76816be65674

Re: [PULL] u-boot-riscv/master

On Fri, Feb 17, 2023 at 10:01:54AM -0500, Tom Rini wrote: > On Fri, Feb 17, 2023 at 12:12:18PM +0000, Leo Liang wrote: > > > Hi Tom, > > > > The following changes since commit faac9dee8e0629326dc122f4624fc4897e3f38b0: > > > > Prepare v2023.04-rc2 (202

[PULL] u-boot-riscv/master

Hi Tom, The following changes since commit c4ee4fe92e9be120be6d12718273dec6b63cc7d9: Merge tag 'u-boot-imx-20221114' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx (2022-11-14 09:33:36 -0500) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-ri

Re: [PATCH v5 0/3] Add riscv semihosting support in u-boot

Hi Kautuk, Sorry for the late reply. The CI failure still exists and if tested on QEMU(7.0.0) without a gdb attached, it is possible that we get weird output on console.[1] Another thing is that with your patch, QEMU could not exit with Ctrl a + x. This might be the reason for CI failure (timeout

Re: [PATCH v5 0/3] Add riscv semihosting support in u-boot

xists. Thanks! Best regards, Leo > > Thanks. > > On Fri, Dec 2, 2022 at 2:16 PM Leo Liang wrote: > > > Hi Kautuk, > > > > Sorry for the late reply. > > The CI failure still exists and > > if tested on QEMU(7.0.0) without a gdb attached, > > it is

Re: [PATCH v5 3/3] board: qemu-riscv: enable semihosting

Hi Kautuk, We have tested your patchset with QEMU 7.1.0. It generally looks fine, but CI error seems to persist. https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/14314 The error comes from CI testcase timed-out. The reason for the time-out is not yet confirmed, but we suspect it

Re: [PATCH v5 3/3] board: qemu-riscv: enable semihosting

Hi Kautuk, On Tue, Dec 06, 2022 at 05:02:49PM +0530, Kautuk Consul wrote: > Hi Leo, > > On Tue, Dec 6, 2022 at 4:29 PM Leo Liang wrote: > > > > Hi Kautuk, > > > > We have tested your patchset with QEMU 7.1.0. > > It generally looks fine, but CI error seems

[PULL] u-boot-riscv/master

Hi Tom, The following changes since commit 14f2d087a3d6347ba0ff7a7e9aaff6955e53e7a8: Merge tag 'sound-2023-01-rc4' of https://source.denx.de/u-boot/custodians/u-boot-efi (2022-12-06 10:07:01 -0500) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-risc

Re: [PATCH 1/2] riscv: ae350: Fix OF_BOARD boot failure

On Wed, Apr 20, 2022 at 09:14:05AM +0800, Andes wrote: > From: Rick Chen > > Enable OF_HAS_PRIOR_STAGE for ae350 boards with OF_BOARD > > Fixes: 239d22c79520 ("fdt: Enable OF_HAS_PRIOR_STAGE for most boards with > OF_BOARD") > Signed-off-by: Rick Chen > --- > board/AndesTech/ax25-ae350/Kconfi

Re: [PATCH 2/2] riscv: ae350: Fix OF_BOARD boot failure

On Wed, Apr 20, 2022 at 09:23:51AM +0800, Andes wrote: > From: Rick Chen > > Disable BINMAN_FDT for ae350 boards which don't actually use it. > > Fixes: 836eac7c6fe3 ("fdt: Make OF_BOARD a bool option") > Signed-off-by: Rick Chen > --- > configs/ae350_rv32_spl_defconfig | 1 + > configs/ae

Re: [PATCH 1/3] riscv: sifive: unmatched: Adjust for big ramdisk image

On Tue, May 24, 2022 at 12:31:12PM +0800, Bin Meng wrote: > Move kernel_comp_addr_r to an address that comes before the ramdisk > image, since the decompressed kernel size is known to us. This way > we can allow big ramdisk image to be loaded. > > Signed-off-by: Bin Meng > --- > > include/confi

Re: [PATCH 2/3] riscv: sifive: unleashed: Set kernel_comp_addr_r for compressed kernel

On Tue, May 24, 2022 at 12:31:13PM +0800, Bin Meng wrote: > Set kernel_comp_addr_r and kernel_comp_size for compressed kernel. > Adjust existing addresses for ramdisk, so that kernel_comp_addr_r > comes before the ramdisk image, since the decompressed kernel size > is known to us. This way we can a

Re: [PATCH 3/3] riscv: qemu: Set kernel_comp_addr_r for compressed kernel

On Tue, May 24, 2022 at 12:31:14PM +0800, Bin Meng wrote: > Set kernel_comp_addr_r and kernel_comp_size for compressed kernel. > Adjust existing addresses for ramdisk, so that kernel_comp_addr_r > comes before the ramdisk image, since the decompressed kernel size > is known to us. This way we can a

[PULL] u-boot-riscv/master

Hi Tom, The following changes since commit 7e0edcadb09d55d5319fdc862041fd1b874476f5: Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi (2022-05-24 23:29:00 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.gi

Re: [PULL] u-boot-riscv/master

On Fri, May 27, 2022 at 09:30:49AM -0400, Tom Rini wrote: > On Fri, May 27, 2022 at 02:36:29AM +0000, Leo Liang wrote: > > > Hi Tom, > > > > The following changes since commit 7e0edcadb09d55d5319fdc862041fd1b874476f5: > > > > Merge branch 'mast

Re: [PATCH] riscv: cpu: set gp before board_init_f_init_reserve

On Fri, May 20, 2022 at 02:41:17PM +0300, Nikita Shubin wrote: > From: Nikita Shubin > > Restore global pointer before board_init_f_init_reserve call, > as "a0" can be set in harts_early_init call and we end up with > invalid global pointer. > > Signed-off-by: Nikita Shubin > --- > arch/riscv/

Re: [PATCH] riscv: cpu: fu740: Fix typo of date

On Mon, Aug 02, 2021 at 03:33:17PM +0800, Zong Li wrote: > Fixed the typo of date of copyright declaration. > > Signed-off-by: Zong Li > --- > arch/riscv/cpu/fu740/spl.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Leo Yu-Chi Liang

Re: [PATCH v2 1/3] risv: add missing SBI extension definitions

Hi Heinrich, I've noticed that there is also a typo in the commit title "risv". Please correct it in v3 patch as well! Thanks! On Thu, Jul 22, 2021 at 12:33:03AM +0800, Heinrich Schuchardt wrote: > Add the System Reset Extension and the Hart State Management Extension > definitions. > > Add miss

Re: [PATCH 1/1] doc: riscv: flashing SiFive boards

Hi Bin, On Wed, Jul 28, 2021 at 05:18:59PM +0800, Bin Meng wrote: > On Wed, Jul 28, 2021 at 5:03 PM Heinrich Schuchardt > wrote: > > > > nits: missing Could you explain what is missing here? I did not quite catch the point, thanks! > > From: Heinrich Schuchardt > > > We should not use /de

Re: [PATCH 1/2] board: sifive: compile stuff only related to SPL in SPL build

On Tue, Jul 27, 2021 at 05:06:58PM +0800, Zong Li wrote: > As (3581811dc26f "riscv: sifive/fu540: Move SPL related functions to spl.c"), > we put the SPL stuff in spl.c, we don't need to compile unleashed.c and > unmatched.c in SPL build. > > Signed-off-by: Zong Li > --- > board/sifive/unleashed

Re: [PATCH 2/2] board: sifive: overwrite board_fdt_blob_setup in u-boot proper

On Tue, Jul 27, 2021 at 05:06:59PM +0800, Zong Li wrote: > Add board_fdt_blob_setup to return the device tree location which is > passed by prior stage in u-boot proper. The generic board_fdt_blob_setup > always returns _end, it mignt be ok because u-boot SPL would currently > put the dtb there, bu

Re: [PATCH 1/1] doc: riscv: flashing SiFive boards

Hi Bin, On Mon, Aug 02, 2021 at 05:01:07PM +0800, Bin Meng wrote: > Hi Leo, > > On Mon, Aug 2, 2021 at 4:50 PM Leo Liang wrote: > > > > Hi Bin, > > > > On Wed, Jul 28, 2021 at 05:18:59PM +0800, Bin Meng wrote: > > > On Wed, Jul 28, 2021 at

Re: [PATCH 1/1] doc: riscv: flashing SiFive boards

Hi Bin, On Mon, Aug 02, 2021 at 05:48:49PM +0800, Bin Meng wrote: > Hi Leo, > > On Mon, Aug 2, 2021 at 5:17 PM Leo Liang wrote: > > > > Hi Bin, > > On Mon, Aug 02, 2021 at 05:01:07PM +0800, Bin Meng wrote: > > > Hi Leo, > > > > >

[PULL] u-boot-riscv/master

Hi Tom, The following changes since commit a0da2dda4ed9d0aee5265e9cd8876734f9f80e09: Prepare v2021.10-rc2 (2021-08-16 14:18:45 -0400) are available in the Git repository at: g...@source.denx.de:u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 47d73ba4f4a40f17622d93f96b48e

Re: [PATCH] riscv: Add missing sentinel in ocores_i2c.c

On Sun, Aug 15, 2021 at 04:04:03PM -0700, Thomas Skibo wrote: > The ocores_i2c.c driver is missing a sentinel at the end of > the compatible strings list. This causes the "dm compat" command > to spew garbage. > > Signed-off-by: Thomas Skibo > --- > drivers/i2c/ocores_i2c.c | 1 + > 1 file chan

Re: [PATCH] riscv: cpu: set gp before board_init_f_init_reserve

Hi Nikita, On Tue, Aug 02, 2022 at 01:29:24PM +0300, Nikita Shubin wrote: > Hello Leo! > > On Wed, 1 Jun 2022 02:07:34 +0000 > Leo Liang wrote: > > > On Fri, May 20, 2022 at 02:41:17PM +0300, Nikita Shubin wrote: > > > From: Nikita Shubin > > &g

Re: [PATCH] riscv: fix the wrong swap value register

n to complete. >*/ > la t0, hart_lottery > - li s2, 1 > + li t1, 1 > amoswap.w s2, t1, 0(t0) > bnezs2, wait_for_gd_init > #else Reviewed-by: Leo Liang

Re: [PATCH v3 1/1] riscv: Add timer_get_us() for tracing

..@google.com; Bin Meng > >; Paul Walmsley ( Sifive) ; > >Anup Patel ; Sagar Kadam > >; Sean Anderson ; rick > >; Alan Kao ; Leo Liang > > > >Subject: Re: [PATCH v3 1/1] riscv: Add timer_get_us() for tracing > > > >[External Email] Do not click link

Re: [PATCH v3 1/1] riscv: Add timer_get_us() for tracing

Hi Pragnesh, On Mon, Nov 23, 2020 at 06:19:06AM +, Pragnesh Patel wrote: > Hi Leo, > > >-Original Message----- > >From: Leo Liang > >Sent: 23 November 2020 11:28 > >To: Pragnesh Patel > >Cc: Rick Chen ; U-Boot Mailing List >b...@list

[PATCH 1/1] sandbox: Make tracing totally depends on Kconfig

With this patch, 'make sandbox_defconfig', choose tracing support option then 'make', would be enough when trying tracing feature with sandbox. No need to add FTRACE=1 Signed-off-by: Leo Yu-Chi Liang --- config.mk | 2 +- include/configs/sandbox.h | 7 --- lib/Kco

Re: [PATCH] riscv: dts: jh7110: fix indentation

On Mon, Mar 04, 2024 at 09:51:47PM +0100, Leon M. Busch-George wrote: > From: "Leon M. Busch-George" > > Signed-off-by: Leon M. Busch-George > --- > arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Leo Yu-Chi Liang

Re: [PATCH v1 1/2] board: starfive: Update maintainer of VisionFive v2 board

On Fri, Mar 08, 2024 at 02:53:35PM +0800, Minda Chen wrote: > Update the maintainer of Starfive VisionFive v2 board. > > Signed-off-by: Minda Chen > --- > board/starfive/visionfive2/MAINTAINERS | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Leo Yu-Chi Liang

Re: [PATCH v1 2/2] board: starfive: maintainer: Add visionfive2 PCIe driver

On Fri, Mar 08, 2024 at 02:53:36PM +0800, Minda Chen wrote: > Add PCIe driver file to visionfive2 board MAINTAINERS list. > > Signed-off-by: Minda Chen > --- > board/starfive/visionfive2/MAINTAINERS | 1 + > 1 file changed, 1 insertion(+) Reviewed-by: Leo Yu-Chi Liang

Re: [PATCH] riscv: dts: jh7110: Enable PLL node in SPL

On Tue, Mar 05, 2024 at 07:00:11PM -0800, Bo Gan wrote: > Previously PLL node was missing from SPL dts. This caused BUS_ROOT > to stay on OSC clock (24Mhz). As a result, all peripherals have to > run at a much lower frequency, and loading from sdcard/emmc is slow. > Thus, enabling PLL node in dts t

Re: [PATCH] riscv: sifive: fu740: reduce DDR speed from 1866MT/s to 1600MT/s

On Thu, Feb 22, 2024 at 03:52:03PM +0100, thomas.per...@bootlin.com wrote: > From: Thomas Perrot > > It appears that there is some timing marginality either in the > board layout or the SoC that results in occasional data corruption > on some boards. > We observed this issue on some of the new Hi

Re: [PATCH] starfive: visionfive2: switch to standard boot

On Wed, Feb 21, 2024 at 01:00:14PM +0100, Nam Cao wrote: > Distro boot scripts are deprecated. Use standard boot instead. > > Signed-off-by: Nam Cao > --- > configs/starfive_visionfive2_defconfig | 2 +- > include/configs/starfive-visionfive2.h | 14 +- > 2 files changed, 2 insertio

[GIT PULL] u-boot-riscv/master

Hi Tom, The following changes since commit f3c979dd0053c082d2df170446923e7ce5edbc2d: Prepare v2024.04-rc4 (2024-03-11 13:11:46 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 544af8207c69829b1697f3aa5d

Re: [PATCH v2 2/3] riscv: dts: sophgo: Add clk node and sdhci node

On Sun, Mar 10, 2024 at 01:51:56AM +0800, Kongyang Liu wrote: > Add clk node and sdhci node for cv18xx SoCs according to patches from Linux > kernel. > > clk: > https://lore.kernel.org/all/ia1pr20mb4953f9ad6792013b54636f05bb...@ia1pr20mb4953.namprd20.prod.outlook.com/ > sdhci: https://lore.kernel

Re: [PATCH v2 1/2] riscv: cpu: cv1800b: Add support for cv1800b SoC

On Sun, Mar 10, 2024 at 12:54:56AM +0800, Kongyang Liu wrote: > Add Sophgo cv1800b SoC to support RISC-V arch. > > Signed-off-by: Kongyang Liu > --- > > Changes in v2: > - Remove duplicate code in function cleanup_before_linux > > arch/riscv/Kconfig | 1 + > arch/riscv/cpu/cv1800

Re: [PATCH v2 2/2] riscv: cache: Implement dcache for cv1800b

On Sun, Mar 10, 2024 at 12:54:57AM +0800, Kongyang Liu wrote: > Add dcache operations invalidate_dcache_range and flush_dcache_range for > cv1800b. > > Signed-off-by: Kongyang Liu > --- > > (no changes since v1) > > arch/riscv/cpu/cv1800b/Makefile | 1 + > arch/riscv/cpu/cv1800b/cache.c | 45

Re: [PATCH 1/3] board: milkv_duo: Add init code for Milk-V Duo ethernet

On Sun, Mar 10, 2024 at 01:56:44PM +0800, Kongyang Liu wrote: > Initialize register in cv1800b ethernet phy to make it compatible with > generic phy driver > > Signed-off-by: Kongyang Liu > --- > > board/sophgo/milkv_duo/Makefile | 3 +- > board/sophgo/milkv_duo/board.c| 4 ++ > board/s

Re: [PATCH 2/3] riscv: dts: sophgo: Add ethernet node

On Sun, Mar 10, 2024 at 01:56:45PM +0800, Kongyang Liu wrote: > Add ethernet node for cv1800b SoC > > Signed-off-by: Kongyang Liu > --- > > arch/riscv/dts/cv18xx.dtsi | 6 ++ > 1 file changed, 6 insertions(+) Hi KongYang, Will there be a patch adding this ethernet node for kernel as well

Re: [PATCH 3/3] configs: milkv_duo: Add ethernet configs

On Sun, Mar 10, 2024 at 01:56:46PM +0800, Kongyang Liu wrote: > Add configs related to ethernet and ethernet boot command for Sophgo Milk-V > Duo board > > Signed-off-by: Kongyang Liu > --- > > configs/milkv_duo_defconfig | 4 > 1 file changed, 4 insertions(+) Reviewed-by: Leo Yu-Chi Lian

Re: [PATCH v2 3/3] configs: milkv_duo: Add SD card configs

On Sun, Mar 10, 2024 at 01:51:57AM +0800, Kongyang Liu wrote: > Add configs related to sdhci and mmc for Sophgo Milk-V Duo board > > Signed-off-by: Kongyang Liu > --- > > (no changes since v1) > > configs/milkv_duo_defconfig | 10 ++ > 1 file changed, 10 insertions(+) Reviewed-by: Leo

Re: [PATCH v2 1/3] mmc: cv1800b: Add sdhci driver support for cv1800b SoC

On Sun, Mar 10, 2024 at 01:51:55AM +0800, Kongyang Liu wrote: > Add sdhci driver for cv1800b SoC. > > Signed-off-by: Kongyang Liu > --- > > Changes in v2: > - Refactored and simplified some of the code. > > drivers/mmc/Kconfig | 13 > drivers/mmc/Makefile| 1 + > driver

Re: [PATCH] riscv: Repeat virtio scan

Hi Łukasz, On Mon, Feb 19, 2024 at 01:41:39PM +0100, Łukasz Stelmach wrote: > The first time virtio_init() gets called from board_init() PCI isn't > ready. Thus any virtio-over-PCI (e.g. network interfaces) devices can't > be detected and used without additional `virtio scan` scan in the shell > o

Re: [PATCH] spl: riscv: opensbi: fix check of PAYLOAD_ARGS_ADDR

On Fri, Mar 22, 2024 at 07:36:37PM +0800, Randolph wrote: > When Falcon Mode is enabled on RISC-V, use CONFIG_VAL > to check PAYLOAD_ARGS_ADDR, not CONFIG_IS_ENABLED. > > Signed-off-by: Randolph > --- > common/spl/spl_opensbi.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Tested-by:

[GIT PULL] u-boot-riscv/master

Hi Tom, The following changes since commit dde373bde392c38649c8c4420e0c98ef8d38d9dc: Prepare v2024.04-rc5 (2024-03-25 21:56:50 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 0cfe1bc6ed9b322d2b03ded317

Re: [PATCH v2 1/6] riscv: do not set default fdt for VisionFive 2

On Thu, Mar 21, 2024 at 07:11:44PM +0100, Heinrich Schuchardt wrote: > Currently in set_fdtfile() we set the value of environment variable fdtfile > unconditionally. The implies that a value in the environment will be > ignored. > > With the patch environment variable fdtfile will only be set if i

Re: [PATCH v2 2/6] eeprom: starfive: function get_product_id_from_eeprom()

On Thu, Mar 21, 2024 at 07:11:45PM +0100, Heinrich Schuchardt wrote: > Export a function get_product_id_from_eeprom() to read the product ID. > This value can be used for fixing up the device-tree on JH7110 based > products. > > Signed-off-by: Heinrich Schuchardt > --- > v2: > no change > -

Re: [PATCH v2 5/6] riscv: starfive: avoid including common.h

On Thu, Mar 21, 2024 at 07:11:48PM +0100, Heinrich Schuchardt wrote: > The usage of common.h is deprecated. Remove it from board files. > > Signed-off-by: Heinrich Schuchardt > --- > v2: > no change > --- > board/starfive/visionfive2/spl.c| 1 - > board/starfive/visionf

Re: [PATCH v2 3/6] riscv: set fdtfile on Milk-V Mars

On Thu, Mar 21, 2024 at 07:11:46PM +0100, Heinrich Schuchardt wrote: > Set environment variable fdtfile to the correct value for the Milk-V Mars > board. > > Signed-off-by: Heinrich Schuchardt > --- > v2: > rebase patch > --- > .../visionfive2/starfive_visionfive2.c| 43 +++

Re: [PATCH v2 4/6] board: starfive: support Milk-V Mars board

Hi Heinrich, On Thu, Mar 21, 2024 at 07:11:47PM +0100, Heinrich Schuchardt wrote: > The differences between the Milk-V Mars board and the VisionFive 2 board > are small enough that we can support both using the same U-Boot build. > > * The model and compatible property are taken from proposed Lin

Re: [PATCH v2 4/6] board: starfive: support Milk-V Mars board

Hi Heinrich, On Wed, Mar 27, 2024 at 12:03:01PM +0100, Heinrich Schuchardt wrote: > [EXTERNAL MAIL] > > On 24.03.24 16:00, Aurelien Jarno wrote: > > On 2024-03-21 19:11, Heinrich Schuchardt wrote: > > > The differences between the Milk-V Mars board and the VisionFive 2 board > > > are small enoug

Re: [PATCH v1 1/2] riscv: don't read riscv, isa in the riscv cpu's get_desc()

On Mon, Mar 18, 2024 at 03:16:02PM +, Conor Dooley wrote: > From: Conor Dooley > > cpu_get_desc() for the RISC-V CPU currently reads "riscv,isa" to get > the description, but it is no longer a required property and cannot be > assummed to always be present, as the new "riscv,isa-extensions" a

Re: [PATCH v1 2/2] riscv: support extension probing using riscv, isa-extensions

On Mon, Mar 18, 2024 at 03:16:03PM +, Conor Dooley wrote: > From: Conor Dooley > > A new property has been added, with an extensive rationale at [1], that > can be used in place of "riscv,isa" to indicate what extensions are > supported by a given platform that is a list of strings rather tha

Re: [[PATCH v2]] riscv: add backtrace support

On Tue, Sep 05, 2023 at 01:12:53PM +0100, Ben Dooks wrote: > When debugging, it is useful to have a backtrace to find > out what is in the call stack as the previous function (RA) > may not have been the culprit. > > Since this adds size to the build, do not add it by default > and avoid putting i

Re: [PATCH 01/11] riscv: global_data.h: Correct the comment for PLICSW

On Thu, Jan 19, 2023 at 03:05:34PM +0800, Yu Chien Peter Lin wrote: > PLIC is used for external interrupt, while PLICSW is an Andes-specific > design for software interrupt. > > Signed-off-by: Yu Chien Peter Lin > --- > arch/riscv/include/asm/global_data.h | 2 +- > 1 file changed, 1 insertion(+

Re: [PATCH 02/11] riscv: Remove redundant Kconfig "RISCV_NDS_CACHE"

On Thu, Jan 19, 2023 at 03:05:35PM +0800, Yu Chien Peter Lin wrote: > From: Leo Yu-Chi Liang > > There is no need for RISCV_NDS_CACHE config to control cache switches. > > Signed-off-by: Leo Yu-Chi Liang > Reviewed-by: Yu Chien Peter Lin > --- > arch/riscv/cpu/ax25/Kconfig | 10 - > arch/

Re: [PATCH 03/11] board: AndesTech: ax25-ae350.c: Enable v5l2-cache in spl_board_init()

On Thu, Jan 19, 2023 at 03:05:36PM +0800, Yu Chien Peter Lin wrote: > The L2-cache is not enabled currently, the enbale_caches() will call > the v5l2_enable() callback to enable it in SPL. > > Signed-off-by: Yu Chien Peter Lin > --- > board/AndesTech/ax25-ae350/ax25-ae350.c | 17 +---

Re: [PATCH 04/11] driver: cache: cache-v5l2: Update memory-mapped scheme to support Gen2 platform

On Thu, Jan 19, 2023 at 03:05:37PM +0800, Yu Chien Peter Lin wrote: > The L2C configuration register has MAP field to indicate its version > is v0 (Gen1) or v1 (Gen2) L2-cache. This patch makes the driver > compatible with both memory-mapped scheme. > > Signed-off-by: Yu Chien Peter Lin > --- >

Re: [PATCH 05/11] riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init()

Hi Peter, On Thu, Jan 19, 2023 at 03:05:38PM +0800, Yu Chien Peter Lin wrote: > This patch improves the cache enabling operation in harts_early_init(), > also moves the CSR definition to include/asm/arch-andes/csr.h and drops > unnecessary i/d-cache disable functions from cleanup_before_linux(). >

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