On Tue, Oct 25, 2022 at 08:58:49AM +0100, Conor Dooley wrote:
> The initial devicetree for PolarFire SoC incorrectly created a fixed
> frequency clock in the devicetree to represent the msspll, but the
> msspll is not a fixed frequency clock. The actual reference clock on a
> board is either 125 or 100 MHz, 125 MHz in the case of the icicle kit.
> Swap the incorrect representation of the msspll out for the actual
> reference clock.
>
> Fixes: dd4ee416a6 ("riscv: dts: Add device tree for Microchip Icicle Kit")
> Signed-off-by: Conor Dooley <conor.doo...@microchip.com>
> ---
> arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 4 ++++
> arch/riscv/dts/microchip-mpfs.dtsi | 14 ++++++--------
> 2 files changed, 10 insertions(+), 8 deletions(-)
Reviewed-by: Leo Yu-Chi Liang <ycli...@andestech.com>
