Hi Kautuk, Sorry for the late reply. The CI failure still exists and if tested on QEMU(7.0.0) without a gdb attached, it is possible that we get weird output on console.[1]
Another thing is that with your patch, QEMU could not exit with Ctrl a + x. This might be the reason for CI failure (timeout). Could you take a look at this? Yet with a gdb attached, everything works as expected, So maybe we could disable semihosting as default? Best regards, Leo [1] The weird console output looks like below, it outputs random character without us typing anything. U-Boot 2022.10-rc5 (Dec 02 2022 - 16:27:43 +0800) CPU: rv64imafdcsuh Model: riscv-virtio,qemu DRAM: 2 GiB Core: 35 devices, 15 uclasses, devicetree: board Flash: 32 MiB Loading Environment from nowhere... OK In: serial_semihosting Out: serial_semihosting Err: serial_semihosting Net: eth0: virtio-net#1 Hit any key to stop autoboot: 0 => 55555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555555 55555555555555555555555555555555555555555555555555555555555555555555 On Tue, Nov 29, 2022 at 12:27:51PM +0530, Kautuk Consul wrote: > I have tested it both on Qemu and Ventana's internal simulator. > > On Tue, Nov 29, 2022 at 12:06 PM Bin Meng <bmeng...@gmail.com> wrote: > > > Hi Kautuk, > > > > On Tue, Nov 29, 2022 at 2:29 PM Kautuk Consul <kcon...@ventanamicro.com> > > wrote: > > > > > > Hi, > > > > > > Can someone pick this patchset up ? > > > > > > It has been reviewed and there has been no comment on this in recent > > days. > > > > > > Thanks. > > > > > > On Fri, Sep 23, 2022 at 12:33 PM Kautuk Consul <kcon...@ventanamicro.com> > > wrote: > > >> > > >> Semihosting is a mechanism that enables code running on > > >> a target to communicate and use the Input/Output > > >> facilities on a host computer that is running a debugger. > > >> This patchset adds support for semihosting in u-boot > > >> for RISCV64 targets. > > >> > > >> CHANGES since v4: > > >> - Check arch dependencies for SEMIHOSTING as well as > > SPL_SEMIHOSTING > > >> config options as per Sean's comment. > > >> - arch/riscv/lib/interrupts.c: Check for post and pre instructions > > >> of the ebreak statement whether they are as per the RISCV > > >> semihosting specification. Only then do a disable_semihosting > > >> and epc += 4 and return. > > >> > > >> Compilation and test commands for SPL and S-mode configurations > > >> ================================================================= > > >> > > >> U-Boot S-mode on QEMU virt > > >> ---------------------------- > > >> // Compilation of S-mode u-boot > > >> ARCH=riscv > > >> CROSS_COMPILE=riscv64-unknown-linux-gnu- > > >> make qemu-riscv64_smode_defconfig > > >> make > > >> // Run riscv 64-bit u-boot with opensbi on qemu > > >> qemu-system-riscv64 -M virt -m 256M -display none -serial stdio -bios\ > > >> opensbi/build/platform/generic/firmware/fw_jump.bin -kernel\ > > >> u-boot/u-boot.bin > > >> > > >> U-Boot SPL on QEMU virt > > >> ------------------------ > > >> // Compilation of u-boot-spl > > >> ARCH=riscv > > >> CROSS_COMPILE=riscv64-unknown-linux-gnu- > > >> make qemu-riscv64_spl_defconfig > > >> make OPENSBI=opensbi/build/platform/generic/firmware/fw_dynamic.bin > > >> // Run 64-bit u-boot-spl in qemu > > >> qemu-system-riscv64 -M virt -m 256M -display none -serial stdio -bios\ > > >> u-boot/spl/u-boot-spl.bin -device\ > > >> loader,file=u-boot/u-boot.itb,addr=0x80200000 > > >> > > > > Do you have instructions on how to actually test semihosting? Does it > > require a JTAG debugger? But I see you are using QEMU? > > > > Regards, > > Bin > >
