Hi YanHong,
There are some errors when "make htmldocs".
I thought v4 was the final patch set and these are minor build errors,
so I have fixed them up on my side.
Now that since you are adding new defconfig and spinning a v5 patch set,
could you also fix those build errors that came from "make ht
On Tue, Jul 04, 2023 at 07:13:20PM +0800, Yu Chien Peter Lin wrote:
> On some AE350 boards, we need to explicitly initialize the priority
> registers to a non-zero value so the boot hart can instruct secondary
> harts to jump to OpenSBI.
>
> This patch also updates the information about PLICSW.
>
On Tue, Jul 04, 2023 at 07:13:21PM +0800, Yu Chien Peter Lin wrote:
> The 'booti' command is unable to boot Image.gz due to the absence
> of required environment variables 'kernel_comp_addr_r' and
> 'kernel_comp_size'.
>
> This commit adds these variables and reorganizes the memory layout
> to pre
On Tue, Jul 04, 2023 at 02:14:21AM +0200, Heinrich Schuchardt wrote:
> Describe which numeric values can be used for as scratch options for
> OpenSBI.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> common/spl/Kconfig | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
Reviewed-by: L
On Tue, Jun 20, 2023 at 01:55:00PM +0800, Bin Meng wrote:
> Use the latest OpenSBI v1.2 release binaries for the RISC-V CI.
>
> Signed-off-by: Bin Meng
> ---
>
> .azure-pipelines.yml | 8
> .gitlab-ci.yml | 8
> 2 files changed, 8 insertions(+), 8 deletions(-)
>
Reviewe
Hi Tom,
The following changes since commit e80f4079b3a3db0961b73fa7a96e6c90242d8d25:
Merge tag 'v2023.07-rc6' into next (2023-07-05 11:28:55 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git riscv-for-next
for you to fetch changes up t
On Thu, Jun 15, 2023 at 05:36:44PM +0800, Yanhong Wang wrote:
> Add ethernet device tree node to support StarFive ethernet driver for
> the JH7110 RISC-V SoC.
>
> Signed-off-by: Yanhong Wang
> ---
> .../dts/jh7110-starfive-visionfive-2.dtsi | 34 +
> arch/riscv/dts/jh7110.dtsi
On Thu, Jun 15, 2023 at 05:36:45PM +0800, Yanhong Wang wrote:
> The difference between 1.2A and 1.3B is dynamically configured according
> to the PCB version, and there is no difference on the board device tree,
> so the same DT file can be used.
>
> Signed-off-by: Yanhong Wang
> ---
> arch/risc
On Thu, Jun 15, 2023 at 05:36:46PM +0800, Yanhong Wang wrote:
> The defconfig file name for StarFive VisionFive2 has been changed, and
> the documentation description has also changed.
>
> Signed-off-by: Yanhong Wang
> ---
> doc/board/starfive/visionfive2.rst | 6 +++---
> 1 file changed, 3 inse
On Thu, Jun 15, 2023 at 05:36:47PM +0800, Yanhong Wang wrote:
> Enable DWC_ETH_QOS and PHY_MOTORCOMM configuration to support ethernet
> function for StarFive VisionFive 2 board,including versions 1.2A and
> 1.3B.
>
> Signed-off-by: Yanhong Wang
> ---
> configs/starfive_visionfive2_defconfig | 9
On Thu, Jun 15, 2023 at 05:36:48PM +0800, Yanhong Wang wrote:
> Enabled ID_EEPROM configuration for StarFive VisionFive2 board.
>
> Signed-off-by: Yanhong Wang
> ---
> arch/riscv/include/asm/arch-jh7110/eeprom.h | 13 +
> board/starfive/visionfive2/Makefile | 1 +
> .../visionfive
On Thu, Jun 15, 2023 at 05:36:49PM +0800, Yanhong Wang wrote:
> Add support "atmel,24c04" eeprom for StarFive VisionFive2 board.
>
> Signed-off-by: Yanhong Wang
> ---
> .../dts/jh7110-starfive-visionfive-2-u-boot.dtsi | 14 ++
> arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi |
On Thu, Jun 15, 2023 at 05:36:50PM +0800, Yanhong Wang wrote:
> Enabled ID_EEPROM and I2C configuration for StarFive VisionFive2 board.
>
> Signed-off-by: Yanhong Wang
> ---
> .../visionfive2/starfive_visionfive2.c| 13 +
> configs/starfive_visionfive2_defconfig| 19 +
On Thu, Jun 15, 2023 at 05:36:51PM +0800, Yanhong Wang wrote:
> StarFive VisionFive 2 has two versions, 1.2A and 1.3B, each version of
> DDR capacity includes 2G/4G/8G, a DT can not support multiple
> capacities, so the capacity size information is recorded to EEPROM, when
> DDR initialization requ
Hi Tom,
The following changes since commit 8e21064cb3452950b09301baec06d86e37342471:
Merge tag 'efi-2023-07-rc7' of
https://source.denx.de/u-boot/custodians/u-boot-efi (2023-07-11 13:27:32 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.
On Fri, Jul 14, 2023 at 06:41:09PM +0900, Chanho Park wrote:
> Apply the trailing space changes in the guide document.
>
> Signed-off-by: Chanho Park
> ---
> doc/board/starfive/visionfive2.rst | 18 +-
> 1 file changed, 9 insertions(+), 9 deletions(-)
Reviewed-by: Leo Yu-Chi Lia
On Fri, Jul 14, 2023 at 06:41:08PM +0900, Chanho Park wrote:
> Adds a trailing space to SYS_PROMPT to make it easier to distinguish
> between commands and the prompt.
>
> Signed-off-by: Chanho Park
> ---
> configs/starfive_visionfive2_defconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletio
On Thu, Jul 20, 2023 at 07:37:29PM +0800, Minda Chen wrote:
> Add PCIe device rtl8169 net adapter driver support.
>
> Signed-off-by: Minda Chen
> ---
> configs/starfive_visionfive2_defconfig | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Leo Yu-Chi Liang
On Thu, Jul 20, 2023 at 07:37:26PM +0800, Minda Chen wrote:
> While compiling rtl8169.c, There are many "make pointer from
> integer without a cast" compile warnings. fix them with
> adding cast.
>
> Signed-off-by: Minda Chen
> ---
> drivers/net/rtl8169.c | 12 ++--
> 1 file changed, 6 i
On Thu, Jul 20, 2023 at 07:37:27PM +0800, Minda Chen wrote:
> For RISC-V architeture, hardware maintain the dcache coherency.
> Software do not flush the cache. So even cache-line size larger
> than descriptor size, driver can work.
>
> Signed-off-by: Minda Chen
> ---
> drivers/net/rtl8169.c | 4
On Thu, Jul 20, 2023 at 07:37:28PM +0800, Minda Chen wrote:
> Add rtl8169 NIC device ID and reorder the device ID.
>
> Signed-off-by: Minda Chen
> ---
> drivers/net/rtl8169.c | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
Reviewed-by: Leo Yu-Chi Liang
On Sun, Jun 11, 2023 at 04:54:17PM -0700, Bo Gan wrote:
> Harts need to use per-hart stack before any function call, even if that
> function is a simple one. When the callee uses stack for register save/
> restore, especially RA, if nested call, concurrent access by multiple
> harts on the same sta
On Fri, Jul 07, 2023 at 06:50:07PM +0800, Hal Feng wrote:
> From: Xingyu Wu
>
> Drop the PLL part in SYSCRG driver and separate to be a single
> PLL driver of which the compatible is "starfive,jh7110-pll".
>
> Signed-off-by: Xingyu Wu
> Signed-off-by: Hal Feng
> ---
> drivers/clk/starfive/clk
On Fri, Jul 07, 2023 at 06:50:08PM +0800, Hal Feng wrote:
> From: Xingyu Wu
>
> Add child node about PLL clock controller in sys_syscon node.
>
> Signed-off-by: Xingyu Wu
> Signed-off-by: Hal Feng
> ---
> arch/riscv/dts/jh7110.dtsi | 8 +++-
> 1 file changed, 7 insertions(+), 1 deletion(-
On Fri, Jul 07, 2023 at 06:50:09PM +0800, Hal Feng wrote:
> From: Xingyu Wu
>
> Change the PLL clock source from syscrg to sys_syscon child node.
>
> Signed-off-by: Xingyu Wu
> Signed-off-by: Hal Feng
> ---
> arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 6 +++---
> arch/riscv/dts/jh7110
On Fri, Jul 07, 2023 at 06:50:10PM +0800, Hal Feng wrote:
> From: Xingyu Wu
>
> The clock id needs to be changed to be consistent with Linux.
>
> Signed-off-by: Xingyu Wu
> Signed-off-by: Hal Feng
> ---
> .../dt-bindings/clock/starfive,jh7110-crg.h | 101 +-
> 1 file changed
On Fri, Jul 07, 2023 at 06:50:11PM +0800, Hal Feng wrote:
> From: Xingyu Wu
>
> Modify the drivers to add of_xlate ops and transform clock id.
>
> Signed-off-by: Xingyu Wu
> Signed-off-by: Hal Feng
> ---
> drivers/clk/starfive/clk-jh7110-pll.c | 29 ++-
> drivers/clk/starfive/clk-jh7110.c
On Mon, Jul 24, 2023 at 09:03:10AM +0200, Heinrich Schuchardt wrote:
> CONFIG_SPL_PCI_PNP=y without CONFIG_SPL_PCI=y makes no sense.
>
> Move CONFIG_SPL_PCI_PNP to the SPL menu and add the missing dependency.
>
> Fixes: 32f5e9e5c1a7 ("nvme: pci: Enable for SPL")
> Signed-off-by: Heinrich Schuchar
Hi Tom,
The following changes since commit 247aa5a191159ea7e03bf1918e22fbbb784cd410:
Merge branch '2023-07-21-assorted-TI-platform-updates' (2023-07-21 19:33:05
-0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch change
On Thu, Jul 20, 2023 at 07:23:31PM +0800, Minda Chen wrote:
> From: Mason Huo
>
> Add pcie driver for StarFive JH7110, Also add PLDA
> PCIe controller common driver functions.
>
> Several devices are tested:
> a) M.2 NVMe SSD
> b) Realtek 8169 Ethernet adapter.
>
> Signed-off-by: Mason Huo
> S
On Thu, Jul 20, 2023 at 07:23:32PM +0800, Minda Chen wrote:
> From: Mason Huo
>
> Add PCIe host driver and nvme driver in configure file.
>
> Signed-off-by: Mason Huo
> Signed-off-by: Minda Chen
> ---
> configs/starfive_visionfive2_defconfig | 8
> 1 file changed, 8 insertions(+)
Re
On Thu, Jul 20, 2023 at 07:23:33PM +0800, Minda Chen wrote:
> From: Mason Huo
>
> Enable and add pinctrl configuration for PCIe host controller.
>
> Signed-off-by: Mason Huo
> Signed-off-by: Minda Chen
> ---
> .../dts/jh7110-starfive-visionfive-2.dtsi | 11 +++
> arch/riscv/dts/jh7110.dts
On Thu, Oct 12, 2023 at 01:35:34PM +0800, Randolph wrote:
> Source hart information is not necessary in IPI, so we could
> use single-bit-per-hart strategy to rearrange PLICSW mapping.
>
> Bit 0 of Interrupt Pending Bits is hardwired to 0.
> Therefore, we use bit 1 to send IPI to hart 0,
> bit 2 t
On Tue, Oct 10, 2023 at 05:49:18PM +0900, Chanho Park wrote:
> Enable BOOTSTAGE configuration and its command for visionfive2 board.
> The feature can be useful for analyzing the elapsed time between boot
> stages.
>
> TODO: define / reserve memory region for boot stage stash
>
> StarFive # boots
On Thu, Oct 12, 2023 at 02:35:08PM +0800, Randolph wrote:
> Fork from ae350_rv[32/64]_spl_[xip]_defconfig and
> append CONFIG_SPL_LOAD_FIT_OPENSBI_OS_BOOT=y
>
> Signed-off-by: Randolph
> ---
> configs/ae350_rv32_falcon_defconfig | 60
> configs/ae350_rv32_falcon_xip_
On Thu, Oct 12, 2023 at 02:35:09PM +0800, Randolph wrote:
> Originally, u-boot SPL will place the DTB directly after the kernel,
> but the size of the kernel does not include the BSS section, This
> means that u-boot SPL places the DTB in the kernel BSS section causing
> the DTB to be cleared by th
On Wed, Aug 09, 2023 at 06:49:30PM +0800, Yu Chien Peter Lin wrote:
> This patch adds ISA string to the -march to generate zbb instructions
> for U-Boot binaries, along with optimized string functions introduced
> from Linux kernel.
>
> Signed-off-by: Yu Chien Peter Lin
> ---
> arch/riscv/Kconfi
On Tue, Oct 17, 2023 at 11:38:45AM -0400, Tom Rini wrote:
> On Wed, Aug 09, 2023 at 06:49:30PM +0800, Yu Chien Peter Lin wrote:
>
> > This patch adds ISA string to the -march to generate zbb instructions
> > for U-Boot binaries, along with optimized string functions introduced
> > from Linux kerne
Hi Tom,
The following changes since commit 9a0cf3993f71043ba08c315572c54622de42d447:
Merge branch '2023-10-17-spl-test-some-load-methods' (2023-10-18 08:28:00
-0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes
On Sun, Oct 29, 2023 at 09:45:32AM +0100, Heinrich Schuchardt wrote:
> If CSRs like seed are readable by S-mode, may not be determinable by
> S-mode. For safe driver probing allow to resume via a longjmp after an
> exception.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> v2:
> new patch
>
On Sun, Oct 29, 2023 at 09:45:33AM +0100, Heinrich Schuchardt wrote:
> The Zkr ISA extension (ratified Nov 2021) introduced the seed CSR. It
> provides an interface to a physical entropy source.
>
> A RNG driver based on the seed CSR is provided. It depends on
> mseccfg.sseed being set in the SBI
On Wed, Oct 25, 2023 at 12:15:43AM +0200, Heinrich Schuchardt wrote:
> Use the most recent upstream release of OpenSBI for CI testing.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> .azure-pipelines.yml | 8
> .gitlab-ci.yml | 8
> 2 files changed, 8 insertions(+), 8 dele
Hi Xiang,
On Tue, Oct 31, 2023 at 02:16:22PM +0800, merle w wrote:
> drivers/rng/riscv_zkr_rng.c:10:10: fatal error: interrupt.h: No such
> file or directory
> 10 | #include
> | ^
> compilation terminated.
>
> Where is this interrupt.h?
I think this file is created by the first patch
On Tue, Oct 31, 2023 at 12:32:12AM -0500, Samuel Holland wrote:
> Clean things up for the next time somebody adds a target.
>
> Signed-off-by: Samuel Holland
> ---
>
> arch/riscv/Kconfig | 18 +-
> 1 file changed, 9 insertions(+), 9 deletions(-)
Reviewed-by: Leo Yu-Chi Liang
On Tue, Oct 31, 2023 at 12:35:41AM -0500, Samuel Holland wrote:
> This is required on CPUs which always operate in CLIC mode, such as the
> T-HEAD E906 and E907. Per the CLIC specification: "In this mode, the
> trap vector base address held in mtvec is constrained to be aligned on a
> 64-byte or la
On Tue, Oct 31, 2023 at 12:37:20AM -0500, Samuel Holland wrote:
> Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a
> vendor-specific way to invalidate a portion of the instruction cache.
> Allow them to override invalidate_icache_range().
>
> Signed-off-by: Samuel Holland
> ---
>
> a
On Tue, Oct 31, 2023 at 02:55:51PM +0200, Heinrich Schuchardt wrote:
> If CSRs like seed are readable by S-mode, may not be determinable by
> S-mode. For safe driver probing allow to resume via a longjmp after an
> exception.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> v3:
> Add API docu
On Tue, Oct 31, 2023 at 05:55:59PM +0900, Chanho Park wrote:
> Add gpio.h header file that includes JH7110 helper macros. The file is
> imported from StarFive github[1] with small changes such as alignment.
>
> [1]: https://github.com/starfive-tech/u-boot
>
> Signed-off-by: Chanho Park
> ---
>
On Tue, Oct 31, 2023 at 05:56:00PM +0900, Chanho Park wrote:
> JTAG pins are mapped as below. To access the JTAG pins, we need to
> control the GPIO pins from SPL which seems to be the earliest stage for
> JTAG.
>
> - JTAG nTRST: GPIO36 / Input
> - JTAG TDI: GPIO61 / Input
> - JTAG TMS: GPIO63
On Wed, Nov 01, 2023 at 09:16:48PM +0900, Chanho Park wrote:
> This imports mmio functions from Linux's arch/riscv/include/asm/mmio.h
> to use read/write[b|w|l|q]_relaxed functions.
>
> Signed-off-by: Chanho Park
> ---
> arch/riscv/include/asm/io.h | 45 +
> 1
On Wed, Nov 01, 2023 at 09:16:49PM +0900, Chanho Park wrote:
> Add STGCLK_SEC_HCLK and STGCLK_SEC_MISCAHB clocks for JH7110 TRNG
> device.
>
> Signed-off-by: Chanho Park
> ---
> drivers/clk/starfive/clk-jh7110.c | 10 ++
> 1 file changed, 10 insertions(+)
Reviewed-by: Leo Yu-Chi Liang
On Wed, Nov 01, 2023 at 09:16:50PM +0900, Chanho Park wrote:
> Adds to support JH7110 TRNG driver which is based on linux kernel's
> jh7110-trng.c. This can support to generate 256-bit random numbers and
> 128-bit but this makes 256-bit default for convenience.
>
> Signed-off-by: Chanho Park
> --
On Wed, Nov 01, 2023 at 09:16:51PM +0900, Chanho Park wrote:
> Adds jh7110 trng device tree node.
>
> Signed-off-by: Chanho Park
> ---
> arch/riscv/dts/jh7110.dtsi | 10 ++
> 1 file changed, 10 insertions(+)
Reviewed-by: Leo Yu-Chi Liang
Hi Tom,
The following changes since commit a803f87202aa48974bdff4d8100464a8288931e4:
Merge https://source.denx.de/u-boot/custodians/u-boot-mmc (2023-11-01
09:44:33 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch ch
On Sat, Aug 19, 2023 at 03:12:49PM +0200, Heinrich Schuchardt wrote:
> The DBCN extension provides a Console Write Byte call.
> Implement function sbi_dbcn_write_byte to invoke it.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> arch/riscv/include/asm/sbi.h | 1 +
> arch/riscv/lib/sbi.c
On Sat, Aug 19, 2023 at 03:12:50PM +0200, Heinrich Schuchardt wrote:
> Use the DBCN SBI extension to implement a debug console.
> Make it the default for S-mode RISC-V.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> drivers/serial/Kconfig | 3 ++-
> drivers/serial/serial_sbi.c | 19 +++
On Mon, Aug 14, 2023 at 06:05:28PM +0200, Torsten Duwe wrote:
> For the architectural timer on riscv, there already is a defined
> device tree binding[1]. Allow timer instances to be created from
> device tree matches, but for now retain the old mechanism, which
> registers the timer biggy-back wit
On Mon, Aug 14, 2023 at 06:05:33PM +0200, Torsten Duwe wrote:
> The JH7110 has the arhitectural CPU timer on all 5 rv64 cores.
> Note that in the device tree.
>
> Signed-off-by: Torsten Duwe
> ---
> arch/riscv/dts/jh7110.dtsi | 9 +
> 1 file changed, 9 insertions(+)
Reviewed-by: Leo Yu-
On Fri, Aug 11, 2023 at 04:12:25PM +0900, Seung-Woo Kim wrote:
> fdt_fixup_ethernet() sets eth0 mac address from ethaddr. Set
> ethaddr to environment instead of eth0addr.
>
> Signed-off-by: Seung-Woo Kim
> ---
> board/starfive/visionfive2/visionfive2-i2c-eeprom.c | 2 +-
> 1 file changed, 1 ins
On Fri, Aug 25, 2023 at 12:25:20AM +0800, Shengyu Qu wrote:
> Starfive JH7110 needs to clear L2 LIM to zero before use or ECC error
> would be triggered. Currently, we use DDR ram for SPL malloc arena on
> Visionfive 2 board in defconfig, but it's also possible to use L2 LIM as
> SPL malloc arena.
On Fri, Aug 25, 2023 at 12:25:21AM +0800, Shengyu Qu wrote:
> SPL_SYS_MALLOC_CLEAR_ON_INIT would enable SYS_MALLOC_CLEAR_ON_INIT by
> default, but that's not need on JH7110, so disable that.
>
> Signed-off-by: Shengyu Qu
> ---
> configs/starfive_visionfive2_defconfig | 2 ++
> 1 file changed, 2
On Mon, Aug 28, 2023 at 06:49:36PM +0900, Chanho Park wrote:
> Below warning can be occurred when CONFIG_BOOTSTAGE and
> !CONFIG_SPL_BOOTSTAGE. It should be guarded by using CONFIG_IS_ENABLED
> for SPL build.
>
> arch/riscv/lib/bootm.c:46:9: warning: implicit declaration of
> function 'bootstage_r
Hi Chanho,
On Mon, Aug 28, 2023 at 06:49:37PM +0900, Chanho Park wrote:
> timer_get_boot_us function is required to record the boot stages as
> us-based timestamp.
>
> Signed-off-by: Chanho Park
> ---
> drivers/timer/riscv_timer.c | 21 +
> 1 file changed, 21 insertions(+)
>
Hi Chanho,
On Mon, Aug 28, 2023 at 06:49:38PM +0900, Chanho Park wrote:
> timer_get_boot_us function is required to record the boot stages as
> us-based timestamp.
>
> Signed-off-by: Chanho Park
> ---
> drivers/timer/riscv_aclint_timer.c | 22 ++
> 1 file changed, 22 inserti
On Tue, Aug 29, 2023 at 10:20:14AM +0900, Chanho Park wrote:
> spl_invoke_opensbi function is not returned to SPL. Thus, we need to
> set __noreturn function attribute.
>
> Signed-off-by: Chanho Park
> ---
> common/spl/spl_opensbi.c | 7 ---
> include/spl.h| 2 +-
> 2 files chang
On Mon, Sep 04, 2023 at 01:24:04PM +0200, Heinrich Schuchardt wrote:
> Use the DBCN SBI extension to implement a debug console.
> Make it the default for S-mode RISC-V.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> v2:
> check that we are in S-mode
> ---
> drivers/serial/Kconfig | 5
Hi Tom,
On Mon, Sep 04, 2023 at 03:06:34PM -0400, Tom Rini wrote:
> This function should now be a EVENT_SPY_SIMPLE call, update it.
>
> Signed-off-by: Tom Rini
> ---
> arch/riscv/cpu/cpu.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/cpu/cpu.c b/arch/
Hi Tom,
The following changes since commit 493fd3363f6da6a784514657d689c7cda0f390d5:
nokia_rx51: Remove platform (2023-09-04 21:14:32 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to dfe08374943c0e898fcf
Hi Heinrich,
On Tue, Sep 05, 2023 at 10:58:31AM +0200, Heinrich Schuchardt wrote:
> On 05.09.23 05:01, Leo Liang wrote:
> > Hi Tom,
> >
> > On Mon, Sep 04, 2023 at 03:06:34PM -0400, Tom Rini wrote:
> > > This function should now be a EVENT_SPY_SIMPLE call, update
On Thu, Sep 07, 2023 at 01:21:28PM +0200, Heinrich Schuchardt wrote:
> Multiple revisions of the StarFive VisionFive 2 board exist. They can be
> identified by reading their EEPROM.
>
> Linux uses two differently named device-tree files. To load the correct
> device-tree we need to set $fdtfile to
On Thu, Sep 07, 2023 at 03:53:36PM +0200, Heinrich Schuchardt wrote:
> Make NVMe and USB target boot devices on the StarFive VisionFive 2 board.
> The boot devices are sorted by decreasing device speed.
>
> CONFIG_PCI_INIT_R=y is set via [1]. 'start usb' is added to CONFIG_PREBOOT
> by the same pa
On Mon, Sep 05, 2022 at 04:40:49PM +0200, Heinrich Schuchardt wrote:
> System reset via the SRST extension in the SBI should be the default.
> The driver checks if the extension is available when probing.
> So there is no risk in enabling it.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> driver
Hi Tom,
The following changes since commit 427aa3c9b72b6672f714389a6f71b6cc2841d559:
Merge tag 'tpm-03092022' of
https://source.denx.de/u-boot/custodians/u-boot-tpm (2022-09-03 14:55:37 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
On Wed, Sep 21, 2022 at 02:34:54PM +0800, Andes wrote:
> From: Rick Chen
>
> In SMP all harts will register themself in available_hart
> during start up. Then main hart will send IPI to other harts
> according to this variables. But this mechanism may not
> guarantee that all other harts can jump
On Wed, Sep 21, 2022 at 02:34:55PM +0800, Andes wrote:
> From: Rick Chen
>
> Disable AVAILABLE_HARTS mechanism to make sure that all harts
> can boot to Kernel shell successfully.
>
> Signed-off-by: Rick Chen
> ---
> configs/ae350_rv32_spl_defconfig | 1 +
> configs/ae350_rv64_spl_defconfig |
On Mon, Sep 19, 2022 at 05:19:06PM +0530, Kautuk Consul wrote:
> We factor out the arch-independent parts of the ARM semihosting
> implementation as a common library so that it can be shared
> with RISC-V.
>
> Signed-off-by: Kautuk Consul
> ---
> arch/arm/Kconfig | 46 -
> arc
On Mon, Sep 19, 2022 at 05:19:07PM +0530, Kautuk Consul wrote:
> We add RISC-V semihosting based serial console for JTAG based early
> debugging.
>
> The RISC-V semihosting specification is available at:
> https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc
>
> S
On Mon, Sep 19, 2022 at 05:19:08PM +0530, Kautuk Consul wrote:
> To enable semihosting we also need to enable the following
> configs in defconfigs:
> CONFIG_SEMIHOSTING
> CONFIG_SPL_SEMIHOSTING
> CONFIG_SEMIHOSTING_SERIAL
> CONFIG_SERIAL_PROBE_ALL
> CONFIG_SPL_FS_EXT4
> CONFIG_SPL_FS_FAT
>
> Sign
Hi Tom,
The following changes since commit 435596d57f8beedf36b5dc858fe7ba9d6c03334b:
Merge tag 'u-boot-imx-20220922' of
https://gitlab.denx.de/u-boot/custodians/u-boot-imx (2022-09-22 10:29:29 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-ri
Hi Sean,
On Tue, Oct 04, 2022 at 02:23:33AM -0400, Sean Anderson wrote:
> On 10/1/22 03:39, Heinrich Schuchardt wrote:
> > The SBI command can print out the version number of the SBI implementation.
> > Choose the correct output format for RustSBI.
> >
> > Signed-off-by: Heinrich Schuchardt
> > -
Hi Kautuk,
On Fri, Sep 23, 2022 at 12:33:20PM +0530, Kautuk Consul wrote:
> To enable semihosting we also need to enable the following
> configs in defconfigs:
> CONFIG_SEMIHOSTING
> CONFIG_SPL_SEMIHOSTING
> CONFIG_SEMIHOSTING_SERIAL
> CONFIG_SERIAL_PROBE_ALL
> CONFIG_SPL_FS_EXT4
> CONFIG_SPL_FS_F
On Mon, Aug 08, 2022 at 01:24:25PM +0300, Nikita Shubin wrote:
> From: Nikita Shubin
>
> s/obensbi_info/opensbi_info/
>
> Signed-off-by: Nikita Shubin
> ---
> common/spl/spl_opensbi.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/common/spl/spl_opensbi.c b/common/sp
On Mon, Aug 08, 2022 at 01:28:52PM +0300, Nikita Shubin wrote:
> From: Nikita Shubin
>
> Convert hardcoded "opensbi_info.options" to config provided value, this
> allows changing options passed to OpenSBI.
>
> SPL_OPENSBI_SCRATCH_OPTIONS is defaulted to SBI_SCRATCH_NO_BOOT_PRINTS.
>
> Link:
>
Hi Tom,
The following changes since commit cdebee1fd9fa04cc4c972f826bae19b28c253eb0:
Merge branch '2022-08-10-assorted-updates' (2022-08-10 17:49:20 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-riscv.git
for you to fetch changes up to aa0ed
On Mon, May 30, 2022 at 11:05:54AM -0400, Tom Rini wrote:
> On Sat, May 28, 2022 at 09:02:09AM +0000, Leo Liang wrote:
> > On Fri, May 27, 2022 at 09:30:49AM -0400, Tom Rini wrote:
> > > On Fri, May 27, 2022 at 02:36:29AM +, Leo Liang wrote:
> > >
> >
On Fri, Aug 12, 2022 at 06:50:03PM +0100, Jessica Clarke wrote:
> This adds the onkey, RTC and watchdog children to the DA9063 PMIC node,
> fixes the compatible for qspi0's flash node to match the official DT
> schema (it being an is25wp256 is discoverable, hence jedec,spi-nor is
> the only compati
On Thu, Aug 11, 2022 at 10:23:02PM +, Leo Liang wrote:
> On Mon, May 30, 2022 at 11:05:54AM -0400, Tom Rini wrote:
> > On Sat, May 28, 2022 at 09:02:09AM +0000, Leo Liang wrote:
> > > On Fri, May 27, 2022 at 09:30:49AM -0400, Tom Rini wrote:
> > > > On Fri, Ma
Hi Icenowy,
On Thu, Aug 25, 2022 at 04:11:18PM +0800, Icenowy Zheng wrote:
> This commit sychornizes the header file for FU740 PRCI clocks with the
> one from Linux 5.19.
>
> The constant values are the same, but all constant names are changed
> (most are just prefixed with FU740_).
>
> Signed-of
On Sun, Aug 14, 2022 at 09:57:14PM +0200, Heinrich Schuchardt wrote:
> Format the KVM implementation number in a human readable form.
>
> With the patch output of the sbi command for Linux 5.19.1 looks like:
>
> => sbi
> SBI 0.3
> KVM 5.19.1
> Machine:
> Vendor ID 0
>
On Thu, Aug 25, 2022 at 04:11:19PM +0800, Icenowy Zheng wrote:
> These DT files are synchornized from Linux 5.19.
>
> Signed-off-by: Icenowy Zheng
> ---
> arch/riscv/dts/fu740-c000.dtsi | 67 +
> arch/riscv/dts/hifive-unmatched-a00.dts | 95 +++--
> 2
On Fri, Aug 19, 2022 at 09:24:53AM -0600, Simon Glass wrote:
> Hi Leo,
>
> On Fri, 19 Aug 2022 at 03:09, Leo Liang wrote:
> >
> > On Thu, Aug 11, 2022 at 10:23:02PM +, Leo Liang wrote:
> > > On Mon, May 30, 2022 at 11:05:54AM -0400, Tom Rini wrote:
> > &g
On Wed, Aug 31, 2022 at 12:38:01AM +0800, Icenowy Zheng wrote:
> 在 2022-08-30星期二的 03:26 +0000，Leo Liang写道：
> > Hi Icenowy,
> > On Thu, Aug 25, 2022 at 04:11:18PM +0800, Icenowy Zheng wrote:
> > > This commit sychornizes the header file for FU740 PRCI clocks with
> > &
Hi Bin,
On Thu, Apr 13, 2023 at 06:06:29PM +0800, Bin Meng wrote:
> On Mon, Apr 10, 2023 at 3:25 PM Rick Chen wrote:
> >
> > > From: Simon Glass
> > > Sent: Monday, April 03, 2023 4:28 AM
> > > To: U-Boot Mailing List
> > > Cc: Sean Anderson ; Bin Meng ;
> > > Rick Jian-Zhi Chen(陳建志) ; Leo Yu-
Hi YanHong, Torsten, Matthias,
On Thu, Apr 13, 2023 at 06:05:56PM +0800, yanhong wang wrote:
>
>
> On 2023/4/13 17:03, Torsten Duwe wrote:
> > On Thu, 13 Apr 2023 10:05:28 +0800
> > yanhong wang wrote:
> >
> >> the definition of DT refers to Linux and is consistent with the definition
> >> fr
Hi, Torsten, Matthias,
On Wed, Apr 19, 2023 at 02:34:03PM +0200, Matthias Brugger wrote:
>
>
> On 19/04/2023 13:28, Torsten Duwe wrote:
> > U-Boot already has a mechanism to fix up the DT before OS boot.
> > This avoids the excessive duplication of data and work proposed
> > by the explicit sepa
On Thu, Apr 13, 2023 at 02:20:05PM +0800, Bin Meng wrote:
> The codes currently skip the very first relocation entry, and have
> an inaccurate comment "skip first reserved entry" indicating that
> the first entry is reserved, but later it references the elements
> in the first relocation entry usin
On Thu, Apr 13, 2023 at 02:20:06PM +0800, Bin Meng wrote:
> board_init_r does not return for U-Boot SPL hence there is no need
> to update the link register when jumping to board_init_r.
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v2:
> - new patch: "riscv: Avoid updating the link regist
On Thu, Apr 13, 2023 at 02:20:07PM +0800, Bin Meng wrote:
> U-Boot SPL is not relocable. Drop these relocation sections.
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v2:
> - fix SPL build error
>
> arch/riscv/cpu/start.S| 2 ++
> arch/riscv/cpu/u-boot-spl.lds | 25 -
On Thu, Apr 13, 2023 at 02:20:08PM +0800, Bin Meng wrote:
> Some sections in the linker scripts are aligned to 4 bytes, which
> may cause misaligned exception on some platforms, e.g.: clearing
> the bss section on 64-bit hardware if __bss_start does not start
> from a naturally 8 bytes aligned addr
On Fri, Apr 07, 2023 at 01:44:59PM +0800, Bin Meng wrote:
> Since commit 409e4b547872 ("Makefile: Enforce DWARF4 output") the
> whole U-Boot build switched to enforce DWARF4 output, but RISC-V
> is still on its own setting. Let's switch to use U-Boot's setting.
>
> Signed-off-by: Bin Meng
> ---
>
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