On Tue, Oct 31, 2023 at 12:37:20AM -0500, Samuel Holland wrote: > Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a > vendor-specific way to invalidate a portion of the instruction cache. > Allow them to override invalidate_icache_range(). > > Signed-off-by: Samuel Holland <sam...@sholland.org> > --- > > arch/riscv/lib/cache.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Leo Yu-Chi Liang <ycli...@andestech.com>
