gt; Compile tested only.
>
Sorry, it's my bad.
I don't have the NDS32 toolchain, so I didn't run the compiling test
for NDS32 platforms.
> Cc: Kuo-Jung Su
> Cc: Macpaul Lin
> Signed-off-by: Gabor Juhos
> ---
> drivers/mmc/ftsdc010_mci.c |6 +-
> 1 fil
2013/6/11 Albert ARIBAUD :
> Hi Kuo-Jung,
>
> On Tue, 7 May 2013 14:25:12 +0800, Kuo-Jung Su
> wrote:
>
>> From: Kuo-Jung Su
>>
>> Signed-off-by: Kuo-Jung Su
>> CC: Albert Aribaud
>> ---
>> Changes for v4:
>>- Coding Style cleanup.
2013/6/11 Albert ARIBAUD :
> Hi Kuo-Jung,
>
> On Tue, 7 May 2013 14:25:13 +0800, Kuo-Jung Su
> wrote:
>
>> arch/arm/cpu/faraday/a360/Makefile| 49 +
>> arch/arm/cpu/faraday/a369/Makefile| 50 +
>> arch/arm/cpu/faraday/a369/cmd_fa606.c
2013/6/11 Albert ARIBAUD :
> Hi Kuo-Jung,
>
> On Tue, 7 May 2013 14:25:08 +0800, Kuo-Jung Su
> wrote:
>
>
>> diff --git a/arch/arm/include/asm/mach-types.h
>> b/arch/arm/include/asm/mach-types.h
>> index 440b041..a103922 100644
>> --- a/arch/arm/
2013/6/11 Albert ARIBAUD :
> Hi Kuo-Jung,
>
> On Tue, 7 May 2013 14:25:07 +0800, Kuo-Jung Su
> wrote:
>
>> diff --git a/arch/arm/include/asm/dma-mapping.h
>> b/arch/arm/include/asm/dma-mapping.h
>> index 5bbb0a0..5a13af5 100644
>> --- a/arch/arm/incl
2013/6/11 Albert ARIBAUD :
> Hi Kuo-Jung,
>
> On Tue, 11 Jun 2013 11:09:57 +0800, Kuo-Jung Su
> wrote:
>
>> 2013/6/11 Albert ARIBAUD :
>> > Hi Kuo-Jung,
>> >
>> > On Tue, 7 May 2013 14:25:07 +0800, Kuo-Jung Su
>> > wrote:
>> >
&
2013/6/13 Jagan Teki :
> Hi,
>
> Few comments, please get back your inputs.
>
> Use commit header as "spi: ftssp010_spi: "
>
Got it, thanks
>
> On 07-05-2013 12:04, Kuo-Jung Su wrote:
>>
>> From: Kuo-Jung Su
>>
>> The Faraday FTSSP010 is
From: Kuo-Jung Su
These patches introduce Faraday A36x SoC platform support.
Here are some public documents for your reference.
http://www.faraday-tech.com/html/documentation/index.html
There is also a A369 QEMU emulator available at my github account:
https://github.com/dantesu1218
From: Kuo-Jung Su
Faraday FTMAC110 10/100Mbps supports half-word data transfer for Linux.
However it has a weird DMA alignment issue:
(1) Tx DMA Buffer Address:
1 bytes aligned: Invalid
2 bytes aligned: O.K
4 bytes aligned: O.K
(2) Rx DMA Buffer Address:
1 bytes aligned
From: Kuo-Jung Su
Even though the MMU/D-cache is off, some DMA engines still
expect strict address alignment.
For example, the incoming Faraday FTMAC110 & FTGMAC100 ethernet
controllers expect the tx/rx descriptors should always be aligned
to 16-bytes boundary.
Signed-off-by: Kuo-Jung Su
From: Kuo-Jung Su
1. Dynamically allocate the tx/rx descriptors
through dma_alloc_coherent(), instead of
allocating at compile/link time.
2. Do not block on ftgmac100_send(), the packet
has been copied to a safe buffer. Although it's
a little bit slower, but the tx performan
From: Kuo-Jung Su
This updates the map_physmem()/unmap_physmem(), and use
them to implement dma_alloc_coherent() & dma_free_coherent().
It uses 1MB section for each mapping, and thus wastes lots of
address space, however this should still be good enough for
tiny systems (i.e. u-boot).
Si
From: Kuo-Jung Su
Faraday FTNANDC021 is a integrated NAND flash controller.
It use a build-in command table to abstract the underlying
NAND flash control logic.
For example:
Issuing a command 0x10 to FTNANDC021 would result in
a page write + a read status operation.
Signed-off-by: Kuo-Jung Su
From: Kuo-Jung Su
While the flash_detect_legacy() of drivers/mtd/cfi_flash.c
feed unmap_physmem() with MAP_NOCACHE as 2nd parameter,
the do_spi_flash_read_write() of common/cmd_sf.c
feed unmap_physmem() with the length of the mapped buffer
as 2nd parameter.
It's apparently a bug,
From: Kuo-Jung Su
This adds i/d-cache control, mmu setup & bootstrap code
for Faraday cores.
Signed-off-by: Kuo-Jung Su
CC: Albert Aribaud
---
Changes for v5:
- Initial commit which is separated from
"arm: add Faraday common utilities"
arch/arm/cpu/faraday/Ma
From: Kuo-Jung Su
Signed-off-by: Kuo-Jung Su
CC: Albert Aribaud
---
Changes for v5:
- Coding Style cleanup.
- Now the irq is always enabled inside irq_install_handler().
Changes for v4:
- Coding Style cleanup.
- Break up from [arm: add Faraday A36x SoC platform support]
Changes
From: Kuo-Jung Su
Faraday FTLCDC200 Color LCD controller performs translation of
pixel-coded data into the required formats and timings to
drive a variety of single/dual mono and color LCDs.
Depending on the LCD type and mode, the unpacked data can represent:
1. an actual true display gray
From: Kuo-Jung Su
At the time of writting, none of Faraday NAND & SPI controllers
supports XIP (eXecute In Place). So the Faraday A360/A369 SoC has
to implement a 1st level bootstrap code stored in the embedded ROM
inside the SoC.
After power-on, the ROM code (1st level bootstrap code) w
From: Kuo-Jung Su
Signed-off-by: Kuo-Jung Su
CC: Albert Aribaud
---
Changes for v5:
- Drop IRQ dependant implementation
- Use gd->arch.timer_rate_hz for timer clock source
- Use gd->arch.tbl for timestamp
Changes for v4:
- Coding Style cleanup.
- Break up from [arm: add F
From: Kuo-Jung Su
This updates ftsdc010_mci.c for latest Faraday clock APIs.
Signed-off-by: Kuo-Jung Su
CC: Albert Aribaud
CC: Andy Fleming
---
Changes for v5:
- Initial commit
drivers/mmc/ftsdc010_mci.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc
From: Kuo-Jung Su
Signed-off-by: Kuo-Jung Su
CC: Albert Aribaud
---
Changes for v5:
- Drop IRQ dependant implementation
- Use gd->arch.timer_rate_hz for timer clock source
- Use gd->arch.tbl for timestamp
Changes for v4:
- Coding Style cleanup.
- Break up from [arm: add F
2013/6/18 Andy Fleming :
>
>
>
> On Mon, Jun 17, 2013 at 7:07 AM, Kuo-Jung Su wrote:
>>
>> From: Kuo-Jung Su
>>
>> This updates ftsdc010_mci.c for latest Faraday clock APIs.
>>
>> Signed-off-by: Kuo-Jung Su
>> CC: Albert Aribaud
>>
2013/6/18 Scott Wood :
> On 06/17/2013 07:06:55 AM, Kuo-Jung Su wrote:
>>
>> diff --git a/README b/README
>> index ac1ec44..3dbb7cc 100644
>> --- a/README
>> +++ b/README
>> @@ -3930,6 +3930,12 @@ Low Level (hardware related) configuration options:
>&
2013/6/23 Albert ARIBAUD :
> Hi Kuo-Jung,
>
> On Mon, 17 Jun 2013 20:07:02 +0800, Kuo-Jung Su
> wrote:
>
>> From: Kuo-Jung Su
>>
>> At the time of writting, none of Faraday NAND & SPI controllers
>> supports XIP (eXecute In Place). So the Faraday A3
2013/6/23 Albert ARIBAUD :
> Hi Kuo-Jung,
>
> On Mon, 17 Jun 2013 20:06:52 +0800, Kuo-Jung Su
> wrote:
>
>> 3. No matter if MMU/D-cache is on or off, this patch
>>always depends on previous patch:
>>
>>arm: dma_alloc_coherent: malloc() -> memalign
From: Kuo-Jung Su
1. Update license statement
2. struct ftmac110_regs __iomem *regs -> struct ftmac110_regs *regs.
3. Reformat hardware tx/rx descriptor as an uniform one,
and replace uint32_t[2] with uint64_t for descriptor control.
Signed-off-by: Kuo-Jung Su
CC: Joe Hershberger
CC:
From: Kuo-Jung Su
Faraday FTLCDC200 Color LCD controller performs translation of
pixel-coded data into the required formats and timings to
drive a variety of single/dual mono and color LCDs.
Depending on the LCD type and mode, the unpacked data can represent:
1. an actual true display gray
From: Kuo-Jung Su
Faraday FTNANDC021 is a integrated NAND flash controller.
It use a build-in command table to abstract the underlying
NAND flash control logic.
For example:
Issuing a command 0x10 to FTNANDC021 would result in
a page write + a read status operation.
Signed-off-by: Kuo-Jung Su
From: Kuo-Jung Su
These patches introduce Faraday A36x SoC platform support.
Here are some public documents for your reference.
http://www.faraday-tech.com/html/documentation/index.html
There is also a A369 QEMU emulator available at my github account:
https://github.com/dantesu1218
From: Kuo-Jung Su
Even though the MMU/D-cache is off, some DMA engines still
expect strict address alignment.
For example, the incoming Faraday FTMAC110 & FTGMAC100 ethernet
controllers expect the tx/rx descriptors should always be aligned
to 16-bytes boundary.
Signed-off-by: Kuo-Jung Su
From: Kuo-Jung Su
While the flash_detect_legacy() of drivers/mtd/cfi_flash.c
feed unmap_physmem() with MAP_NOCACHE as 2nd parameter,
the do_spi_flash_read_write() of common/cmd_sf.c
feed unmap_physmem() with the length of the mapped buffer
as 2nd parameter.
It's apparently a bug,
From: Kuo-Jung Su
Signed-off-by: Kuo-Jung Su
CC: Albert Aribaud
---
Changes for v6:
- Nothing updates
Changes for v5:
- Coding Style cleanup.
- Now the irq is always enabled inside irq_install_handler().
Changes for v4:
- Coding Style cleanup.
- Break up from [arm: add Faraday
From: Kuo-Jung Su
This updates the map_physmem()/unmap_physmem(), and use
them to implement dma_alloc_coherent() & dma_free_coherent().
It uses 1MB section for each mapping, and thus wastes lots of
address space, however this should still be good enough for
tiny systems (i.e. u-boot).
Si
From: Kuo-Jung Su
Signed-off-by: Kuo-Jung Su
CC: Albert Aribaud
---
Changes for v6:
- Nothing updates
Changes for v5:
- Drop IRQ dependant implementation
- Use gd->arch.timer_rate_hz for timer clock source
- Use gd->arch.tbl for timestamp
Changes for v4:
- Coding Style c
From: Kuo-Jung Su
This adds i/d-cache control, mmu setup & bootstrap code
for Faraday cores.
Signed-off-by: Kuo-Jung Su
CC: Albert Aribaud
---
Changes for v6:
- Nothing updates
Changes for v5:
- Initial commit which is separated from
"arm: add Faraday common utilities&qu
From: Kuo-Jung Su
Signed-off-by: Kuo-Jung Su
CC: Albert Aribaud
---
Changes for v6:
- Nothing updates
Changes for v5:
- Drop IRQ dependant implementation
- Use gd->arch.timer_rate_hz for timer clock source
- Use gd->arch.tbl for timestamp
Changes for v4:
- Coding Style c
From: Kuo-Jung Su
This updates ftsdc010_mci.c for latest Faraday clock APIs.
Signed-off-by: Kuo-Jung Su
CC: Albert Aribaud
CC: Andy Fleming
---
Changes for v6:
- Nothing updates
Changes for v5:
- Initial commit
drivers/mmc/ftsdc010_mci.c |2 +-
1 file changed, 1 insertion(+), 1
From: Kuo-Jung Su
At the time of writting, none of Faraday NAND & SPI controllers
supports XIP (eXecute In Place), and the 1st stage bootstrap
stored in embedded ROM is not compatible to U-Boot design.
So this patch is added to support booting from Faraday Images.
Signed-off-by: Kuo-Jun
2013/7/9 Scott Wood :
> On 07/03/2013 10:40:35 PM, Kuo-Jung Su wrote:
>>
>> +#ifndef __ARMEB__
>> + put_unaligned_le32(readl(®s->dr), buf + off);
>> +#else
>> + put_unaligned_be32(readl(®s->dr), buf + off);
>> +#endif
>
&
2013/7/9 Joe Hershberger :
> Hi Kuo-Jung Su,
>
> On Wed, Jul 3, 2013 at 9:10 PM, Kuo-Jung Su wrote:
>> From: Kuo-Jung Su
>>
>> 1. Update license statement
>>
>> 2. struct ftmac110_regs __iomem *regs -> struct ftmac110_regs *regs.
>>
>> 3
2013/7/9 Scott Wood :
> On 07/08/2013 08:42:01 PM, Kuo-Jung Su wrote:
>>
>> 2013/7/9 Scott Wood :
>> > On 07/03/2013 10:40:35 PM, Kuo-Jung Su wrote:
>> >>
>> >> +#ifndef __ARMEB__
>> >> +
From: Kuo-Jung Su
1. Update license statement
2. struct ftmac110_regs __iomem *regs -> struct ftmac110_regs *regs.
3. Reformat hardware tx/rx descriptor as an uniform one,
and replace uint32_t[2] with uint64_t for descriptor control.
Changes for v2:
- Re-send these as separate patc
From: Kuo-Jung Su
Signed-off-by: Kuo-Jung Su
CC: Joe Hershberger
---
drivers/net/ftmac110.c | 17 ++---
drivers/net/ftmac110.h | 17 ++---
2 files changed, 28 insertions(+), 6 deletions(-)
diff --git a/drivers/net/ftmac110.c b/drivers/net/ftmac110.c
index 35f8633
From: Kuo-Jung Su
1. Reformat tx/rx descriptor as an uniform struct.
2. Replace uint32_t[2] with uint64_t for descriptor control.
Signed-off-by: Kuo-Jung Su
CC: Joe Hershberger
---
drivers/net/ftmac110.c | 86 ++--
drivers/net/ftmac110.h | 70
From: Kuo-Jung Su
Signed-off-by: Kuo-Jung Su
CC: Joe Hershberger
---
drivers/net/ftmac110.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/net/ftmac110.c b/drivers/net/ftmac110.c
index c7d45e1..1afd95a 100644
--- a/drivers/net/ftmac110.c
+++ b/drivers
2013/12/20 Jagan Teki :
> Hi Kuo-Jung Su,
>
> Please check this v7 and try to add the test log if you have.
>
Hi Jagan:
Thanks for the v7 patch, it works flawlessly.
Here is the test log on Faraday A369 EVB:
U-Boot 2014.01-rc2-g3444b6f (Dec 20 2013 - 10:58:40)
CPU: FA626TE
2013/12/19 Marek Vasut :
> On Thursday, December 19, 2013 at 08:07:00 AM, Kuo-Jung Su wrote:
>> 2013/12/19 Marek Vasut :
>> > On Thursday, December 19, 2013 at 01:50:55 AM, Kuo-Jung Su wrote:
>> >> 2013/12/18 Marek Vasut :
>> >> > On Wednesday, Decemb
From: Kuo-Jung Su
1. It's known that EP0 fifo empty indication is not reliable, an extra delay
is necessary to avoid data corruption while handling packets with size
greater than 64 bytes.
2. Since hardware revision 1.11.0, some fields of interrupt status registers
are now wr
From: Kuo-Jung Su
The fifo size of ep0 is 64 bytes, and if the packet size grater than
64 bytes, the driver would have to fill up the fifo multiple times,
and before filling up the fifo, the driver should make sure the fifo
is empty by checking fifo empty indication.
However there is a hardware
From: Kuo-Jung Su
Since hardware revision 1.11.0, the following interrupt status
registers are now W1C (i.e., write 1 clear):
1. Interrupt Source Group 0 Register (0x144) (EP0 Abort: BIT5)
2. Interrupt Source Group 2 Register (0x14C) (All bits)
And before revision 1.11.0, these registers are
2013/12/20 Marek Vasut :
> On Friday, December 20, 2013 at 05:32:58 AM, Kuo-Jung Su wrote:
>> From: Kuo-Jung Su
>>
>> 1. It's known that EP0 fifo empty indication is not reliable, an extra
>> delay is necessary to avoid data corruption while handling packets wi
2013/12/23 Marek Vasut :
> On Monday, December 23, 2013 at 01:50:36 AM, Kuo-Jung Su wrote:
>> 2013/12/20 Marek Vasut :
>> > On Friday, December 20, 2013 at 05:32:58 AM, Kuo-Jung Su wrote:
>> >> From: Kuo-Jung Su
>> >>
>> >> 1. It's kno
From: Kuo-Jung Su
The DMA API is revised as follow:
1. Create an un-cached shadow memory for malloc(),
the un-cached shadow memory is controlled by
CONFIG_CONSISTENT_DMA_START and CONFIG_CONSISTENT_DMA_END,
and initialized inside arch_early_init_r().
2. The virtual address returned by
From: Kuo-Jung Su
Faraday FTTMR010 is a simple APB device which supports
generic timer functions.
Signed-off-by: Kuo-Jung Su
CC: Albert Aribaud
---
Changes for v8:
- Nothing updates
Changes for v7:
- Update license to use SPDX identifiers.
Changes for v6:
- Nothing
From: Kuo-Jung Su
This adds board support for the Faraday A369 SoC platform.
Working functions:
- MMU/D-cache
- SD Host controller
- USB EHCI controller
- Network
- I2C EEPROM
- UART
Signed-off-by: Kuo-Jung Su
CC: Albert Aribaud
---
Changes for v8:
- Make A369 a standalong changeset
From: Kuo-Jung Su
This adds board support for the Faraday A360 SoC platform.
Working functions:
- MMU/D-cache
- SD Host controller
- USB EHCI controller
- Network
- I2C EEPROM
- UART
Signed-off-by: Kuo-Jung Su
CC: Albert Aribaud
---
Changes for v8:
- Make A360 a standalong changeset
From: Kuo-Jung Su
This fixes the following compiler warnings:
fti2c010.c: In function 'fti2c010_read':
fti2c010.c:204:8: warning: 'paddr' may be used uninitialized in this function
[-Wuninitialized]
fti2c010.c: In function 'fti2c010_write':
fti2c010.c:266:8
From: Kuo-Jung Su
These patches introduce Faraday A36x SoC platform support.
Here are some public documents for your reference.
http://www.faraday-tech.com/html/documentation/index.html
There is also a A369 QEMU emulator available at my github account:
https://github.com/dantesu1218
From: Kuo-Jung Su
Add 'cpu_id' and 'has_mmu' for Faraday SoC platforms
Signed-off-by: Kuo-Jung Su
CC: Albert Aribaud
---
Changes for v8:
- Initial commit
arch/arm/include/asm/global_data.h |4
arch/arm/lib/cache-cp15.c |5 +
2 files c
From: Kuo-Jung Su
By making mmu_enabled() a global function, we could reuse the code
in other mmu/d-cache related routines.
Signed-off-by: Kuo-Jung Su
CC: Albert Aribaud
---
Changes for v8:
- Initial commit
arch/arm/lib/cache-cp15.c |2 +-
include/common.h |1 +
2
From: Kuo-Jung Su
Here is the list of verified cores:
1. FA606TE (ARMv5TE, no mmu)
2. FA626TE (ARMv5TE)
Signed-off-by: Kuo-Jung Su
CC: Albert Aribaud
---
Changes for v8:
- add arm_init_before_mmu() & mmu_page_table_flush()
Changes for v7:
- Update license to use
From: Kuo-Jung Su
Faraday FTPWMTMR010 is a simple APB device which supports
both timer and pwm functions.
Signed-off-by: Kuo-Jung Su
CC: Albert Aribaud
---
Changes for v8:
- Nothing updates
Changes for v7:
- Update license to use SPDX identifiers.
Changes for v6
mc.o
> obj-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o
> obj-$(CONFIG_MMC_SPI) += mmc_spi.o
> diff --git a/drivers/mmc/ftsdc021_sdhci.c b/drivers/mmc/ftsdc021_sdhci.c
> deleted file mode 100644
> index 1f6cdba..000
> --- a/drivers/mmc/ftsdc021_sdhci.c
> +++ /dev/null
retract this patch.
>
>
Thanks for your understanding
--
Best wishes,
Kuo-Jung Su
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
From: Kuo-Jung Su
These patches introduce Faraday A369 & Virtual SoC platform support.
Here are some public documents for your reference.
http://www.faraday-tech.com/html/Product/SoCPlatform/SoCreativeIII.htm
http://www.faraday-tech.com/html/documentation/index.html
There is also a
From: Kuo-Jung Su
Here is the list of verified cores:
1. FA606TE (ARMv5TE, no mmu)
2. FA626TE (ARMv5TE)
Signed-off-by: Kuo-Jung Su
CC: Albert Aribaud
---
Changes for v9:
- Build 'arch_preboot_os()' only when CONFIG_CMD_BOOTM is defined.
- Add do_go_exec() to ov
From: Kuo-Jung Su
1. arch/arm/include/asm/faraday.h:
Faraday SoC header file
2. include/configs/faraday-common.h:
Faraday SoC common/default configurations
Signed-off-by: Kuo-Jung Su
CC: Albert Aribaud
---
Changes for v9:
- Separated as a standalone changeset by first time
From: Kuo-Jung Su
Faraday FTPWMTMR010 is a simple APB device which supports
both timer and pwm functions.
Signed-off-by: Kuo-Jung Su
CC: Albert Aribaud
---
Changes for v9:
- Nothing updates
Changes for v8:
- Nothing updates
Changes for v7:
- Update license to use
From: Kuo-Jung Su
Faraday FTTMR010 is a simple APB device which supports
generic timer functions.
Signed-off-by: Kuo-Jung Su
CC: Albert Aribaud
---
Changes for v9:
- Nothing updates
Changes for v8:
- Nothing updates
Changes for v7:
- Update license to use SPDX
From: Kuo-Jung Su
Add a macro constant for fail-safe timing value.
Signed-off-by: Kuo-Jung Su
CC: Albert Aribaud
---
Changes for v9:
- Separated as a standalone changeset by first time.
include/faraday/ftsmc020.h |1 +
1 file changed, 1 insertion(+)
diff --git a/include/faraday
From: Kuo-Jung Su
Faraday Virtual Machine (FVM) is a QEMU based emulator
which is designed for early stage software development
(e.g., IPL, SPL).
Please check the link bellow for details:
https://github.com/dantesu1218/qemu/blob/qemu-1.5.1/hw/arm/faraday_fvm.c
Signed-off-by: Kuo-Jung Su
CC
From: Kuo-Jung Su
The A369 is an ARM CPU-based SoC with rich SoC features and
convenient FPGA link for building fast system prototyping
and volume production.
More information about this hardware can be found at:
http://www.faraday-tech.com/html/Product/SoCPlatform/SoCreativeIII.htm
Signed-off
From: Kuo-Jung Su
These patches introduce Faraday A369 & Virtual SoC platform support.
Here are some public documents for your reference.
http://www.faraday-tech.com/html/Product/SoCPlatform/SoCreativeIII.htm
http://www.faraday-tech.com/html/documentation/index.html
There is also a
From: Kuo-Jung Su
Faraday FTTMR010 is a simple APB device which supports
generic timer functions.
Signed-off-by: Kuo-Jung Su
CC: Albert Aribaud
---
Changes for v8, v9, v10:
- Nothing updates
Changes for v7:
- Update license to use SPDX identifiers.
Changes for v6
From: Kuo-Jung Su
Here is the list of verified cores:
1. FA606TE (ARMv5TE, no mmu)
2. FA626TE (ARMv5TE)
Signed-off-by: Kuo-Jung Su
CC: Albert Aribaud
---
Changes for v10:
- Merge [arm: add Faraday SoC helper files]
Changes for v9:
- Build 'arch_preboot_os()'
From: Kuo-Jung Su
Faraday FTPWMTMR010 is a simple APB device which supports
both timer and pwm functions.
Signed-off-by: Kuo-Jung Su
CC: Albert Aribaud
---
Changes for v8, v9, v10:
- Nothing updates
Changes for v7:
- Update license to use SPDX identifiers.
Changes for v6
From: Kuo-Jung Su
For the Faraday FTSDC021 (SDHCI) controller driver source is
sent out before the patches for Faraday Virtual Machine (FVM)
which actually uses this chip.
The header file (ftsdc021.h) has been accidentally removed
by commit: 3b98b57fa - include: delete unused header files
This
From: Kuo-Jung Su
Faraday Virtual Machine (FVM) is a QEMU based emulator
which is designed for early stage software development
(i.e., IPL, SPL development).
Please check the link bellow for details:
https://github.com/dantesu1218/qemu/blob/qemu-1.5.1/hw/arm/faraday_fvm.c
Signed-off-by: Kuo
From: Kuo-Jung Su
The A369 is an ARM CPU-based SoC with rich SoC features and
convenient FPGA link for building fast system prototyping
and mass production.
More information about this hardware can be found at:
http://www.faraday-tech.com/html/Product/SoCPlatform/SoCreativeIII.htm
Signed-off
Got it, thanks, and sorry for the mess I made.
I'll send out the unsplit patch after the Faraday platform patches got commited.
2014-03-04 10:17 GMT+08:00 Scott Wood :
> On Thu, Nov 28, 2013 at 10:48:51AM +0800, Kuo-Jung Su wrote:
>> From: Kuo-Jung Su
>>
>> Faraday F
From: Kuo-Jung Su
Here is the list of verified cores:
1. FA606TE (ARMv5TE, no mmu)
2. FA626TE (ARMv5TE)
Signed-off-by: Kuo-Jung Su
CC: Albert Aribaud
---
Changes for v11:
- Nothing updates
Changes for v10:
- Merge [arm: add Faraday SoC helper files]
Changes for v9
From: Kuo-Jung Su
Faraday FTTMR010 is a simple APB device which supports
generic timer functions.
Signed-off-by: Kuo-Jung Su
CC: Albert Aribaud
---
Changes for v11:
- Directly specify the timer object in
'arch/arm/cpu/faraday//Makefile'
instead of using CONFIG_F
From: Kuo-Jung Su
The A369 is an ARM CPU-based SoC with rich SoC features and
convenient FPGA link for building fast system prototyping
and mass production.
More information about this hardware can be found at:
http://www.faraday-tech.com/html/Product/SoCPlatform/SoCreativeIII.htm
Signed-off
From: Kuo-Jung Su
Faraday Virtual Machine (FVM) is a QEMU based emulator
which is designed for early stage software development
(i.e., IPL, SPL development).
Please check the link bellow for details:
https://github.com/dantesu1218/qemu/blob/qemu-1.5.1/hw/arm/faraday_fvm.c
Signed-off-by: Kuo
From: Kuo-Jung Su
These patches introduce Faraday A369 & Virtual SoC platform support.
Here are some public documents for your reference.
http://www.faraday-tech.com/html/Product/SoCPlatform/SoCreativeIII.htm
http://www.faraday-tech.com/html/documentation/index.html
There is also a
From: Kuo-Jung Su
Faraday FTPWMTMR010 is a simple APB device which supports
both timer and pwm functions.
Signed-off-by: Kuo-Jung Su
CC: Albert Aribaud
---
Changes for v11:
- Directly specify the timer object in
'arch/arm/cpu/faraday//Makefile'
instea
From: Kuo-Jung Su
For the Faraday FTSDC021 (SDHCI) controller driver source is
sent out before the patches for Faraday Virtual Machine (FVM)
which actually uses this chip.
The header file (ftsdc021.h) has been accidentally removed
by commit: 3b98b57fa - include: delete unused header files
This
2014-03-25 20:41 GMT+08:00 Albert ARIBAUD :
> Hi Kuo-Jung,
>
> On Thu, 20 Feb 2014 11:40:32 +0800, Kuo-Jung Su
> wrote:
>
>> From: Kuo-Jung Su
>>
>> These patches introduce Faraday A369 & Virtual SoC platform support.
>
> Except for patches 4/6 and 6/6
2014-03-26 14:47 GMT+08:00 Wolfgang Denk :
> Dear Kuo-Jung Su,
>
> In message <1395813799-3672-2-git-send-email-dant...@gmail.com> you wrote:
>> From: Kuo-Jung Su
>>
>> Here is the list of verified cores:
>>
>> 1. FA606TE (ARMv5TE, no mmu)
>>
2014-03-26 14:52 GMT+08:00 Wolfgang Denk :
> Dear Kuo-Jung Su,
>
> In message <1395813799-3672-7-git-send-email-dant...@gmail.com> you wrote:
>> From: Kuo-Jung Su
>>
>> Faraday Virtual Machine (FVM) is a QEMU based emulator
>> which is designed for early s
From: Kuo-Jung Su
Faraday FTMAC110 10/100Mbps supports half-word data transfer for Linux.
However it has a weird DMA alignment issue:
(1) Tx DMA Buffer Address:
1 bytes aligned: Invalid
2 bytes aligned: O.K
4 bytes aligned: O.K
(2) Rx DMA Buffer Address:
1 bytes aligned
From: Kuo-Jung Su
This patch add supports to both Faraday FUSBH200 and FOTG210,
these controllers slightly differ from standard EHCI specification.
Signed-off-by: Kuo-Jung Su
---
common/usb_hub.c|5 ++
drivers/usb/host/Makefile |1 +
drivers/usb/host/ehci
From: Kuo-Jung Su
Faraday FTI2C010 is a multi-function I2C controller
which supports both master and slave mode.
This patch simplily implements the master mode only.
Signed-off-by: Kuo-Jung Su
---
drivers/i2c/Makefile |1 +
drivers/i2c/fti2c010.c | 360
From: Kuo-Jung Su
Faraday FTSDC010 is a MMC/SD host controller.
There is already a driver in u-boot, which is
modified from eSHDC and contributed by Andes Tech.
However it works extreamly slow in Faraday A36x SoC
Platforms, so I turn to implement this new version
of driver with 10 times faster
From: Kuo-Jung Su
Faraday FTSPI020 is dedicated SPI bus designed for
SPI Flash chips. It supports Fast-Read-Dual,
Fast-Read-Dual-IO, Fast-Read-Quad and Fast-Read-Quad-IO.
Signed-off-by: Kuo-Jung Su
---
drivers/mtd/spi/Makefile |4 +
drivers/mtd/spi/ftspi020.c | 589
From: Kuo-Jung Su
This patch would enable MMU for Faraday ARMv5TE cores.
Here is the abstract of the MMU design.
Assume SDRAM memory region starts at 0x1000, and its size = 0x80.
0x +---+
| |
| UN-CACHED
From: Kuo-Jung Su
The Faraday FTSSP010 is a multi-function controller
which supports I2S/SPI/SSP/AC97/SPDIF.
This patch simpily implements the SPI mode only.
BTW the DMA and CS/Clock control logic has been
altered since revision 1.19.0. So this patch
would 1st detects the revision id of the
From: Kuo-Jung Su
This patch would try to use Faraday FOTG210 to implement
a USB RNDIS Ethernet.
Signed-off-by: Kuo-Jung Su
---
drivers/usb/gadget/Makefile |1 +
drivers/usb/gadget/fotg210.c | 926 +
drivers/usb/gadget/fotg210.h | 99
From: Kuo-Jung Su
These patches introduce Faraday A36x SoC platform support.
Here are some public documents for your reference.
http://www.faraday-tech.com/html/documentation/index.html
There is also a A369 QEMU emulator available at my github account:
https://github.com/dantesu1218
From: Kuo-Jung Su
Faraday FTNANDC021 is a integrated NAND flash controller.
It use a build-in command table to abstract the underlying
NAND flash control logic.
For example:
Issuing a command 0x10 to FTNANDC021 would result in
a page write + a read status operation.
Signed-off-by: Kuo-Jung Su
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