From: Kuo-Jung Su <dant...@faraday-tech.com>
Even though the MMU/D-cache is off, some DMA engines still
expect strict address alignment.
For example, the incoming Faraday FTMAC110 & FTGMAC100 ethernet
controllers expect the tx/rx descriptors should always be aligned
to 16-bytes boundary.
Signed-off-by: Kuo-Jung Su <dant...@faraday-tech.com>
CC: Albert ARIBAUD <albert.u.b...@aribaud.net>
---
Changes for v6:
- Nothing updates
Changes for v5:
- Initial commit, which is separated from
"arm: add MMU/D-Cache support for Faraday cores"
arch/arm/include/asm/dma-mapping.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/dma-mapping.h
b/arch/arm/include/asm/dma-mapping.h
index 5bbb0a0..a11178f 100644
--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -32,7 +32,7 @@ enum dma_data_direction {
static void *dma_alloc_coherent(size_t len, unsigned long *handle)
{
- *handle = (unsigned long)malloc(len);
+ *handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len);
return (void *)*handle;
}
--
1.7.9.5
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