Hi Maxime,
Dne ponedeljek, 24. april 2017 ob 09:19:40 CEST je Maxime Ripard napisal(a):
> Hi Jernej,
>
> On Fri, Apr 21, 2017 at 07:24:12PM +0200, Jernej Škrabec wrote:
> > Dne petek, 21. april 2017 ob 09:04:13 CEST je Maxime Ripard napisal(a):
> > > Hi Jernej,
> >
Hi Maxime,
Dne torek, 25. april 2017 ob 10:57:05 CEST je Maxime Ripard napisal(a):
> On Mon, Apr 24, 2017 at 11:54:22PM +0200, Jernej Škrabec wrote:
> > Hi Maxime,
> >
> > Dne ponedeljek, 24. april 2017 ob 09:19:40 CEST je Maxime Ripard
napisal(a):
> > > Hi Jerne
Hi Maxime,
Dne ponedeljek, 24. april 2017 ob 09:19:40 CEST je Maxime Ripard napisal(a):
> Hi Jernej,
>
> On Fri, Apr 21, 2017 at 07:24:12PM +0200, Jernej Škrabec wrote:
> > Dne petek, 21. april 2017 ob 09:04:13 CEST je Maxime Ripard napisal(a):
> > > Hi Jernej,
> >
Hi Philipp,
Dne petek, 28. april 2017 ob 17:53:10 CEST je Philipp Tomsich napisal(a):
> This commit enables RK3399 support for HDMI through the following
> changes:
> - adds a driverdata structure to mirror some subtle version
> differences between the RK3399 VOPs and those in the RK3288
> (e.
Hi Philipp,
Dne petek, 28. april 2017 ob 17:53:11 CEST je Philipp Tomsich napisal(a):
> This commit enables the RK3399 HDMI TX, which is very similar to the
> one found on the RK3288. The differences between the two SoCs (mainly
> the input VOP selection) is abstracted away through the driverdata.
Hi Maxime,
Dne ponedeljek, 22. maj 2017 ob 09:35:56 CEST je Maxime Ripard napisal(a):
> On Fri, May 19, 2017 at 05:41:17PM +0200, Jernej Skrabec wrote:
> > This commit adds support for TV (composite) output.
> >
> > Because there is no mechanism to select TV standard, PAL is
> > hardcoded.
>
> I
Hi,
Dne sreda, 24. maj 2017 ob 03:00:16 CEST je Tom Rini napisal(a):
> On Tue, May 23, 2017 at 11:05:30PM +0200, Jernej Skrabec wrote:
> > This commit fixes the warning produced by gcc 7.1.
> >
> > Signed-off-by: Jernej Skrabec
>
> Reviewed-by: Tom Rini
>
> And I'm curious, where is your gcc-
Hi,
Dne torek, 23. maj 2017 ob 22:22:14 CEST je Maxime Ripard napisal(a):
> Hi Jernej,
>
> On Mon, May 22, 2017 at 08:49:57PM +0200, Jernej Škrabec wrote:
> > Dne ponedeljek, 22. maj 2017 ob 09:35:56 CEST je Maxime Ripard napisal(a):
> > > On Fri, May 19, 2017 at 05:41:17
Hi Maxime,
Dne petek, 12. maj 2017 ob 17:47:17 CEST je Maxime Ripard napisal(a):
> Hi Jernej,
>
> On Wed, May 10, 2017 at 06:46:29PM +0200, Jernej Skrabec wrote:
> > This patch adds support for TV encoder clocks which will be used later.
> >
> > Signed-off-by: Jernej Skrabec
> > ---
> >
> > a
Hi,
Dne ponedeljek, 15. maj 2017 ob 08:11:55 CEST je Maxime Ripard napisal(a):
> On Sun, May 14, 2017 at 09:03:19PM -0600, Simon Glass wrote:
> > Hi,
> >
> > On 12 May 2017 at 10:06, Maxime Ripard
wrote:
> > > Hi Jernej,
> > >
> > > The patch content looks fine, but there's a few things that w
Hi,
Dne ponedeljek, 15. maj 2017 ob 08:31:22 CEST je Maxime Ripard napisal(a):
> On Sat, May 13, 2017 at 11:14:00PM +0800, Chen-Yu Tsai wrote:
> > >>> +static int sunxi_tve_get_plug_in_status(void)
> > >>> +{
> > >>> + struct sunxi_tve_reg * const tve =
> > >>> + (struct sunxi_
Hi,
On Tue, Dec 13, 2016 at 16:18:58 CET, Maxime Ripard wrote:
> Hi,
>
> First off, thanks a lot for working on this.
>
> On Tue, Dec 13, 2016 at 01:36:28AM +0100, Jernej Skrabec wrote:
> > This is needed for HDMI support, which will be added later.
> >
> > Signed-off-by: Jernej Skrabec
> > --
Hi,
On Tue, Dec 13, 2016 at 16:40:55 CET, Maxime Ripard wrote:
> Hi,
>
> On Tue, Dec 13, 2016 at 01:36:29AM +0100, Jernej Skrabec wrote:
> > This patch adds support for hdmi output. It is designed in the same
> > way as video driver for older Allwinner SoCs.
> >
> > First it checks if monitor is
Hi,
On Wed, Dec 14, 2016 at 11:28:43 CET, Maxime Ripard wrote:
> Hi,
>
> On Tue, Dec 13, 2016 at 09:13:11PM +0100, Jernej Škrabec wrote:
> > Hi,
> >
> > On Tue, Dec 13, 2016 at 16:40:55 CET, Maxime Ripard wrote:
> > > Hi,
> > >
> > > On
Hi,
Dne torek, 19. september 2017 ob 21:00:30 CEST je Vasily Khoruzhick
napisal(a):
> On Tue, Sep 19, 2017 at 1:33 AM, Maxime Ripard
>
> wrote:
> > On Mon, Sep 18, 2017 at 10:04:21PM -0700, Vasily Khoruzhick wrote:
> >> Extend DE2 driver with LCD support
> >
> > (All) your commit messages coul
Hi,
Dne sreda, 02. maj 2018 ob 16:47:07 CEST je Vasily Khoruzhick napisal(a):
> On Wed, May 2, 2018 at 4:01 AM, Anatolij Gustschin wrote:
> > Hi,
> >
> > On Sat, 28 Apr 2018 14:57:27 -0700
> >
> > Vasily Khoruzhick anars...@gmail.com wrote:
> >> Previous attempt to fix HSYNC and VSYNC polarity
Hi!
Dne ponedeljek, 14. maj 2018 ob 22:49:52 CEST je Vasily Khoruzhick napisal(a):
> HSYNC is bit 8, and VSYNC is bit 9.
>
> Signed-off-by: Vasily Khoruzhick
Reviewed-by: Jernej Skrabec
Best regards,
Jernej
> ---
> drivers/video/sunxi/sunxi_dw_hdmi.c | 4 ++--
> 1 file changed, 2 insertions
Hi,
Dne ponedeljek, 14. maj 2018 ob 22:49:53 CEST je Vasily Khoruzhick napisal(a):
> Currently dw_hdmi configures HSYNC polarity using VSYNC setting from
> EDID and vice versa. Fix it, since it breaks displays where HSYNC
> and VSYNC polarity differs
>
> Signed-off-by: Vasily Khoruzhick
Reviewe
Hi,
Dne petek, 19. januar 2018 ob 19:38:52 CET je Nuno Gonçalves napisal(a):
> Sorry, there is only 1 patch in this series.
>
> I would like comments regarding removing DM_I2C for MACH_SUNXI_H3_H5,
> as I didn't found a reason for it to be defined.
there is good reason to be there. When H3/H5 bo
gpio [ + ] gpio_sunxi `-- pinctrl@01f02c00
> gpio [ + ] gpio_sunxi `-- PL
>
> Is there any typical cause for this driver not to be probed?
>
> Thanks
>
> On Mon, Jan 22, 2018 at 10:18 AM, Nuno Gonçalves wrote:
> > On Fri, Jan 19,
Dne torek, 18. junij 2019 ob 19:13:16 CEST je Clément Péron napisal(a):
> Hi,
>
> On Thu, 16 May 2019 at 03:27, Andre Przywara wrote:
> > The first USB controller on the H6 SoC shares a PHY with the OTG
> > controller. Reportedly to avoid problems with the VBUS regulator under
> > Linux, we don't
Hi!
Dne sreda, 19. junij 2019 ob 03:11:06 CEST je Andre Przywara napisal(a):
> At the moment the H6 DRAM driver only supports LPDDR3 DRAM.
>
> Extend the driver to cover DDR3 DRAM as well.
>
> The changes are partly motivated by looking at the ZynqMP register
> documentation, partly by looking a
Hi!
Dne sreda, 19. junij 2019 ob 03:11:07 CEST je Andre Przywara napisal(a):
> Add a routine to program the timing parameters for DDR3-1333 DRAM chips
> connected to the H6 DRAM controller.
>
> The values were gathered from doing back-calculations from a register
> dump, trying to match them up w
Dne četrtek, 28. marec 2019 ob 08:52:48 CET je Jagan Teki napisal(a):
> On Sun, Mar 24, 2019 at 11:56 PM Jernej Skrabec
wrote:
> > Currently, HDMI driver doesn't consider minimum and maximum allowed rate
> > of pll3 (video PLL). It works most of the time, but not always.
> >
> > Consider monitor
Hi!
Dne nedelja, 26. maj 2019 ob 08:28:41 CEST je codekip...@gmail.com napisal(a):
> From: Marcus Cooper
>
> The Beelink X2 is an STB based on the Allwinner H3 SoC with a uSD slot,
> 2 USB ports( 1 * USB-2 Host, 1 USB OTG), a 10/100M ethernet port using the
> SoC's integrated PHY, Wifi via an sd
Hi!
Dne nedelja, 26. maj 2019 ob 08:28:41 CEST je codekip...@gmail.com napisal(a):
> From: Marcus Cooper
>
> The Beelink X2 is an STB based on the Allwinner H3 SoC with a uSD slot,
> 2 USB ports( 1 * USB-2 Host, 1 USB OTG), a 10/100M ethernet port using the
> SoC's integrated PHY, Wifi via an sd
Dne torek, 02. julij 2019 ob 11:51:41 CEST je Andre Przywara napisal(a):
> An updated version, with minor changes.
> I realised that my comments about JEDEC values were still based on the
> DDR3-1600 speed bin, so I updated those to match the DDR3-1333 values.
> I also used the actual JEDEC recomme
+CC: Thomas
Dne četrtek, 18. julij 2019 ob 00:16:17 CEST je Jernej Skrabec napisal(a):
> Half DQ configuration seems to be very rare for H6 based boards/STBs,
> but exists nevertheless. Currently the only known product which needs
> this support is Tanix TX6 mini.
>
> This commit adds support for
Hi!
Dne sreda, 21. avgust 2019 ob 02:31:04 CEST je André Przywara napisal(a):
> On 17/07/2019 23:16, Jernej Skrabec wrote:
> > Half DQ configuration seems to be very rare for H6 based boards/STBs,
> > but exists nevertheless. Currently the only known product which needs
> > this support is Tanix T
Dne sreda, 21. avgust 2019 ob 13:07:13 CEST je Andre Przywara napisal(a):
> On Wed, 21 Aug 2019 08:01:31 +0200
> Jernej Škrabec wrote:
>
> Hi,
>
> > Dne sreda, 21. avgust 2019 ob 02:31:04 CEST je André Przywara napisal(a):
> > > On 17/07/2019 23:16, Jernej
Hi everyone!
Commit cb9faa6f98ae ("tools: Use a single target-independent config to enable
OpenSSL") recently introduced option to disable usage of OpenSSL via
CONFIG_TOOLS_LIBCRYPTO. However, just a bit later, another commit b4f3cc2c42d9
("tools: kwbimage: Do not hide usage of secure header un
Hi!
Dne četrtek, 07. oktober 2021 ob 21:41:00 CEST je Tom Rini napisal(a):
> On Wed, Oct 06, 2021 at 11:27:43PM +0200, Jernej Škrabec wrote:
>
> > Hi everyone!
> >
> > Commit cb9faa6f98ae ("tools: Use a single target-independent config to
enable
> > Open
Hi Alex!
Dne četrtek, 07. oktober 2021 ob 00:05:24 CEST je Alex G. napisal(a):
> Hi Jernej,
>
> On 10/6/21 4:27 PM, Jernej Škrabec wrote:
> > Hi everyone!
> >
> > Commit cb9faa6f98ae ("tools: Use a single target-independent config to
enable
> > OpenSSL&q
Hi Andre!
Dne ponedeljek, 13. december 2021 ob 02:03:22 CET je Andre Przywara
napisal(a):
> Add some long overdue instructions for building and installing U-Boot on
> Allwinner SoC based boards.
> This describes the building process, including TF-A and crust, plus
> installation to SD card, eMMC
Dne torek, 14. december 2021 ob 02:07:58 CET je Andre Przywara napisal(a):
> On Mon, 13 Dec 2021 18:20:37 +0100
> Jernej Škrabec wrote:
>
> Hi Jernej,
>
> thanks for having a look!
>
> > Dne ponedeljek, 13. december 2021 ob 02:03:22 CET je Andre Przywara
> >
Dne sreda, 16. marec 2022 ob 01:54:42 CET je Andre Przywara napisal(a):
> Commit 5bc4cd05d7d4 ("sunxi: move non-essential code out of s_init()")
> moved the call to eth_init_board() from s_init() into board_init_f().
> This means it's now only called from the SPL, which makes sense for
> most of th
Dne sreda, 07. junij 2023 ob 02:07:41 CEST je Andre Przywara napisal(a):
> The usage of the C keyword "inline" seems to be a common
> misunderstanding: it's a *hint* only, and modern compilers will inline
> (or not) functions based on their own judgement and provided compiler
> options.
> So while
Dne sreda, 07. junij 2023 ob 02:07:42 CEST je Andre Przywara napisal(a):
> There are quite some functions in the Allwinner H616 DRAM "driver", some
> of them actually change the parameters in the structure passed to them,
> but many are actually not.
> To increase the optimisation potential for the
Dne sreda, 07. junij 2023 ob 02:07:43 CEST je Andre Przywara napisal(a):
> Currently there is one DRAM parameter struct for the Allwinner H616 DRAM
> "driver". It contains many fields that are compile time constants
> (set by Kconfig variables), though there are also some fields that are
> probed a
Dne sreda, 07. junij 2023 ob 02:07:44 CEST je Andre Przywara napisal(a):
> From: iuncuim
>
> Allwinner H616 SoC supports several types of DRAM memory. To further
> integrate other types of memory, we need to add this delimitation.
> ---
> arch/arm/mach-sunxi/Kconfig | 10 +-
Dne sreda, 07. junij 2023 ob 02:07:45 CEST je Andre Przywara napisal(a):
> From: iuncuim
>
> The H616 SoC has support for several types of DRAM: DDR3, LPDDR3,
> DDR4 and LPDDR4.
> At the moment, the driver only supports DDR3 memory.
> Let's extend the driver to support the LPDDR3 memory. All "mag
Dne petek, 09. junij 2023 ob 12:56:19 CEST je Andre Przywara napisal(a):
> In its of_xlate() function, the Allwinner USB PHY driver compares the
> args_count variable against the number of implemented USB PHYs, although
> this is the *number of arguments* to the DT phandle property. Per the DT
> bi
Dne petek, 09. junij 2023 ob 12:56:20 CEST je Andre Przywara napisal(a):
> The Allwinner F1C100s implements a single USB PHY, connected to its MUSB
> OTG controller. The USB PHY is of the simpler, older type (like the A10),
> the only real difference is that it's indeed only one PHY.
>
> Add a str
Dne petek, 09. junij 2023 ob 12:56:21 CEST je Andre Przywara napisal(a):
> At the moment we use "select" in each Allwinner SoC's Kconfig section to
> include the USB PHY driver in the build. This means it cannot be disabled
> via Kconfig, although USB is not really a strictly required core
> functi
Dne ponedeljek, 12. junij 2023 ob 01:32:38 CEST je Andre Przywara napisal(a):
> So far we were assigning some crude "type" (SoC name, really) to each
> Allwinner USB PHY model, then guarding certain quirks based on this.
> This does not only look weird, but gets more or more cumbersome to
> maintai
Dne ponedeljek, 12. junij 2023 ob 01:32:39 CEST je Andre Przywara napisal(a):
> The H616 USB PHY is some kind of special snowflake: Only port2 works out
> of the box, but all other ports need some help from this port2 to work
> correctly: The CLK_BUS_PHY2 and RST_USB_PHY2 clock and reset need to be
Dne ponedeljek, 12. junij 2023 ob 01:32:40 CEST je Andre Przywara napisal(a):
> Now that the Allwinner USB PHY driver supports the H616 quirk, let's
> enable support for USB ports on that SoC.
>
> We connect the compatible string to a new struct describing the SoCs USB
> PHY properties, and unbloc
Dne ponedeljek, 12. junij 2023 ob 01:32:41 CEST je Andre Przywara napisal(a):
> Now that the PHY driver supports the H616 USB PHY, we can enable USB
> support for the two H616 boards.
> As the OrangePi Zero2 has a USB-C port hard-wired to peripheral mode,
> let's enable USB gadget mode for port 0,
Dne torek, 13. junij 2023 ob 13:21:58 CEST je Andre Przywara napisal(a):
> Some older SoCs (<=A20, F1C100s) do not have a dedicated SRAM buffer for
> the USB-OTG controller, but require the CPU to relinquish one of its SRAM
> blocks to the USB controller. This is done by flipping a bit in the SRAM
Dne nedelja, 19. januar 2025 ob 17:41:54 Srednjeevropski standardni čas je
Andre Przywara napisal(a):
> In contrast to some other Allwinner SoCs, there is no difference between
> the DTs for the Allwinner F1C100/F1C200 SoCs (sunvi) between the U-Boot
> and the Linux kernel repository.
>
> Remove
Dne nedelja, 19. januar 2025 ob 17:41:53 Srednjeevropski standardni čas je
Andre Przywara napisal(a):
> This series converts boards with the Allwinner F1C100s/F1C200s, A10, A10s
> and A13s SoCs over to OF_UPSTREAM. The .dts and .dtsi files were
> identical between the kernel and U-Boot repository,
Dne petek, 17. januar 2025 ob 02:45:30 Srednjeevropski standardni čas je Andre
Przywara napisal(a):
> With each new SoC added to the clock_sun50i_h6.h header file, we add a
> list of default values for the bus clock registers. This list gets a bit
> hard to read, as the spacing between the lines l
Dne petek, 17. januar 2025 ob 02:45:31 Srednjeevropski standardni čas je Andre
Przywara napisal(a):
> Some of the X-Power AXP PMICs can be ordered with an alternative I2C
> address, for instance an AXP717 could be shipped with address 0x34 or
> with address 0x35.
> The datasheets for the AXP717 an
Dne petek, 17. januar 2025 ob 02:45:33 Srednjeevropski standardni čas je Andre
Przywara napisal(a):
> The Allwinner A100 SoC has been around for a while, and has now seemingly
> been replaced with its close sibling A133.
>
> Add support for the CCU, as far as used by U-Boot proper. Linux has some
Dne petek, 17. januar 2025 ob 02:45:32 Srednjeevropski standardni čas je Andre
Przywara napisal(a):
> The H616 DRAM controller requires some board specific parameters, which
> we declare in Kconfig, let each board specify in their defconfig, and
> then use in the DRAM init code.
>
> Other DRAM co
Dne petek, 17. januar 2025 ob 02:45:34 Srednjeevropski standardni čas je Andre
Przywara napisal(a):
> The Allwinner A100 SoC has been around for a while, and has now seemingly
> been replaced with its close sibling A133.
>
> Add the required mapping between the pinmux group strings and their
> re
Dne petek, 17. januar 2025 ob 02:45:35 Srednjeevropski standardni čas je Andre
Przywara napisal(a):
> The AXP803 has been around for about a decade now, but so far we didn't
> need SPL support, since the DRAM rail was wired up correctly at reset.
>
> Now some boards using the A133 SoC use the (co
Dne petek, 17. januar 2025 ob 02:45:37 Srednjeevropski standardni čas je Andre
Przywara napisal(a):
> The Allwinner A100 SoC has been around for a while, mostly on cheap
> tablets, but didn't generate much interest in the community so far.
> There were some efforts by two Allwinner employees in 20
Dne petek, 17. januar 2025 ob 02:45:36 Srednjeevropski standardni čas je Andre
Przywara napisal(a):
> From: Cody Eksal
>
> This adds preliminary support for the DRAM controller in the Allwinner
> A100/A133 SoCs.
> This is work in progress, and has rough edges, but works on at least
> three diffe
Dne ponedeljek, 20. januar 2025 ob 00:42:19 Srednjeevropski standardni čas je
Andre Przywara napisal(a):
> On Sun, 19 Jan 2025 20:45:43 +0100
> Jernej Škrabec wrote:
>
> Hi Jernej,
>
> > Dne nedelja, 19. januar 2025 ob 17:41:54 Srednjeevropski standardni čas je
> &g
Dne nedelja, 19. januar 2025 ob 23:25:30 Srednjeevropski standardni čas je
Andre Przywara napisal(a):
> On Sat, 18 Jan 2025 08:21:31 +0100
> Jernej Škrabec wrote:
>
> Hi Jernej,
>
> many thanks for the review and your opinion.
>
> > Dne petek, 17. januar 2025
Dne sreda, 26. februar 2025 ob 12:37:12 Srednjeevropski standardni čas je Andre
Przywara napisal(a):
> On the Allwinner D1/R528/T113-s3 SoCs (NCAT2) the factors encoded in
> the PLL register describe the doubled clock rate, as in the other SoCs.
>
> Correct for that by always dividing the calcula
Dne sreda, 26. februar 2025 ob 12:37:11 Srednjeevropski standardni čas je Andre
Przywara napisal(a):
> On the Allwinner D1/R528/T113-s3 SoCs the MMC clock source selected by
> mux value 1 is PLL_PERIPH0(1x), not (2x), as in the other SoCs.
> But we have still the hidden divisor of 2 in the MMC mod
Hi Andre!
Dne nedelja, 23. marec 2025 ob 12:35:11 Srednjeevropski standardni čas je Andre
Przywara napisal(a):
> U-Boot drivers often revert to using C structures for modelling hardware
> register frames. This creates some problems:
> - A "struct" is a C language construct to group several variab
Dne nedelja, 23. marec 2025 ob 12:35:23 Srednjeevropski standardni čas je Andre
Przywara napisal(a):
> From: Jernej Skrabec
>
> The watchdog in the Allwinner A523 SoC differs a bit from the one in the
> previous SoCs: it lives in a separate register frame, so no longer
> inside some timer device
Dne nedelja, 23. marec 2025 ob 12:35:26 Srednjeevropski standardni čas je Andre
Przywara napisal(a):
> Add a clock driver for the PRCM clock controller on the Allwinner A523
> family of SoCs, often also used with an "r" prefix or suffix.
> This just describes the clock gates and reset lines for th
Dne nedelja, 23. marec 2025 ob 12:35:36 Srednjeevropski standardni čas je Andre
Przywara napisal(a):
> Because the Allwinner BootROM always runs in AArch32, even on ARMv8 SoCs,
> we need to switch to AArch64 first, but also need to save the CPU state,
> when we later may need to return to the Boot
Dne nedelja, 23. marec 2025 ob 12:35:34 Srednjeevropski standardni čas je Andre
Przywara napisal(a):
> To return a 64-bit Allwinner chip back to the 32-bit BootROM code, we
> have some embedded AArch32 code that restores the CPU state, before
> branching back to the BootROM. At the moment the poin
Dne nedelja, 23. marec 2025 ob 12:35:37 Srednjeevropski standardni čas je Andre
Przywara napisal(a):
> To be able to return to the BootROM FEL USB debug code, we must restore
> the core's state as accurately as possible after the SPL has been run.
> Since the BootROM runs in AArch32, but the SPL u
Dne nedelja, 23. marec 2025 ob 12:35:38 Srednjeevropski standardni čas je Andre
Przywara napisal(a):
> Thanks for Jernej's JTAG debugging effort, it turns out that the BROM
> expects SP_IRQ to be saved and restored, when we want to enter back into
> FEL after the SPL's AArch64 stint.
> Save and re
Dne nedelja, 23. marec 2025 ob 12:35:32 Srednjeevropski standardni čas je Andre
Przywara napisal(a):
> Most Allwinner SoCs (used on 107 out of 172 boards) use a default CPU
> frequency of 1008 MHz during the initial setup in the SPL.
>
> Make this the fallback default, in case nothing else is sel
Dne nedelja, 23. marec 2025 ob 12:35:39 Srednjeevropski standardni čas je Andre
Przywara napisal(a):
> From: Jernej Skrabec
I'm sure you can take credit for this as it's just making definitions and
putting them in place. But I can also provide SoB if you want.
>
> ---
> .../include/asm/arch-s
Dne nedelja, 23. marec 2025 ob 12:35:33 Srednjeevropski standardni čas je Andre
Przywara napisal(a):
> Reorder the Kconfig defaults for the maximum SPL size, to make the
> Allwinner specific values more readable and extensible: many older SoCs
> need to be limited to 32KB, so make this the last AR
Dne nedelja, 23. marec 2025 ob 12:35:12 Srednjeevropski standardni čas je Andre
Przywara napisal(a):
> The Allwinner MMC code uses a complex C struct, modelling the clock
> device's register frame. We rely on sharing the member names across all
> Allwinner SoCs, which is fragile.
>
> Drop the usa
Dne nedelja, 23. marec 2025 ob 12:35:35 Srednjeevropski standardni čas je Andre
Przywara napisal(a):
> To be able to return to the BootROM when booting via the FEL USB
> protocol, we need to save the CPU state very early, which we need to do
> in the embedded AArch32 code. At the moment the pointe
Dne nedelja, 23. marec 2025 ob 12:35:40 Srednjeevropski standardni čas je Andre
Przywara napisal(a):
> From: Jernej Skrabec
>
> DRAM init code, as per reverse engineering and matching against
> previous SoCs.
> Supports LPDDR4 for now only.
> ---
> arch/arm/include/asm/arch-sunxi/dram.h
Dne četrtek, 27. marec 2025 ob 22:21:02 Srednjeevropski standardni čas je Andre
Przywara napisal(a):
> Now that eMMC is working properly on H616 devices, it became apparent
> that some boards were missing the right defconfig bits to enable eMMC
> access.
>
> Add the eMMC device number to the Tani
Dne torek, 25. marec 2025 ob 15:27:37 Srednjeevropski standardni čas je Andre
Przywara napisal(a):
> Hi Jernej,
>
> what do you think about this solution the A10 compilation problem?
> That looks like a simple change, somewhat half of the way to the proper
> solution.
> If you agree, I'd squash t
101 - 178 of 178 matches
Mail list logo
