PCIe layerscape ATU

Hello I have a question to this code (drivers/pci/pcie_layerscape.c): void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type, u64 phys, u64 bus_addr, u64 size) { dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | idx, PCIE_ATU_VIEWPORT); dbi_w

[U-Boot] new board with common code

Hi I'm adding a new board. It's very similar to freescale's P2020DS, that's why I used this code as starting point. The problem is now that it still uses some code from board/freescale/common. At the first try this didn't get built and therefore I get link errors. What's the preferred way in this

Re: [U-Boot] new board with common code

>> I'm adding a new board. It's very similar to freescale's P2020DS, that's >> why I used this code as starting point. The problem is now that it still >> uses some code from board/freescale/common. At the first try this >> didn't get built and therefore I get link errors. What's the preferred >>

[U-Boot] P2020 L2 cache as SRAM

Hi We're trying to configure the PPC P2020 cpu to use the L2 cache as SRAM so we can load the U-Boot code in there. However we stumble into problems. Sometimes the cpu goes on trap when trying to access this area. Sometimes there's no trap but we seem to access a different area. That's probably a

[U-Boot] PCIe and Dell parity interrupt

Hi We have a PCIe board with a PPC P2020 cpu. We're trying to set it up using U-Boot. Without initializing the PCIe part the PC won't even boot. Now we seem to have the initialization part running but we sometimes get an error on the PC: I/O Card Parity Interrupt Some googleing suggests that thi

Re: [U-Boot] P2020 L2 cache as SRAM

At 09:07 17.01.2011 +0100, Fabian Cenedese wrote: >Hi > >We're trying to configure the PPC P2020 cpu to use the L2 cache >as SRAM so we can load the U-Boot code in there. However we >stumble into problems. Sometimes the cpu goes on trap when >trying to access this area. So

Re: [U-Boot] P2020 L2 cache as SRAM

>> >We're trying to configure the PPC P2020 cpu to use the L2 cache >> >as SRAM so we can load the U-Boot code in there. However we >> >stumble into problems. Sometimes the cpu goes on trap when >> >trying to access this area. Sometimes there's no trap but we >> >seem to access a different area. T

[U-Boot] How to give RESET_VECTOR_ADDRESS

Hi As the config.mk file is doomed I tried to set my reset vector in another way. I first tried it in the board's config header. But that didn't seem to have an effect. I then tried a config option in the boards.cfg file but that also didn't work. The only way I could get it to work so far was wit

Re: [U-Boot] How to give RESET_VECTOR_ADDRESS

At 09:38 25.01.2011 -0600, Kumar Gala wrote: >On Jan 25, 2011, at 7:25 AM, Fabian Cenedese wrote: > >> Hi >> >> As the config.mk file is doomed I tried to set my reset vector >> in another way. I first tried it in the board's config header. But >> that di

Re: [U-Boot] How to give RESET_VECTOR_ADDRESS

At 08:47 26.01.2011 +0100, Fabian Cenedese wrote: >At 09:38 25.01.2011 -0600, Kumar Gala wrote: > >>On Jan 25, 2011, at 7:25 AM, Fabian Cenedese wrote: >> >>> Hi >>> >>> As the config.mk file is doomed I tried to set my reset vector >>>

Re: [U-Boot] [PATCH 5/8 v3] P1021: add P1021MDS board support

At 23:58 27.01.2011 -0500, haiying.w...@freescale.com wrote: >From: Haiying Wang > >Support P1021MDS board to boot from NAND flash (No NOR flash on this >board). And because P1021 only has 256K L2 SRAM, which can not used for final >uboot image, this patch also enables the TPL BOOT on P1021MDS so

[U-Boot] mpc85xx endless ddr init

Hi Since I updated to the last u-boot version my board keeps stalling in a newly added loop in ddr3-gen.c. At the end of the function fsl_ddr_set_memctl_regs is a loop that tests an undocumented register (at least it's not in the reference manuals). while (!(in_be32(&ddr->debug[1]) & 0x2)

Re: [U-Boot] mpc85xx endless ddr init

>> Since I updated to the last u-boot version my board keeps stalling >> in a newly added loop in ddr3-gen.c. At the end of the function >> fsl_ddr_set_memctl_regs is a loop that tests an undocumented >> register (at least it's not in the reference manuals). >> >> while (!(in_be32(&ddr->deb

[U-Boot] P2020 SPL L2 clearing

Hi I'm creating a SPL u-boot image for our board. In the file arch/powerpc/cpu/mpc85xx/cpu_init_nand.c is the setup for the L2 cache as SRAM. In the end is a loop that fills the cache with 0 (512KB in this case). /* Initialize L2 SRAM to zero */ l2srbar = (char *)CONFIG_SYS_INIT_L

Re: [U-Boot] P2020 SPL L2 clearing

At 14:17 03.02.2011 +0100, Fabian Cenedese wrote: >Hi > >I'm creating a SPL u-boot image for our board. In the file >arch/powerpc/cpu/mpc85xx/cpu_init_nand.c is the setup for >the L2 cache as SRAM. In the end is a loop that fills the >cache with 0 (512KB in this case). >

Re: [U-Boot] Policy for checkpatch usage?

At 10:49 21.04.2011 -0400, Eric Cooper wrote: >On Thu, Apr 21, 2011 at 04:29:17PM +0200, Detlev Zundel wrote: >> What about the problem with checkpatch errors in current code, i.e. the >> origin of this sentence: >> >> Also warnings produced for context lines (i.e. existing code) rather >> tha

[U-Boot] Full amount of sdram

Hi I'm trying to get the full size of the sdram, not the available size as in gd->ram_size. We use a P2020 so I'm looking in the fsl_ code. I tried it with fsl_ddr_sdram_size() which from the comment should just return the size and don't do anything else. However this is already called in the u-b

Re: [U-Boot] P2020 SPL L2 clearing

>>> I'm creating a SPL u-boot image for our board. In the file >>> arch/powerpc/cpu/mpc85xx/cpu_init_nand.c is the setup for >>> the L2 cache as SRAM. In the end is a loop that fills the >>> cache with 0 (512KB in this case). >>> >>> 1. Why is the access byte-wise and not dword-wise? This >>> is

Re: [U-Boot] P2020 SPL L2 clearing

>>> 2. Why does the cache to be cleared at all? L2-SRAM is usually >>> just used to copy in the second part of the u-boot image, so >>> the 0s will be overwritten again anyway. > >This needs to be done because we enable ECC. I'm still trying to get my head around this. From looking at the code th

[U-Boot] [PATCH] Removed clearing of L2-as-SRAM

Removed clearing of L2 cache as SRAM as it is not necessary without ECC. This also speeds up the booting process. Signed-off-by: Fabian Cenedese Cc: Kumar Gala --- arch/powerpc/cpu/mpc85xx/cpu_init_nand.c |7 --- 1 files changed, 0 insertions(+), 7 deletions(-) diff --git a/arch

[U-Boot] P2020 L1 stack flickering

Hi I'm trying to adjust u-boot to our board which is using a P2020. I'm having strange effects with the stack in the L1 data cache, during the NAND phase as well as in the SPL main u-boot. Sometimes when a value is written to the cache this value itself shows up correctly. However it's possible t

[U-Boot] get ram size/end in env var

Hi I want to add in my board's config header an environment command that needs the ram end address (or ram size as ram starts at 0). As the sdram size can differ I'd like to get it at runtime and then jump there with the "go" command (minus some offset). How could I do that? Thanks bye Fabi __

Re: [U-Boot] [PATCH] Removed clearing of L2-as-SRAM

At 12:59 14.02.2011 +0100, Fabian Cenedese wrote: >Removed clearing of L2 cache as SRAM as it is not necessary without ECC. >This also speeds up the booting process. > >Signed-off-by: Fabian Cenedese >Cc: Kumar Gala >--- > arch/powerpc/cpu/mpc85xx/cpu_init_nand.c |7

Re: [U-Boot] Please pull u-boot-mpc85xx.git

At 09:14 04.04.2011 -0500, you wrote: >The following changes since commit 19b54a701811220221fc4d5089a2bb18892018ca: > > Prepare v2011.03 (2011-03-31 23:45:36 +0200) > >are available in the git repository at: > git://git.denx.de/u-boot-mpc85xx.git master May I also ask about this patch? Removed

Re: [U-Boot] get ram size/end in env var

At 15:47 18.03.2011 +0100, Fabian Cenedese wrote: >Hi > >I want to add in my board's config header an environment command >that needs the ram end address (or ram size as ram starts at 0). >As the sdram size can differ I'd like to get it at runtime and then >jump there