At 23:58 27.01.2011 -0500, haiying.w...@freescale.com wrote: >From: Haiying Wang <haiying.w...@freescale.com> > >Support P1021MDS board to boot from NAND flash (No NOR flash on this >board). And because P1021 only has 256K L2 SRAM, which can not used for final >uboot image, this patch also enables the TPL BOOT on P1021MDS so that DDR can >be initialized in L2 SRAM through SPD code. So there are three stage uboot >images: >* nand_spl, pad from 4KB size to 16KB, load tpl_boot from offset 16KB in NAND. >* tpl_boot, 112KB size. The env variables are copied to offset 128KB > in L2 SRAM, so that ddr spd code can get the interleaving mode setting in > env. > It loads final uboot image from offset 128KB in NAND. >* final uboot image, size is variable depends on the functions enabled.
I'm not questioning the patch, I'm just trying to understand. >+#define CONFIG_MP /* Multiprocessor support */ >+ >+#define CONFIG_PCI /* Disable PCI/PCIE */ Shouldn't that be "Enable" PCI? bye Fabi _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
