ned-off-by: Jonas Karlman
---
Cc: David Wu
Cc: Ezequiel Garcia
---
drivers/net/Kconfig| 8 +
drivers/net/Makefile | 1 +
drivers/net/dwc_eth_qos.c | 8 +-
drivers/net/dwc_eth_qos.h | 2 +
drivers/net/dwc_eth_qos_rockch
tch the alias stem is a more
reasonable way.
Signed-off-by: David Wu
---
net/eth-uclass.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/net/eth-uclass.c b/net/eth-uclass.c
index e14695c0f1..7dd962db64 100644
--- a/net/eth-uclass.c
+++ b/net/eth-uclass.c
@@ -594,7 +594,7 @@ stat
tch the alias stem is a more
reasonable way.
Signed-off-by: David Wu
---
net/eth-uclass.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/net/eth-uclass.c b/net/eth-uclass.c
index e14695c0f1..3497a17db6 100644
--- a/net/eth-uclass.c
+++ b/net/eth-uclass.c
@@ -593,8 +593,8 @@ stat
Rockchip Socs can support two controllers "snps, dwmac-4.20a"
and "snps, dwmac-3.50". In order to support two at gmac-rockchip.c,
export public interface functions and struct data, it will be more
general for others.
David Wu (8):
net: dwc_eth_qos: Use dev_ functions c
It seems dev_ functions are more general than fdt_ functions.
Signed-off-by: David Wu
---
drivers/net/dwc_eth_qos.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 63f2086dec..a72132cacf 100644
--- a/drivers
It can be seen that most of the Socs using STM mac, "snps,reset-gpio"
gpio is used, adding this option makes reset function more general.
Signed-off-by: David Wu
---
drivers/net/dwc_eth_qos.c | 40 ++-
1 file changed, 35 insertions(+), 5 deletion
After moving to eqos_ops, if eqos_config is defined
outside, can not export interface() definition.
Signed-off-by: David Wu
---
drivers/net/dwc_eth_qos.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
When using rgmii Gigabit mode, the wait_for_bit_le32()
reset method resulting in RX can not receive data, after
this patch, works well.
Signed-off-by: David Wu
---
drivers/net/dwc_eth_qos.c | 21 +++--
1 file changed, 15 insertions(+), 6 deletions(-)
diff --git a/drivers/net
Before enabling mac and mac working, we need to obtain
the current link speed to configure the clock, so split
eqos_start into two functions.
Signed-off-by: David Wu
---
drivers/net/dwc_eth_qos.c | 56 ++-
1 file changed, 38 insertions(+), 18 deletions
Open structure data and interface, so that Soc using dw_eth_qos
controller can reference.
Signed-off-by: David Wu
---
drivers/net/dwc_eth_qos.c | 81 +--
1 file changed, 9 insertions(+), 72 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net
For others using, clk_rx and clk_tx may not be necessary,
and their clock names are different.
Signed-off-by: David Wu
---
drivers/net/dwc_eth_qos.c | 65 +++
1 file changed, 31 insertions(+), 34 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers
Change the original data structure so that Rockchip's Soc
gmac controller can support the designware.c and dwc_eth_qos.c
drivers, a Soc can only support one.
Signed-off-by: David Wu
---
drivers/net/Kconfig | 2 +-
drivers/net/gmac_rockchip.c
Hi Stephen,
在 2020/5/1 上午6:36, Stephen Warren 写道:
The kernel's bindings/net/snps,dwmac.yaml does not mention any
reset-gpios property (which is what the existing code parses just above
the portion that is quoted by this patch as context). I suspect that
this patch should simply change the name o
Hi Patrice,
在 2020/4/30 下午11:47, Patrice CHOTARD 写道:
@@ -701,6 +702,15 @@ static int eqos_start_resets_stm32(struct udevice *dev)
debug("%s(dev=%p):\n", __func__, dev);
if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) {
+ ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0)
Hi Stephen,
在 2020/5/1 上午6:39, Stephen Warren 写道:
On 4/30/20 4:36 AM, David Wu wrote:
After moving to eqos_ops, if eqos_config is defined
outside, can not export interface() definition.
Looking at the patch itself, I think this patch just moves a function
pointer from the config to the ops
Hi Stephen,
在 2020/5/9 上午10:41, David Wu 写道:
The kernel's ./Documentation/devicetree/bindings/net/stmmac.txt mentions
that Required properties:
- phy-mode: See ethernet.txt file in the same directory.
- snps,reset-gpio gpio number for phy reset.
- snps,reset-active-low boolean fl
Hi Patrice,
在 2020/4/30 下午10:00, Patrice CHOTARD 写道:
@@ -647,8 +653,10 @@ static void eqos_stop_clks_stm32(struct udevice *dev)
debug("%s(dev=%p):\n", __func__, dev);
- clk_disable(&eqos->clk_tx);
- clk_disable(&eqos->clk_rx);
+ if (clk_valid(&eqos->clk_tx))
+
Hi Stephen,
在 2020/5/1 上午6:45, Stephen Warren 写道:
Oh... Judging by your email, you're trying to make this driver work on a
Rockchip system. However, you're editing an STM32-specific probe
function. You should introduce a new probe function for Rockchip if it
needs to work differently to the exis
Hi Patrice,
在 2020/4/30 下午11:33, Patrice CHOTARD 写道:
Can you explain why you are splitting this function in 2 parts and calling
these parts sequentially ?
For rockchip, need to obtain the current link speed to configure the tx
clocks, (for example, in rgmii mode, 1000M link: 125M, 100M link:
Hi Stephen,
在 2020/5/1 上午6:52, Stephen Warren 写道:
I'm really confused; with a filename like gmac_rockchip.c that sounds
like it's driver for a MAC device. DWC EQoS is also a MAC device. The
two shouldn't be related or coupled in any way.
I think what you need is to completely drop this patch (a
rice)
- None
- Don't change the Rx and Tx clock names. (Patrice, Stephen)
- None
- None
- Add the lost head file. (Patrice)
- None
- None
- None
- None
David Wu (11):
net: dwc_eth_qos: Use dev_ functions calls to get FDT data
net: dwc_eth_qos: Add option "snps,reset-gpio" phy-rs
After moving to eqos_ops, if eqos_config is defined
outside file, can not export interface() definition,
only export eqos_ops struct defined in dwc_eth_qos.c.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/dwc_eth_qos.c | 14 +++---
1 file changed, 7 insertions(+), 7
It can be seen that most of the Socs using STM mac, "snps,reset-gpio"
gpio is used, adding this option makes reset function more general.
Signed-off-by: David Wu
---
Changes in v2:
- Remove the code is not related (Patrice)
drivers/net/dwc_eth_qos.c | 32 +
For others using, clk_rx and clk_tx may not be necessary,
and their clock names are different.
Signed-off-by: David Wu
---
Changes in v2:
- Don't change the Rx and Tx clock names. (Patrice, Stephen)
drivers/net/dwc_eth_qos.c | 61 +++
1 file change
It seems dev_ functions are more general than fdt_ functions.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/dwc_eth_qos.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 63f2086dec
For Rockchip, before enabling mac and mac working, we
need to obtain the current link speed to configure the
TX/RX clocks, so split eqos_start into two functions.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/dwc_eth_qos.c | 56 ++-
1 file
If there are definitions for eqos_start_clks and eqos_stop_clks,
then call these callback function.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/dwc_eth_qos.c | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b
Change the original data structure so that Rockchip's Soc
gmac controller can support the designware.c and dwc_eth_qos.c
drivers, a Soc can only support one.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/Kconfig | 2 +-
drivers/net/gmac_rockchip.c
The eqos_rockchip_ops is simillar to eqos_stm32_ops, and
export the eqos_rockchip_ops to use.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/dwc_eth_qos.c | 16
drivers/net/dwc_eth_qos.h | 2 ++
2 files changed, 18 insertions(+)
diff --git a/drivers/net
The Rockchip CSR clock range is from 100M to 150M, add
EQOS_MAC_MDIO_ADDRESS_CR_100_150.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/dwc_eth_qos.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
index
This Soc is different from the previous Socs, need to
define eqos_config, and follow the dwc_eth_qos driver
process.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/gmac_rockchip.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/net
Discard this duplicate patch.
在 2020/5/11 下午3:08, David Wu 写道:
The Rockchip CSR clock range is from 100M to 150M, add
EQOS_MAC_MDIO_ADDRESS_CR_100_150.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/dwc_eth_qos.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
Open structure data and interface, so that Soc using dw_eth_qos
controller can reference.
Signed-off-by: David Wu
---
Changes in v2:
- Add the lost head file. (Patrice)
drivers/net/dwc_eth_qos.c | 81
drivers/net/dwc_eth_qos.h | 87
The Rockchip CSR clock range is from 100M to 150M, add
EQOS_MAC_MDIO_ADDRESS_CR_100_150.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/dwc_eth_qos.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
index
Hi Patrice,
在 2020/5/11 下午8:48, Patrice CHOTARD 写道:
Hi David
On 5/9/20 8:42 AM, David Wu wrote:
Hi Patrice,
在 2020/4/30 下午11:33, Patrice CHOTARD 写道:
Can you explain why you are splitting this function in 2 parts and calling
these parts sequentially ?
For rockchip, need to obtain the
rice)
- None
- Don't change the Rx and Tx clock names. (Patrice, Stephen)
- None
- None
- Add the lost head file. (Patrice)
- None
- None
- None
- None
David Wu (11):
net: dwc_eth_qos: Use dev_ functions calls to get FDT data
net: dwc_eth_qos: Add option "snps,reset-gpio" phy-rs
It seems dev_ functions are more general than fdt_ functions.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/dwc_eth_qos.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index f67c5f4570
It can be seen that most of the Socs using STM mac, "snps,reset-gpio"
gpio is used, adding this option makes reset function more general.
Signed-off-by: David Wu
---
Changes in v2:
- Remove the code is not related (Patrice)
drivers/net/dwc_eth_qos.c | 32 +
For others using, clk_rx and clk_tx may not be necessary,
and their clock names are different.
Signed-off-by: David Wu
---
Changes in v2:
- Don't change the Rx and Tx clock names. (Patrice, Stephen)
drivers/net/dwc_eth_qos.c | 61 +++
1 file change
according to the current link speed.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/dwc_eth_qos.c | 56 ++-
1 file changed, 38 insertions(+), 18 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index bec9bf556b
If there are definitions for eqos_start_clks and eqos_stop_clks,
then call these callback function.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/dwc_eth_qos.c | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b
After moving to eqos_ops, if eqos_config is defined
outside file, can not export interface() definition,
only export eqos_ops struct defined in dwc_eth_qos.c.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/dwc_eth_qos.c | 20 ++--
1 file changed, 10 insertions
Open structure data and interface, so that Soc using dw_eth_qos
controller can reference.
Signed-off-by: David Wu
---
Changes in v2:
- Add the lost head file. (Patrice)
drivers/net/dwc_eth_qos.c | 81
drivers/net/dwc_eth_qos.h | 87
Change the original data structure so that Rockchip's Soc
gmac controller can support the designware.c and dwc_eth_qos.c
drivers, a Soc can only support one.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/Kconfig | 2 +-
drivers/net/gmac_rockchip.c
The Rockchip CSR clock range is from 100M to 150M, add
EQOS_MAC_MDIO_ADDRESS_CR_100_150.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/dwc_eth_qos.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
index
The eqos_rockchip_ops is simillar to eqos_stm32_ops, and
export the eqos_rockchip_ops to use.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/dwc_eth_qos.c | 16
drivers/net/dwc_eth_qos.h | 2 ++
2 files changed, 18 insertions(+)
diff --git a/drivers/net
This Soc is different from the previous Socs, need to
define eqos_config, and follow the dwc_eth_qos driver
process.
Signed-off-by: David Wu
---
Changes in v2:
- None
drivers/net/gmac_rockchip.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/net
.
Thanks
Patrice
On 5/11/20 9:00 AM, David Wu wrote:
Rockchip Socs can support two controllers "snps, dwmac-4.20a"
and "snps, dwmac-3.50". In order to support two at gmac-rockchip.c,
export public interface functions and struct data, it will be more
general for others.
C
s are inherited based on the devices
sequence IDs which is in turn given by the device tree.
Before there are more users in u-boot and both worlds will differ even
more, rename the alias prefix to "ethernet" to match the linux ones.
Also adapt the test cases and rename any old aliases in
Hi Patrick,
Yes, this is the case, it should be add at PHY node, and I also used the
original writing "snps,reset*" at MAC node. Anyway, I will try to put
the reset gpio in the PHY node.
在 2020/5/13 下午8:55, Patrick DELAUNAY 写道:
Hi David
From: David Wu
Sent: mardi 12 mai 2020
Hi Tom,
在 2020/6/12 下午10:48, Tom Rini 写道:
On Tue, May 12, 2020 at 05:56:01PM +0800, David Wu wrote:
It can be seen that most of the Socs using STM mac, "snps,reset-gpio"
gpio is used, adding this option makes reset function more general.
Signed-off-by: David Wu
Reviewed-by: Patri
,
Reviewed-by: David Wu
在 2020/6/27 下午11:03, Alexander Kochetkov 写道:
To make clear, there is kernel driver i2c-rk3x.c.
For rk3066 it write bits in the GRF word at offset 0x154. See [1] and [2].
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/i2c/busses/i2c
Hi Pierre-Clément,
Thanks for your correction, there was wrong mask here.
Reviewed-by: David Wu
在 2022/4/6 23:08, Kever Yang 写道:
Add David,
Hi David,
Could you help to check this patch?
Thanks,
- Kever
On 2022/3/16 23:39, Pierre-Clément Tosi wrote:
Swap the arguments as that seems
Hi list,
This is my first time to submit a patch to this list. I hope it is in the
correct format. All these patches are based on the Mar. 15's git tree plus
16 patches from TsiChung.
David Wu (7):
Colfdfire MCF5282: enable icache if CONFIG_SYS_ENABLE_ICACHE is
defined
AT49B
Signed-off-by: David Wu
---
CREDITS |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/CREDITS b/CREDITS
index 043ba6e..144fc27 100644
--- a/CREDITS
+++ b/CREDITS
@@ -513,7 +513,7 @@ D: Port to MPC555/556 microcontrollers and support for
cmi board
N: David Wu
E
Signed-off-by: David Wu
---
cpu/mcf52x2/cpu_init.c |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c
index 170bbfc..36f62cc 100644
--- a/cpu/mcf52x2/cpu_init.c
+++ b/cpu/mcf52x2/cpu_init.c
@@ -621,8 +621,10 @@ void
The device id for this Flash is 0xc8.
Signed-off-by: David Wu
---
drivers/mtd/cfi_flash.c |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
index fdba297..af86f99 100644
--- a/drivers/mtd/cfi_flash.c
+++ b
Signed-off-by: David Wu
---
Makefile | 46 +
board/Arcturus/uC5272/Makefile | 44 +
board/Arcturus/uC5272/config.mk |1 +
board/Arcturus/uC5272/u-boot.lds | 142 +++
board/Arcturus/uC5272/uC5272.c | 57 ++
include/configs
Signed-off-by: David Wu
---
Makefile | 21 +++
board/Arcturus/uC5275/Makefile | 44 +++
board/Arcturus/uC5275/config.mk | 23
board/Arcturus/uC5275/u-boot.lds | 139
board/Arcturus/uC5275/uC5275.c | 118
Signed-off-by: David Wu
---
board/Mercury/ep2500/Makefile | 44 ++
board/Mercury/ep2500/config.mk | 23 +++
board/Mercury/ep2500/ep2500.c | 191 +
board/Mercury/ep2500/u-boot.lds | 140 ++
include/configs/EP2500.h| 297
Hi Stefan,
I am new here and I am not quite clear about how to split this patch.
Any suggestion?
Regards,
David
On Thu, 08 Apr 2010 05:35:35 -0400, Stefan Roese wrote:
> On Thursday 08 April 2010 02:00:23 David Wu wrote:
>> The device id for this Flash is 0xc8.
>>
>>
Hi Stefan,
On Thu, 08 Apr 2010 11:21:45 -0400, Stefan Roese wrote:
> Hi David,
>
> On Thursday 08 April 2010 17:16:26 David Wu wrote:
>> I am new here and I am not quite clear about how to split this patch.
>> Any suggestion?
>
> I didn't mean that you shoul
Hi Stefan,
I think those patches if I resubmit are same as before except the subjects
differ.
Anyway If no one complains then I will send.
Regards,
David
On Fri, 09 Apr 2010 02:46:17 -0400, Stefan Roese wrote:
> Hi David,
>
> On Thursday 08 April 2010 17:47:46 David Wu wrote:
>
Signed-off-by: David Wu
---
cpu/mcf52x2/cpu_init.c |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c
index 170bbfc..36f62cc 100644
--- a/cpu/mcf52x2/cpu_init.c
+++ b/cpu/mcf52x2/cpu_init.c
@@ -621,8 +621,10
Signed-off-by: David Wu
---
board/Mercury/ep2500/Makefile | 44 ++
board/Mercury/ep2500/config.mk | 23 +++
board/Mercury/ep2500/ep2500.c | 191 +
board/Mercury/ep2500/u-boot.lds | 140 ++
include/configs/EP2500.h
The device id for this Flash is 0xc8.
Signed-off-by: David Wu
---
drivers/mtd/cfi_flash.c |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
index fdba297..af86f99 100644
--- a/drivers/mtd/cfi_flash.c
+++ b
Signed-off-by: David Wu
---
Makefile | 46 +
board/Arcturus/uC5272/Makefile | 44 +
board/Arcturus/uC5272/config.mk |1 +
board/Arcturus/uC5272/u-boot.lds | 142 +++
board/Arcturus/uC5272/uC5272.c | 57 ++
include
Signed-off-by: David Wu
---
Makefile | 21 +++
board/Arcturus/uC5275/Makefile | 44 +++
board/Arcturus/uC5275/config.mk | 23
board/Arcturus/uC5275/u-boot.lds | 139
board/Arcturus/uC5275/uC5275.c | 118
Signed-off-by: David Wu
---
CREDITS |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/CREDITS b/CREDITS
index 043ba6e..144fc27 100644
--- a/CREDITS
+++ b/CREDITS
@@ -513,7 +513,7 @@ D: Port to MPC555/556 microcontrollers and support for
cmi board
N: David Wu
The device id for this Flash is 0xc8.
Signed-off-by: David Wu
---
drivers/mtd/cfi_flash.c |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
index fdba297..af86f99 100644
--- a/drivers/mtd/cfi_flash.c
+++ b/drivers
Hi Wolfgang,
Thanks for checking the patch, Please see inline.
On Fri, 09 Apr 2010 18:51:06 -0400, Wolfgang Denk wrote:
> Dear "David Wu",
>
> In message you wrote:
>> Signed-off-by: David Wu
>> ---
>> board/Mercury/ep2500/Makefile | 44 +
Hi Wolfgang,
On Fri, 09 Apr 2010 18:54:33 -0400, Wolfgang Denk wrote:
> Dear "David Wu",
>
> In message you wrote:
>> Signed-off-by: David Wu
>> ---
>> Makefile | 46 +
>> board/Arcturus/uC5272/Makefile | 44
Hi Lukasz,
在 2019/1/19 上午7:34, Lukasz Majewski 写道:
Hi David,
Hi Heiko,
在 2019/1/6 上午1:17, Heiko Stuebner 写道:
diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c
b/arch/arm/mach-rockchip/rk3188-board-spl.c index
3c6c3d3c09..a5e4d39cb7 100644 ---
a/arch/arm/mach-rockchip/rk3188-board-spl.c
Ping Philipp...
在 2019/1/22 上午2:50, Simon Glass 写道:
Hi,
On Thu, 3 Jan 2019 at 01:51, David Wu wrote:
The common pinctrl driver for rockchip Socs, it depends the PINCTRL_FULL config.
If use it, the default pinctrl setup from DTS could be configured at device
probe.
Changes in v2:
- Remove
Hi Christoph,
I once submitted a series of patches that they can support all Socs'
Pinctrl and how do you feel about using them.
http://patchwork.ozlabs.org/patch/868849/
在 2018/12/27 上午9:11, Kever Yang 写道:
Add David to review the pinctrl driver.
Thanks,
- Kever
On 12/17/2018 09:30 PM, Chr
Hi Christoph,
This patch seems is less of code about drive strength, for some modules,
like LCD, Ethernet is still needed.
在 2018/12/27 下午9:13, Christoph Müllner 写道:
Hi David,
On 12/27/18 1:49 PM, David Wu wrote:
Hi Christoph,
I once submitted a series of patches that they can support all
Hi Philipp,
在 2018/12/27 下午10:31, Philipp Tomsich 写道:
David,
On 27.12.2018, at 13:49, David Wu wrote:
Hi Christoph,
I once submitted a series of patches that they can support all Socs' Pinctrl
and how do you feel about using them.
http://patchwork.ozlabs.org/patch/868849/
Which re
The common pinctrl driver for rockchip Socs, it depends the PINCTRL_FULL config.
If use it, the default pinctrl setup from DTS could be configured at device
probe.
Changes in v2:
- Remove px30, rk2928, rk3066*.
- Split it to multiple files for the relevant per-SoC data structures.
David Wu (9
When the boot ROM sets up MMC we don't need to do it again. Remove the
MMC setup code entirely, but we also need to enable uart for debug message.
Signed-off-by: David Wu
---
Changes in v2: None
arch/arm/mach-rockchip/rk3188-board-spl.c | 41 ++-
1 file chang
The FDT is requested for new pinctrl driver, disable SPL_OF_PLATDATA
to make FDT be built in.
Signed-off-by: David Wu
---
Changes in v2: None
configs/evb-rk3399_defconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
index
It seems that pinctrl is not requested for rk3188 SPL, remove it so
that can save more space for SPL image size.
Signed-off-by: David Wu
Reviewed-by: Philipp Tomsich
---
Changes in v2: None
arch/arm/mach-rockchip/Kconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/mach
If we use the new pinctrl driver, the pinctrl setup will be done
by device probe. Remove the pinctrl setup at rk3288-board-spl.
Signed-off-by: David Wu
Reviewed-by: Philipp Tomsich
---
Changes in v2: None
arch/arm/mach-rockchip/rk3288-board-spl.c | 79 ---
1 file changed
The FDT is requested for new pinctrl driver, disable SPL_OF_PLATDATA
and enable SPL_OF_LIBFDT to make FDT be built in.
Signed-off-by: David Wu
---
Changes in v2: None
configs/chromebit_mickey_defconfig | 2 --
configs/chromebook_jerry_defconfig | 2 --
configs/chromebook_minnie_defconfig
Use this driver to fit all Rockchip SOCs and to support
the desired pinctrl configuration via DTS.
Signed-off-by: David Wu
---
Changes in v2:
- Remove px30, rk2928, rk3066*.
- Split it to multiple files for the relevant per-SoC data structures.
drivers/pinctrl/Kconfig
If we used the pinctrl-rockchip driver, these config is not needed,
so remove them.
Signed-off-by: David Wu
---
Changes in v2: None
configs/chromebit_mickey_defconfig | 2 --
configs/chromebook_jerry_defconfig | 2 --
configs/chromebook_minnie_defconfig | 2 --
configs/evb-px5_defconfig
To match the iomux setting of uart2 at SPL, correct the uart2
default pin configuration, if not changed, the evb-rk3229 can't
output the log message.
Signed-off-by: David Wu
---
Changes in v2: None
arch/arm/dts/rk322x.dtsi | 11 +--
1 file changed, 9 insertions(+), 2 dele
Hi Heiko,
在 2019/1/6 上午1:17, Heiko Stuebner 写道:
diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c
b/arch/arm/mach-rockchip/rk3188-board-spl.c
index 3c6c3d3c09..a5e4d39cb7 100644
--- a/arch/arm/mach-rockchip/rk3188-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3188-board-spl.c
@@ -120,7 +120,7
If the tx_delay is not enabled, the RGMII/1000M can't work.
Signed-off-by: David Wu
---
arch/arm/include/asm/arch-rockchip/grf_rk3288.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
b/arch/arm/include/asm/arch-roc
Hi Philipp,
在 2018年02月19日 03:36, Philipp Tomsich 写道:
On Sat, 3 Feb 2018, David Wu wrote:
Some Socs both have rgmii and rmii interface, so we need to
separate their speed setting.
Signed-off-by: David Wu
Acked-by: Philipp Tomsich
---
drivers/net/gmac_rockchip.c | 62
Hi Philipp,
在 2018年02月19日 03:38, Philipp Tomsich 写道:
On Sat, 3 Feb 2018, David Wu wrote:
In fact, the evb-rk3229 is default supported the integrated phy,
not need to change any hardware. So it is better to enbale it and
disable external 1000M phy.
Signed-off-by: David Wu
Acked-by: Philipp
Hi Philipp,
在 2018年02月19日 03:00, Philipp Tomsich 写道:
On Sat, 3 Feb 2018, David Wu wrote:
When the boot ROM sets up MMC we don't need to do it again. Remove the
MMC setup code entirely, but we also need to enable uart for debug
message.
If the MMC always set up correctly fo
Hi Philipp,
Okay, each SOC should have its own file, which include private data
structure, and probe(). Can reduce driver size.
在 2018年02月19日 03:20, Philipp Tomsich 写道:
On Sat, 3 Feb 2018, David Wu wrote:
Use this driver to fit all Rockchip SOCs and to support
the desired pinctrl
Unfortunately, the integrated macphy default is enabled, which will
increase power consuming, if we do not use this PHY. So let's disable
it at first, which will save power consuming. If we really use it, then
enable it in driver level.
Signed-off-by: David Wu
---
arch/arm/include/asm
Clean the grf offset at gmac_rockchip.c
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David Wu (18):
rockchip: clk: Add mac clock set for rk3399
rockchip: dts: rk3399-evb: Change the tx/rx delay
nt preview: Assuming mac_clk is fed by an external clock, set clk_rmii_src
clock select control register from IO for rgmii interface. Signed-off-by:
David Wu Acked-by: Philipp Tomsich
Reviewed-by: Philipp Tomsich ---
[...]
Content analysis details: (5.7 points, 5.0 required)
pts
nt preview: Give the mac controller the correct tx-delay and rx-delay
value for the rgmii mode transmission. If they are not matched, there would
be Ethernet packets lost, the net feature may not work. Signed-off-by: David
Wu Acked-by: Philipp Tomsich
Reviewed-by: Phili
If the Ethernet address is not set, the network can't work,
enable the random address config for default use.
Signed-off-by: David Wu
Acked-by: Philipp Tomsich
Reviewed-by: Philipp Tomsich
---
Changes in v2: None
configs/evb-rk3288_defconfig | 1 +
1 file changed, 1 insertion(+)
diff
The last 4 grf registers offset of rv1108 are wrong, fix them
for correct usage.
Signed-off-by: David Wu
---
Changes in v2:
- New patch
arch/arm/include/asm/arch-rockchip/grf_rv1108.h | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch
nt preview: If we include both the rk3288_grf.h and rv1108_grf.h, it will
cause the conflicts of redefinition. Clean the iomux definitions at
grf_rv1108.h,
and move them into pinctrl-driver. Signed-off-by: David Wu
--- [...]
Content analysis details: (6.5 points, 5.0 required)
pts
The rv1108 GMAC only support rmii interface, so need to add the
set_rmii() ops. Use the phy current interface to set rmii or
rgmii ops. At the same time, need to set the mac clock rate of
rmii with 50M, the clock rate of rgmii with 125M.
Signed-off-by: David Wu
---
Changes in v2:
- Add check
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