This patch appends CMA configuration to bootargs for LS1021ATWR board.
Signed-off-by: Shengzhou Liu
Signed-off-by: Alison Wang
---
Changes for v2:
- Append CMA configuration to bootargs directly
include/configs/ls1021atwr.h | 8
1 file changed, 4 insertions(+), 4 deletions
This patch appends othbootargs to bootargs for LS1021ATWR board.
Signed-off-by: Alison Wang
---
include/configs/ls1021atwr.h | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 8e2784b..266107c 100644
--- a
According to commit , this patch appends CMA configuration
to bootargs for LS1021ATWR.
Signed-off-by: Shengzhou Liu
Signed-off-by: Alison Wang
---
include/configs/ls1021atwr.h | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/include/configs/ls1021atwr.h b/include
Signed-off-by: Alison Wang
---
Change in v2:
- Update the comment.
include/configs/ls1021atwr.h | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index a6289850ca..45ce460dca 100644
--- a/include/configs
Hi, Priyanka,
> -Original Message-
> From: Priyanka Jain
> Sent: Thursday, April 23, 2020 6:32 PM
> To: Alison Wang ; u-boot@lists.denx.de; Jagdish
> Gediya
> Cc: Shengzhou Liu
> Subject: RE: [PATCH] configs: ls1021a: Append CMA configuration to bootargs
>
The default reserved memory for CMA is high memory. If LPAE is enabled,
highmem pages are non-remapped and can not be used with
dma_alloc_coherent. This patch will reserve low memory for CMA and fix
the issue on LS1021A.
Signed-off-by: Peng Ma
Signed-off-by: Shengzhou Liu
Signed-off-by: Alison
This patch sets CONFIG_SYS_BOOTMAPSZ to the amount of memory available
to safely contain a kernel, device tree and initrd for relocation. The
way to set fdt_high as 0x to disable device tree relocation is
removed.
Signed-off-by: Alison Wang
---
include/configs/ls1021aiot.h | 5
This patch adds watchdog support for Vybrid VF610 platform.
Signed-off-by: Alison Wang
---
Changes in v4:
- Rename mvf600 to vf610
Changes in v3: None
Changes in v2:
- Add watchdog support
- Use reset_cpu() in imx_watchdog.c
drivers/watchdog/Makefile | 2 +-
1 file changed, 1 insertion(+), 1
#x27;
- Use common iomux-v3 code
- Use common FEC driver fec_mxc.c
- Add watchdog support
- Add an entry to MAINTAINERS file
- Rename directory name 'vybird' to 'mvf600twr'
- Use standard method to set gd->ram_size
- Rewrite board_mmc_getcd() function
- Remove useless undef
- R
CONFIG_IOMUX_SHARE_CONFIG_REG was introduced to fit this difference.
Signed-off-by: Alison Wang
---
Changes in v4:
- Rename "MVF600" to "VF610"
- Define PAD_CTL_PUS_47K_UP and PAD_CTL_PUS_100K_UP with PAD_CTL_PUE enabled
- Reorganize the definitions
- Correct the spaces and tabs
Changes in v3:
- Define
This patch adds lpuart support for Vybrid VF610 platform.
Signed-off-by: TsiChung Liew
Signed-off-by: Alison Wang
---
Changes in v4: None
Changes in v3:
- Move the structure definition to imx-regs.h
Changes in v2:
- Define C structures and access C structures to set/read registers
- Change
This patch adds generic codes to support Freescale's Vybrid VF610 CPU.
It aligns Vybrid VF610 platform with i.MX platform. As there are
some differences between VF610 and i.MX platforms, the specific
codes are in the arch/arm/cpu/armv7/vf610 directory.
Signed-off-by: Alison Wang
---
Chang
This patch adds Vybrid VF610 to mxc_ocotp document.
Signed-off-by: Alison Wang
---
Changes in v4: New
Changes in v3: None
Changes in v2: None
doc/README.mxc_ocotp | 1 +
1 file changed, 1 insertion(+)
diff --git a/doc/README.mxc_ocotp b/doc/README.mxc_ocotp
index 9a53311..7a2863c 100644
FEC_RCNTRL_RGMII / FEC_RCNTRL_RMII /
FEC_RCNTRL_MII_MODE bits.
Signed-off-by: Alison Wang
Reviewed-by: Benoit Thebaudeau
---
Changes in v4: None
Changes in v3:
- Remove the changes for FEC_RCNTRL_RGMII / FEC_RCNTRL_RMII /
FEC_RCNTRL_MII_MODE bits, as they are already set in fec_reg_setup()
Changes
VF610TWR is a board based on Vybrid VF610 SoC.
This patch adds basic support for Vybrid VF610TWR board.
Signed-off-by: Alison Wang
Signed-off-by: Jason Jin
Signed-off-by: TsiChung Liew
---
Changes in v4:
- Rename directory name 'mvf600twr' to 'vf610twr'
- Rename mvf60
, this bit is cleared by writing "0".
Signed-off-by: Alison Wang
---
drivers/i2c/mxc_i2c.c | 62 +--
1 file changed, 55 insertions(+), 7 deletions(-)
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index a73b10b..85e3e8b 100644
This patch adds I2C support for Vybrid VF610 platform and adds
I2C0 support to VF610TWR board.
Signed-off-by: Alison Wang
---
arch/arm/cpu/armv7/vf610/generic.c| 7 +++
arch/arm/include/asm/arch-vf610/clock.h | 1 +
arch/arm/include/asm/arch-vf610/crm_regs.h| 1
This series contain the I2C support for Freescale Vybrid VF610 platform and
VF610TWR board.
Alison Wang (2):
vf610: Add I2C support for Vybrid VF610 platform
I2C: mxc_i2c: Add support for Vybrid VF610 platform
arch/arm/cpu/armv7/vf610/generic.c| 7 +++
arch/arm
Add QSPI support for VF610TWR, such as clock and iomux.
Signed-off-by: Alison Wang
Signed-off-by: Chao Fu
---
arch/arm/include/asm/arch-vf610/crm_regs.h| 11 +-
arch/arm/include/asm/arch-vf610/imx-regs.h| 4 +++-
arch/arm/include/asm/arch-vf610/iomux-vf610.h | 14
-programmed
sequences. Each sequence is basically a sequence of instruction-operand pairs
which when executed sequentially generates a valid serial flash transaction.
This driver has been tested on VF610TWR.
Alison Wang (3):
arm: imx
Add PAD_CTL_DSE_150ohm and PAD_CTL_PUS_22K_UP for VF610 in
IOMUX_PAD structure.
Signed-off-by: Alison Wang
---
arch/arm/include/asm/imx-common/iomux-v3.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h
b/arch/arm/include/asm/imx-common/iomux-v3
Add Freescale QSPI driver support for VF610.
Signed-off-by: Alison Wang
Signed-off-by: Chao Fu
---
drivers/spi/Makefile | 1 +
drivers/spi/fsl_qspi.c | 482 +
drivers/spi/fsl_qspi.h | 127 +
3 files changed, 610 insertions
This patch adds generic board support for MCF547X/8X and MCF5445X.
It is based on the patch about common generic board support for
M68K architecture sent by Angelo.
Signed-off-by: Alison Wang
---
common/board_f.c | 8
common/board_r.c | 2 +-
include/asm-generic
For LS102xA, some workarounds are only used in VER1.0, so silicon
version detection are added for QDS and TWR boards.
Signed-off-by: Alison Wang
---
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 3 +
board/freescale/ls1021aqds/ls1021aqds.c | 69 ---
board
On silicon VER1.0, there is an interleaving issue on CCI400
slave interface S2. The workaround is to enable regulation
of outstanding read transactions for slave interface S2.
Signed-off-by: Alison Wang
---
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 ++
board/freescale/ls1021aqds
This series contain the support for Freescale LS102xA SoC and
LS1021AQDS/TWR board.
The QorIQ LS1 family is built on Layerscape architecture, the
industry's first software-aware, core-agnostic networking
architecture to offer unprecedented efficiency and scale.
Freescale LS102xA is a set of SoCs
high
reliability and pack the highest level of integration
available for sub-3 W embedded communications processors
with Layerscape architecture and with a comprehensive
enablement model focused on ease of programmability.
Signed-off-by: Alison Wang
Signed-off-by: Jason Jin
Signed-off-by: Jing
From: Claudiu Manoil
fsl_enet.h defines the mapping of the usual MII management
registers, which are included in the MDIO register block
common to Freescale ethernet controllers. So it shouldn't
depend on the CPU architecture but it should be actually
part of the arch independent fsl_mdio.h.
To
Use mb() instead of sync assembly instruction to be
compatible for both ARM and PowerPC.
Signed-off-by: Alison Wang
---
Change log:
v3: Use mb() to be compatible for both ARM and PowerPC.
Split from the 0004-arm-ls102xa-Add-etsec-support-for-LS102xA patch.
v2: Add private mdio read and
From: York Sun
Reading DDR register should use ddr_in32() for proper endianess.
This patch fixes incorrect waiting time for ARM platforms.
Signed-off-by: York Sun
---
Change log:
v3: No change.
v2: No change.
drivers/ddr/fsl/arm_ddr_gen3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(
For LS102xA, the platform is little endian, while esdhc IP is
big endian. So two macros are added, CONFIG_SYS_FSL_ESDHC_LE
and CONFIG_SYS_FSL_ESDHC_BE, to determine the registers'
reading/writing in big or little endian format.
Signed-off-by: Alison Wang
---
Change log:
v3: No change.
v
Signed-off-by: Alison Wang
---
Change log:
v3: Add I2C 3 support.
v2: No change.
drivers/i2c/mxc_i2c.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index c14797c..83a9ffa 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers
As extra FPGA settings is needed for MDIO read/write
on LS1021AQDS, private MDIO read/write functions are
created.
Signed-off-by: Alison Wang
---
Change log:
v3: Split from the 0004-arm-ls102xa-Add-etsec-support-for-LS102xA patch.
v2: Add private mdio read and write support.
drivers/net
From: York Sun
JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This
is not an issue unless some DQ pins are not connected. If a platform uses
regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on
those floating pins for the second rank. The workaround is to us
For LS102xA, RxBDs and TxBDs are interpreted with little-endian
bytes ordering. The offset for each of eTSECs and MDIOs is
256K bytes.
Signed-off-by: Alison Wang
---
Change log:
v3: No change.
v2: Add private mdio read and write support.
drivers/net/tsec.c | 7 +++
include/tsec.h | 7
From: Claudiu Manoil
Remove the DMCTRL Tx snooping bits (TDSEN and TBDSEN) as a
workaround for LS1. It has been observed that currently
the Tx stops functioning after a fair amount of Tx traffic
with these settings on. These bits are sticky and once set
they cannot be reset from Linux, for inst
From: York Sun
If less than 8 ECC pins are used for DDR data bus width smaller than 64
bits, the 8-bit ECC code will be transmitted/received across several beats,
and it will be used to check 64-bits of data once 8-bits of ECC are
accumulated.
Signed-off-by: York Sun
---
Change log:
v3: No cha
From: Wang Huan
This patch is to add basic support for LS1021AQDS board.
For the detail board information, please refer to README.
Signed-off-by: Alison Wang
Signed-off-by: Jason Jin
Signed-off-by: York Sun
Signed-off-by: Yuan Yao
Signed-off-by: Prabhakar Kushwaha
---
Change log:
v3: Fix
From: Wang Huan
This patch is to add basic support for LS1021ATWR board.
For the detail board information, please refer to README.
Signed-off-by: Chen Lu
Signed-off-by: Yuan Yao
Signed-off-by: Alison Wang
---
Change log:
v3: Fix checkpatch error.
Update to Kconfig.
v2: New file
From: Jingchang Lu
Signed-off-by: Jingchang Lu
Signed-off-by: Yuan Yao
---
Change log:
v3: New file.
drivers/serial/serial_lpuart.c | 122 +
1 file changed, 122 insertions(+)
diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
Signed-off-by: Alison Wang
---
Change log:
v3: New file.
board/freescale/common/Makefile | 2 +
board/freescale/common/dcu_sii9022a.c | 153 ++
board/freescale/common/dcu_sii9022a.h | 13 +++
3 files changed, 168 insertions(+)
create mode 100644 board
From: Wang Huan
This patch is to add DCU driver support. DCU also named
2D-ACE(Two Dimensional Animation and Compositing Engine)
is a system master that fetches graphics stored in internal
or external memory and displays them on a TFT LCD panel.
Signed-off-by: Alison Wang
---
Change log:
v3
From: Wang Huan
This patch is to add LETECH support for LS1021AQDS/TWR board.
For LETECH, LPUART is used for serial port.
Signed-off-by: Jason Jin
Signed-off-by: Yuan Yao
Signed-off-by: Alison Wang
---
Change log:
v3: New file.
board/freescale/ls1021aqds/MAINTAINERS | 1 +
board
From: Wang Huan
Signed-off-by: Alison Wang
---
Change log:
v3: New file.
board/freescale/ls1021atwr/Makefile | 1 +
board/freescale/ls1021atwr/dcu.c| 47 +
board/freescale/ls1021atwr/ls1021atwr.c | 6 +
include/configs/ls1021atwr.h
This patch is to add I2C 1,2,3 support for LS102xA.
Signed-off-by: Alison Wang
---
Change log:
v4: Add commit messages.
v3: Add I2C 3 support.
v2: No change.
drivers/i2c/mxc_i2c.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c
From: Claudiu Manoil
fsl_enet.h defines the mapping of the usual MII management
registers, which are included in the MDIO register block
common to Freescale ethernet controllers. So it shouldn't
depend on the CPU architecture but it should be actually
part of the arch independent fsl_mdio.h.
To
Use mb() instead of sync assembly instruction to be
compatible for both ARM and PowerPC.
Signed-off-by: Alison Wang
---
Change log:
v4: No change.
v3: Use mb() to be compatible for both ARM and PowerPC.
Split from the 0004-arm-ls102xa-Add-etsec-support-for-LS102xA patch.
v2: Add private
For LS102xA, the platform is little endian, while esdhc IP is
big endian. So two macros are added, CONFIG_SYS_FSL_ESDHC_LE
and CONFIG_SYS_FSL_ESDHC_BE, to determine the registers'
reading/writing in big or little endian format.
Signed-off-by: Alison Wang
---
Change log:
v4: No change.
v3
high
reliability and pack the highest level of integration
available for sub-3 W embedded communications processors
with Layerscape architecture and with a comprehensive
enablement model focused on ease of programmability.
Signed-off-by: Alison Wang
Signed-off-by: Jason Jin
Signed-off-by: Jing
This series contain the support for Freescale LS102xA SoC
and LS1021AQDS/TWR board.
The QorIQ LS1 family is built on Layerscape architecture,
the industry's first software-aware, core-agnostic networking
architecture to offer unprecedented efficiency and scale.
Freescale LS102xA is a set of SoCs
From: York Sun
Reading DDR register should use ddr_in32() for proper endianess.
This patch fixes incorrect waiting time for ARM platforms.
Signed-off-by: York Sun
---
Change log:
v4: No change.
v3: No change.
v2: No change.
drivers/ddr/fsl/arm_ddr_gen3.c | 2 +-
1 file changed, 1 insertion
For LS102xA, RxBDs and TxBDs are interpreted with little-endian
bytes ordering. The offset for each of eTSECs and MDIOs is
256K bytes.
Signed-off-by: Alison Wang
---
Change log:
v4: No change.
v3: No change.
v2: Add private mdio read and write support.
drivers/net/tsec.c | 7
From: York Sun
If less than 8 ECC pins are used for DDR data bus width smaller than 64
bits, the 8-bit ECC code will be transmitted/received across several beats,
and it will be used to check 64-bits of data once 8-bits of ECC are
accumulated.
Signed-off-by: York Sun
---
Change log:
v4: No cha
From: York Sun
JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This
is not an issue unless some DQ pins are not connected. If a platform uses
regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on
those floating pins for the second rank. The workaround is to us
From: Jingchang Lu
On vybrid, lpuart's registers are 8-bit. On LS102xA, lpuart's registers
are 32-bit. This patch adds the support for 32-bit registers on
LS102xA.
Signed-off-by: Jingchang Lu
Signed-off-by: Yuan Yao
---
Change log:
v4: Add commit messages.
v3: New file.
drivers/serial/seri
From: Claudiu Manoil
Remove the DMCTRL Tx snooping bits (TDSEN and TBDSEN) as a
workaround for LS1. It has been observed that currently
the Tx stops functioning after a fair amount of Tx traffic
with these settings on. These bits are sticky and once set
they cannot be reset from Linux, for inst
On LS1021ATWR, Silicon's Sii9022A HDMI Transmitter
is used. This patch adds the common setting for this
chip.
Signed-off-by: Alison Wang
---
Change log:
v4: Add commit messages.
v3: New file.
board/freescale/common/Makefile | 2 +
board/freescale/common/dcu_sii9022a.c
From: Wang Huan
LS102xA is an ARMv7 implementation. This patch is to add
basic support for LS1021AQDS board.
One DDR controller
DUART1 is used as the console
For the detail board information, please refer to README.
Signed-off-by: Alison Wang
Signed-off-by: Jason Jin
Signed-off-by: York
From: Wang Huan
This patch is to add DCU driver support. DCU also named
2D-ACE(Two Dimensional Animation and Compositing Engine)
is a system master that fetches graphics stored in internal
or external memory and displays them on a TFT LCD panel.
Signed-off-by: Alison Wang
---
Change log:
v4
From: Wang Huan
LS102xA is an ARMv7 implementation. This patch is to add
basic support for LS1021ATWR board.
One DDR controller
DUART1 is used as the console
For the detail board information, please refer to README.
Signed-off-by: Chen Lu
Signed-off-by: Yuan Yao
Signed-off-by: Alison Wang
As extra FPGA settings is needed for MDIO read/write
on LS1021AQDS, private MDIO read/write functions are
created.
Signed-off-by: Alison Wang
---
Change log:
v4: No change.
v3: Split from the 0004-arm-ls102xa-Add-etsec-support-for-LS102xA patch.
v2: Add private mdio read and write support
From: Wang Huan
This patch is to add LETECH support for LS1021AQDS/TWR board.
For LETECH, lpuart is used as console.
Signed-off-by: Jason Jin
Signed-off-by: Yuan Yao
Signed-off-by: Alison Wang
---
Change log:
v4: No change.
v3: New file.
board/freescale/ls1021aqds/MAINTAINERS | 1
From: Wang Huan
This patch adds the TWR_LCD_RGB card/HDMI options and the common
configuration for DCU on LS1021ATWR board.
Signed-off-by: Alison Wang
---
Change log:
v4: Add commit messages.
v3: New file.
board/freescale/ls1021atwr/Makefile | 1 +
board/freescale/ls1021atwr/dcu.c
Use mb() instead of sync assembly instruction to be
compatible for both ARM and PowerPC.
Signed-off-by: Alison Wang
---
Change log:
v5: No change.
v4: No change.
v3: Use mb() to be compatible for both ARM and PowerPC.
Split from the 0004-arm-ls102xa-Add-etsec-support-for-LS102xA patch
The existing i.MX's I2C driver mxc_i2c.c is compatible
with the controller of LS102xA. As I2C's registers
are 8-bit on LS102xA, I2C_QUIRK_REG is enabled to
use 8-bit driver.
This patch is to add I2C 1,2,3 support for LS102xA.
Signed-off-by: Alison Wang
---
Change log:
v5: Add detai
This series contain the support for Freescale LS102xA SoC and
LS1021AQDS/TWR board.
The QorIQ LS1 family is built on Layerscape architecture, the
industry's first software-aware, core-agnostic networking
architecture to offer unprecedented efficiency and scale.
Freescale LS102xA is a set of SoCs
For LS102xA, RxBDs and TxBDs are interpreted with little-endian
bytes ordering. The offset for each of eTSECs and MDIOs is
256K bytes.
Signed-off-by: Alison Wang
---
Change log:
v5: No change.
v4: No change.
v3: No change.
v2: Add private mdio read and write support.
drivers/net/tsec.c | 7
From: York Sun
If less than 8 ECC pins are used for DDR data bus width smaller than 64
bits, the 8-bit ECC code will be transmitted/received across several beats,
and it will be used to check 64-bits of data once 8-bits of ECC are
accumulated.
Signed-off-by: York Sun
---
Change log:
v5: No cha
For LS102xA, the platform is little endian, while esdhc IP is
big endian. So two macros are added, CONFIG_SYS_FSL_ESDHC_LE
and CONFIG_SYS_FSL_ESDHC_BE, to determine the registers'
reading/writing in big or little endian format.
Signed-off-by: Alison Wang
---
Change log:
v5: No change.
v
From: York Sun
Reading DDR register should use ddr_in32() for proper endianess.
This patch fixes incorrect waiting time for ARM platforms.
Signed-off-by: York Sun
---
Change log:
v5: No change.
v4: No change.
v3: No change.
v2: No change.
drivers/ddr/fsl/arm_ddr_gen3.c | 2 +-
1 file chan
From: Claudiu Manoil
fsl_enet.h defines the mapping of the usual MII management
registers, which are included in the MDIO register block
common to Freescale ethernet controllers. So it shouldn't
depend on the CPU architecture but it should be actually
part of the arch independent fsl_mdio.h.
To
From: York Sun
JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This
is not an issue unless some DQ pins are not connected. If a platform uses
regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on
those floating pins for the second rank. The workaround is to us
From: Wang Huan
LS102xA is an ARMv7 implementation. This patch is to add
basic support for LS1021AQDS board.
One DDR controller
DUART1 is used as the console
For the detail board information, please refer to README.
Signed-off-by: Alison Wang
Signed-off-by: Jason Jin
Signed-off-by: York
From: Jingchang Lu
On vybrid, lpuart's registers are 8-bit. On LS102xA, lpuart's registers
are 32-bit. This patch adds the support for 32-bit registers on
LS102xA.
Signed-off-by: Jingchang Lu
Signed-off-by: Yuan Yao
---
Change log:
v5: No change.
v4: Add commit messages.
v3: New file.
dri
From: Claudiu Manoil
Remove the DMCTRL Tx snooping bits (TDSEN and TBDSEN) as a
workaround for LS1. It has been observed that currently
the Tx stops functioning after a fair amount of Tx traffic
with these settings on. These bits are sticky and once set
they cannot be reset from Linux, for inst
high
reliability and pack the highest level of integration
available for sub-3 W embedded communications processors
with Layerscape architecture and with a comprehensive
enablement model focused on ease of programmability.
Signed-off-by: Alison Wang
Signed-off-by: Jason Jin
Signed-off-by: Jing
From: Wang Huan
LS102xA is an ARMv7 implementation. This patch is to add
basic support for LS1021ATWR board.
One DDR controller
DUART1 is used as the console
For the detail board information, please refer to README.
Signed-off-by: Chen Lu
Signed-off-by: Yuan Yao
Signed-off-by: Alison Wang
From: Wang Huan
This patch is to add DCU driver support. DCU also named
2D-ACE(Two Dimensional Animation and Compositing Engine)
is a system master that fetches graphics stored in internal
or external memory and displays them on a TFT LCD panel.
Signed-off-by: Alison Wang
---
Change log:
v5
From: Wang Huan
This patch adds the TWR_LCD_RGB card/HDMI options and the common
configuration for DCU on LS1021ATWR board.
Signed-off-by: Alison Wang
---
Change log:
v5: Change the patch order.
v4: Add commit messages.
v3: New file.
board/freescale/ls1021atwr/Makefile | 1 +
board
On LS1021ATWR, Silicon's Sii9022A HDMI Transmitter
is used. This patch adds the common setting for this
chip.
Signed-off-by: Alison Wang
---
Change log:
v5: Change the patch order.
v4: Add commit messages.
v3: New file.
board/freescale/common/Makefile | 2 +
board/freescale/c
of U-Boot for NOR boot is
adjusted to 0x6010.
In RCW, the PBI command needs to change as follows:
.pbi
-write 0xee0200, 0x67f8
+write 0xee0200, 0x6010
.end
Signed-off-by: Alison Wang
---
include/configs/ls1021aqds.h | 2 +-
include/configs/ls1021atwr.h | 2 +-
2 files chang
This series contain the support for Freescale LS102xA SoC and LS1021AQDS/TWR
board.
The QorIQ LS1 family is built on Layerscape architecture, the industry's first
software-aware, core-agnostic networking architecture to offer unprecedented
efficiency and scale.
Freescale LS102xA is a set of SoCs
This patch is to add etsec support for LS102xA. First, Little-endian
descriptor mode should be enabled. So RxBDs and TxBDs are interpreted
with little-endian byte ordering. Second, TSEC_SIZE and TSEC_MDIO_OFFSET
are different from PowerPC, redefine them for LS1021xA.
Signed-off-by: Alison Wang
From: Claudiu Manoil
fsl_enet.h defines the mapping of the usual MII management
registers, which are included in the MDIO register block
common to Freescale ethernet controllers. So it shouldn't
depend on the CPU architecture but it should be actually
part of the arch independent fsl_mdio.h.
To
Use mb() instead of sync assembly instruction to be
compatible for both ARM and PowerPC.
Signed-off-by: Alison Wang
---
Change log:
v6: Fix checkpatch error.
v5: No change.
v4: No change.
v3: Use mb() to be compatible for both ARM and PowerPC.
Split from the 0004-arm-ls102xa-Add-etsec
high
reliability and pack the highest level of integration
available for sub-3 W embedded communications processors
with Layerscape architecture and with a comprehensive
enablement model focused on ease of programmability.
Signed-off-by: Alison Wang
Signed-off-by: Jason Jin
Signed-off-by: Jing
From: Wang Huan
For LS102xA, the processor is in little-endian mode, while esdhc IP is
in big-endian mode. CONFIG_SYS_FSL_ESDHC_LE and CONFIG_SYS_FSL_ESDHC_BE
are added. So accessing ESDHC registers can be determined by ESDHC IP's
endian mode.
Signed-off-by: Alison Wang
---
Change log
From: York Sun
JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This
is not an issue unless some DQ pins are not connected. If a platform uses
regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on
those floating pins for the second rank. The workaround is to us
From: Wang Huan
The existing i.MX's I2C driver mxc_i2c.c is compatible
with the controller of LS102xA. As I2C's registers
are 8-bit on LS102xA, I2C_QUIRK_REG is enabled to
use 8-bit driver.
This patch is to add I2C 1,2,3 support for LS102xA.
Signed-off-by: Alison Wang
---
Change log
From: York Sun
Reading DDR register should use ddr_in32() for proper endianess.
This patch fixes incorrect waiting time for ARM platforms.
Signed-off-by: York Sun
---
Change log:
v6: No change.
v5: No change.
v4: No change.
v3: No change.
v2: No change.
drivers/ddr/fsl/arm_ddr_gen3.c | 2
From: York Sun
If less than 8 ECC pins are used for DDR data bus width smaller than 64
bits, the 8-bit ECC code will be transmitted/received across several beats,
and it will be used to check 64-bits of data once 8-bits of ECC are
accumulated.
Signed-off-by: York Sun
---
Change log:
v6: No cha
From: Claudiu Manoil
Remove the DMCTRL Tx snooping bits (TDSEN and TBDSEN) as a
workaround for LS1. It has been observed that currently
the Tx stops functioning after a fair amount of Tx traffic
with these settings on. These bits are sticky and once set
they cannot be reset from Linux, for inst
From: Jingchang Lu
On vybrid, lpuart's registers are 8-bit. On LS102xA, lpuart's registers
are 32-bit. This patch adds the support for 32-bit registers on
LS102xA.
Signed-off-by: Jingchang Lu
Signed-off-by: Yuan Yao
---
Change log:
v6: Fix the influence to other board.
v5: No change.
v4: Ad
-by: Alison Wang
---
Change log:
v6: Make the commit more clear.
Split from the v5' 06 patch.
v5: No change.
v4: No change.
v3: Add commit messages.
v2: No change.
drivers/mmc/fsl_esdhc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/fsl_esdh
From: Wang Huan
LS102xA is an ARMv7 implementation. This patch is to add
basic support for LS1021AQDS board.
One DDR controller
DUART1 is used as the console
For the detail board information, please refer to README.
Signed-off-by: Alison Wang
Signed-off-by: Jason Jin
Signed-off-by: York
From: Wang Huan
LS102xA is an ARMv7 implementation. This patch is to add
basic support for LS1021ATWR board.
One DDR controller
DUART1 is used as the console
For the detail board information, please refer to README.
Signed-off-by: Chen Lu
Signed-off-by: Yuan Yao
Signed-off-by: Alison Wang
From: Wang Huan
On LS1021ATWR, Silicon's Sii9022A HDMI Transmitter
is used. This patch adds the common setting for this
chip.
Signed-off-by: Alison Wang
---
Change log:
v6: No change.
v5: Change the patch order.
v4: Add commit messages.
v3: New file.
board/freescale/common/Mak
From: Wang Huan
This patch is to add DCU driver support. DCU also named
2D-ACE(Two Dimensional Animation and Compositing Engine)
is a system master that fetches graphics stored in internal
or external memory and displays them on a TFT LCD panel.
Signed-off-by: Alison Wang
---
Change log:
v6
From: Wang Huan
This patch adds the TWR_LCD_RGB card/HDMI options and the common
configuration for DCU on LS1021ATWR board.
Signed-off-by: Alison Wang
---
Change log:
v6: Use #define instead of magic numbers.
v5: Change the patch order.
v4: Add commit messages.
v3: New file.
board
From: Wang Huan
The existing i.MX's I2C driver mxc_i2c.c is compatible
with the controller of LS102xA. As I2C's registers
are 8-bit on LS102xA, I2C_QUIRK_REG is enabled to
use 8-bit driver.
This patch is to add I2C 1,2,3 support for LS102xA.
Signed-off-by: Alison Wang
---
Change log
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