čt 23. 6. 2022 v 13:04 odesílatel Michal Simek napsal:
>
> Enable SquashFS for all xilinx platforms.
>
> Signed-off-by: Michal Simek
> ---
>
> configs/xilinx_versal_virt_defconfig | 1 +
> configs/xilinx_zynq_virt_defconfig | 1 +
> configs/xilinx_zynqmp_virt_defconfig | 1 +
> 3 files changed
>
> We only reference CONFIG_SYS_BFTIC3_BASE in one location. Move the
> comment to where we reference it, and use the value directly.
>
> Cc: Holger Brunck
> Cc: Heiko Schocher
> Signed-off-by: Tom Rini
> ---
> board/keymile/km83xx/km83xx.c | 6 --
> include/configs/kmcoge5ne.h | 6 --
čt 23. 6. 2022 v 13:08 odesílatel Michal Simek napsal:
>
> Add SPL_REGMAP dependency when SPL is enabled. This can avoid compilation
> issues if timer is selected but SPL_REGMAP not.
>
> Reported-by: Ovidiu Panait
> Signed-off-by: Michal Simek
> ---
>
> drivers/timer/Kconfig | 1 +
> 1 file cha
On Mon, 27 Jun 2022 at 07:12, Cédric Le Goater wrote:
>
> Hello Chiawei,
>
> On 6/27/22 02:39, ChiaWei Wang wrote:
> > Reply again to leave record on mailing list.
Sorry, I re-sent it to get it on the list and managed to miss that for
the second time.
> >
> >> From: joel.s...@gmail.com On Behal
Hello,
Am Dienstag, 30. November 2021, 17:06:11 CEST schrieb Alexander Dahl:
> Am Thu, Oct 21, 2021 at 11:33:04AM +0200 schrieb Pali Rohár:
> > kwbimage depends on libcrypto. 32-bit mvebu platforms (except Orion and
> > Discovery, which are not in mach-mvebu) require kwimage for building SPL.
> >
The Aspeed AST2600 is modelled in Qemu. This makes some configuration
changes so it can be added to CI.
It has a depednency on the u-boot-test-hooks patches I sent here:
https://lore.kernel.org/u-boot/20220624023420.3925916-1-j...@jms.id.au
I've given it a run on Azure and the tests passed.
Jo
Allows loading one u-boot from another. Useful for testing on hardware.
Signed-off-by: Joel Stanley
---
configs/evb-ast2600_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig
index 53ba36a28374..f3a6cb222020 100644
--- a/co
For the u-boot-with-spl.bin target to be useful for the AST2600, set the
maximum SPL size which also sets the padding length.
The normal way of loading u-boot is as a FIT, so configure u-boot.img as
the SPL playload.
With this the following simple steps can be used to build and boot a
system:
The AST2600 has a Qemu model that allows testing. Create a SPI NOR image
containing the combined SPL and u-boot FIT image.
Signed-off-by: Joel Stanley
---
.azure-pipelines.yml | 3 +++
.gitlab-ci.yml | 6 ++
2 files changed, 9 insertions(+)
diff --git a/.azure-pipelines.yml b/.azure-p
The HACE driver lacks support for all the hash types, causing boot to
fail with the default FIT configuration which uses CRC32.
Additionally the Qemu model or the u-boot driver is unable to correctly
compute the SHA256 hash used in a FIT.
Disable HACE by default while the above issues are worked
Useful for testing images with the default hash type.
Signed-off-by: Joel Stanley
---
configs/evb-ast2600_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig
index f84b723bbba3..53ba36a28374 100644
--- a/configs/evb-ast2600_
On Monday 27 June 2022 09:53:22 Alexander Dahl wrote:
> After migrating some boards from u-boot v2021.10 to v2022.01 I found this is
> still an issue. Build for example at91 board fails if CONFIG_TOOLS_LIBCRYPTO
> is disabled and build host has no openssl headers installed.
> (Error output bel
Reviewed-by: Chia-Wei Wang
> From: joel.s...@gmail.com On Behalf Of Joel Stanley
> Sent: Monday, June 27, 2022 3:58 PM
>
> Allows loading one u-boot from another. Useful for testing on hardware.
>
> Signed-off-by: Joel Stanley
> ---
> configs/evb-ast2600_defconfig | 1 +
> 1 file changed, 1
Reviewed-by: Chia-Wei Wang
> From: joel.s...@gmail.com On Behalf Of Joel Stanley
> Sent: Monday, June 27, 2022 3:58 PM
>
> Useful for testing images with the default hash type.
>
> Signed-off-by: Joel Stanley
> ---
> configs/evb-ast2600_defconfig | 1 +
> 1 file changed, 1 insertion(+)
>
>
Reviewed-by: Chia-Wei Wang
The QEMU emulation issue is under investigation by Steven.
The CRC32 and MD5 SW support will be added before we re-enabling HW crypto
drivers.
Chiawei
> From: joel.s...@gmail.com On Behalf Of Joel Stanley
> Sent: Monday, June 27, 2022 3:58 PM
>
> The HACE driver la
> From: joel.s...@gmail.com On Behalf Of Joel Stanley
> Sent: Monday, June 27, 2022 3:58 PM
>
> For the u-boot-with-spl.bin target to be useful for the AST2600, set the
> maximum SPL size which also sets the padding length.
>
> The normal way of loading u-boot is as a FIT, so configure u-boot.im
On Sun, Jun 26, 2022 at 2:02 AM Daniel Golle wrote:
>
> On Sat, Jun 25, 2022 at 10:10:08AM +0200, Kegl Rohit wrote:
> > Hello!
> >
> > Is it possible to store the environment inside a mtd partition when
> > using a single qspi nand chip as storage?
> > CONFIG_MTD_SPI_NAND=y
> >
> > The idea is to
Reviewed-by: Chia-Wei Wang
> From: joel.s...@gmail.com On Behalf Of Joel Stanley
> Sent: Monday, June 27, 2022 3:58 PM
>
> The AST2600 has a Qemu model that allows testing. Create a SPI NOR image
> containing the combined SPL and u-boot FIT image.
>
> Signed-off-by: Joel Stanley
> ---
> .azu
On Tue, 21 Jun 2022, Lee Jones wrote:
> Functions pointed to by this op pointer can return non-zero values
> indicating an error. Ensure any error value is propagated back up the
> call-chain.
>
> Signed-off-by: Lee Jones
> ---
> drivers/ram/rockchip/sdram_rk3399.c | 4 +++-
> 1 file changed,
On Mon, 2022-06-27 at 06:55 +0200, Heinrich Schuchardt wrote:
> On 6/27/22 05:43, Su, Bao Cheng wrote:
> > On Fri, 2022-06-24 at 11:44 +0200, Jan Kiszka wrote:
> > > On 24.06.22 10:53, Heinrich Schuchardt wrote:
> > > > On 6/24/22 07:32, Su, Bao Cheng wrote:
> > > > > During PE hashing, when holes
Timing macro's are wrong for MMC_HS_52 and MMC_DDR_52. Fix it with
correct values of MMC_TIMING_MMC_HS and MMC_TIMING_MMC_DDR52 respectively.
Signed-off-by: Ashok Reddy Soma
---
drivers/mmc/zynq_sdhci.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/zynq_sdh
On Fri, 2022-06-24 at 11:44 +0200, Jan Kiszka wrote:
> On 24.06.22 10:53, Heinrich Schuchardt wrote:
> > On 6/24/22 07:32, Su, Bao Cheng wrote:
> > > During PE hashing, when holes exists between sections, the extra
> > > data
> > > calculated could be a dupulicated region of the last section.
> > >
Hello Chiawei,
On 6/27/22 02:39, ChiaWei Wang wrote:
Reply again to leave record on mailing list.
From: joel.s...@gmail.com On Behalf Of Joel Stanley
Sent: Friday, June 24, 2022 10:50 AM
The Qemu model or the u-boot driver is unable to correctly compute the
SHA256 hash used in a FIT. Disable
On 6/27/22 09:58, Joel Stanley wrote:
Useful for testing images with the default hash type.
Signed-off-by: Joel Stanley
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
configs/evb-ast2600_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/evb-ast2600_defconfig b/config
On 6/27/22 09:58, Joel Stanley wrote:
Allows loading one u-boot from another. Useful for testing on hardware.
Signed-off-by: Joel Stanley
---
Reviewed-by: Cédric Le Goater
Thanks,
C.
configs/evb-ast2600_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/evb-ast2600
On 6/27/22 09:58, Joel Stanley wrote:
The HACE driver lacks support for all the hash types, causing boot to
fail with the default FIT configuration which uses CRC32.
Additionally the Qemu model or the u-boot driver is unable to correctly
compute the SHA256 hash used in a FIT.
Disable HACE by de
On 6/27/22 10:15, ChiaWei Wang wrote:
Reviewed-by: Chia-Wei Wang
The QEMU emulation issue is under investigation by Steven.
Great ! I was going to open a gitlab issue under :
https://gitlab.com/qemu-project/qemu/-/issues/
But we still have a couple of weeks before QEMU 7.1 soft freeze :
On 6/27/22 09:58, Joel Stanley wrote:
For the u-boot-with-spl.bin target to be useful for the AST2600, set the
maximum SPL size which also sets the padding length.
The normal way of loading u-boot is as a FIT, so configure u-boot.img as
the SPL playload.
With this the following simple steps can
On 6/27/22 09:58, Joel Stanley wrote:
The AST2600 has a Qemu model that allows testing. Create a SPI NOR image
containing the combined SPL and u-boot FIT image.
Signed-off-by: Joel Stanley
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
.azure-pipelines.yml | 3 +++
.gitlab-ci.yml
Hi Joel,
I was wondering if you could share the commit hash of u-boot you tested.
I would like to test it on qemu.
Thanks,
Steven
* Email Confidentiality Notice
DISCLAIMER:
This message (and any attachments) may contain legally privileged and/or other
confidenti
Hi,
I'm having some difficulty configuring U-Boot, in particular setting it up so
that it can load from an SD card,
but access its Environment from QSPI Flash.
First of all, is this even possible? Can the U-Boot environment be stored in a
different location from where
U-Boot was loaded?
Curre
> Reviewed-by: Chia-Wei Wang
>
> The QEMU emulation issue is under investigation by Steven.
> The CRC32 and MD5 SW support will be added before we re-enabling HW
> crypto drivers.
>
> Chiawei
>
> > From: joel.s...@gmail.com On Behalf Of Joel
> > Stanley
> > Sent: Monday, June 27, 2022 3:58 PM
Hi Peng,
Am 27.06.22 um 05:41 schrieb Peng Fan (OSS):
> From: Peng Fan
>
> V7:
> Rebased with follwoing patchset applied.
> [1] i.MX93 patchset:
> https://patchwork.ozlabs.org/project/uboot/cover/20220627032455.28280-1-peng@oss.nxp.com/
> [2] binman symbols fix:
> https://patchwork.ozla
Hello Neal
On 6/27/22 10:55, Neal Liu wrote:
Reviewed-by: Chia-Wei Wang
The QEMU emulation issue is under investigation by Steven.
The CRC32 and MD5 SW support will be added before we re-enabling HW
crypto drivers.
Chiawei
From: joel.s...@gmail.com On Behalf Of Joel
Stanley
Sent: Monday, J
> Subject: Re: [PATCH V7 0/4] arm64: binman: use binman symbols for imx
>
> Hi Peng,
>
> Am 27.06.22 um 05:41 schrieb Peng Fan (OSS):
> > From: Peng Fan
> >
> > V7:
> > Rebased with follwoing patchset applied.
> > [1] i.MX93 patchset:
> > https://eur01.safelinks.protection.outlook.com/?url=htt
On Mon, 27 Jun 2022 at 08:55, Neal Liu wrote:
>
> > Reviewed-by: Chia-Wei Wang
> >
> > The QEMU emulation issue is under investigation by Steven.
> > The CRC32 and MD5 SW support will be added before we re-enabling HW
> > crypto drivers.
> >
> > Chiawei
> >
> > > From: joel.s...@gmail.com On Beh
On 6/27/22 07:30, Jim Liu wrote:
Hi Marek
Hello all,
Thanks for your reply.
The answer is yes.
Our customer Dell is using our driver now.
so need upstream uboot source to uboot master.
All right, so this Dell device is also going to be upstreamed then ?
If the driver is just going to be up
> Hello Neal
>
> On 6/27/22 10:55, Neal Liu wrote:
> >> Reviewed-by: Chia-Wei Wang
> >>
> >> The QEMU emulation issue is under investigation by Steven.
> >> The CRC32 and MD5 SW support will be added before we re-enabling HW
> >> crypto drivers.
> >>
> >> Chiawei
> >>
> >>> From: joel.s...@gmail.
Hi Tom,
please pull the following patches to your next branch.
There are a lot of changes especially with Microblaze and having an option to
disable MANUAL RELOC.
Gitlab CI doesn't show any issue.
And there is merge conflict with your next branch (Kconfig layout change) which
is easy to reso
Hi,
On 6/27/22 05:01, David Antliff wrote:
Hi,
I'm having some difficulty configuring U-Boot, in particular setting it up so
that it can load from an SD card,
but access its Environment from QSPI Flash.
First of all, is this even possible? Can the U-Boot environment be stored in a
different
Hello Marek,
On Fri, 24 Jun 2022 20:12:31 +0200
Marek Vasut wrote:
> On 6/22/22 10:59, kory.mainc...@bootlin.com wrote:
> > From: Kory Maincent
> >
> > For now the driver does not probe if usbkbd was not present in stdin.
> > This presents two issues, we can not probe the driver before setting
On Mon, 27 Jun 2022 at 08:48, Steven Lee wrote:
>
> Hi Joel,
>
> I was wondering if you could share the commit hash of u-boot you tested.
> I would like to test it on qemu.
I recommend using master with the patch that fixes FIT hash checking:
https://lore.kernel.org/r/20220620070117.3443066-1-j.
A crafted squashfs image could embed a huge number of empty metadata
blocks in order to make the amount of malloc()'d memory overflow and be
much smaller than expected. Because of this flaw, any random code
positioned at the right location in the squashfs image could be memcpy'd
from the squashfs s
The UEFI console initialisation has been modified by commit 68edbed454b8
("efi_loader: initialize console size late"). A corresponding workaround is
now necessary for the automated tests, as added to some of the tests
already by commit e05bd68ed5fc ("test: work around for EFI terminal size
probing"
On 6/27/22 12:23, Vincent Stehlé wrote:
The UEFI console initialisation has been modified by commit 68edbed454b8
("efi_loader: initialize console size late"). A corresponding workaround is
now necessary for the automated tests, as added to some of the tests
already by commit e05bd68ed5fc ("test:
From: Frieder Schrempf
LDO5 has two separate control registers. LDO5CTRL_L is used if the
input signal SD_VSEL is low and LDO5CTRL_H if it is high.
The current driver implementation only uses LDO5CTRL_H. To make this
work on boards that have SD_VSEL connected to a GPIO, we add support
for specify
From: Frieder Schrempf
Currently accessing the SD card on USDHC2 fails with:
=> mmc dev 1
Card did not respond to voltage select! : -110
This is due to the fact that UHS modes are enabled in the defconfig
and the devicetree, but the referenced LDO5 regulator (reg_nvcc_sd)
is not available to sw
On 6/27/22 12:03, Köry Maincent wrote:
Hello Marek,
On Fri, 24 Jun 2022 20:12:31 +0200
Marek Vasut wrote:
On 6/22/22 10:59, kory.mainc...@bootlin.com wrote:
From: Kory Maincent
For now the driver does not probe if usbkbd was not present in stdin.
This presents two issues, we can not probe
On Mon, 27 Jun 2022 13:39:03 +0200
Marek Vasut wrote:
> >> Can you document the usecase in a bit more detail ?
> >
> > My usecase is to get a key press from the USB keyboard and do some thing
> > about it in board_init. I do not want to multiplex the keyboard input to
> > stdin but I still wan
Am 18.06.22 um 14:13 schrieb Alper Nebi Yasak:
> There's some trouble with an i.MX8M series [1] trying to use binman
> symbols. The crux of it is the 'u_boot_any' symbols BINMAN_SYMBOLS
> configs declare, and the boards creating partial binman images including
> an SPL without a U-Boot the symbol i
On 6/24/22 07:32, Su, Bao Cheng wrote:
During PE hashing, when holes exists between sections, the extra data
calculated could be a dupulicated region of the last section.
Such PE image with holes existing between sections may contain the
symbol table for the kernel, for example.
The Authenticod
Move the current CodingStyle wiki page to doc/develop/codingstyle.rst.
The changes here are for formatting or slight rewording so that it reads
well when linking to other sphinx documents.
Signed-off-by: Tom Rini
---
doc/develop/codingstyle.rst | 211
doc/dev
For some time now we've allowed for '//' style comments, which mirrors
the Linux kernel. So drop this point here.
Signed-off-by: Tom Rini
---
doc/develop/codingstyle.rst | 5 -
1 file changed, 5 deletions(-)
diff --git a/doc/develop/codingstyle.rst b/doc/develop/codingstyle.rst
index a41ae
Move the current Process wiki page to doc/develop/process.rst. The
changes here are for formatting or slight rewording so that it reads
well when linking to other sphinx documents.
Signed-off-by: Tom Rini
---
doc/develop/index.rst | 1 +
doc/develop/process.rst | 182 +++
Move the current DesignPrinciples wiki page to
doc/develop/designprinciples.rst. The changes here are for formatting
or slight rewording so that it reads well when linking to other sphinx
documents.
Signed-off-by: Tom Rini
---
doc/develop/designprinciples.rst | 197 +
Hey all,
As you might have seen, the DENX wiki has undergone some updates in the
last few months. As of now, most pages have been restored and are up to
date. But it's also true that the wiki long predates our sphinx
documentation and readthedocs site (which I am very happy the work has
been put
On Mon, Jun 27, 2022 at 11:50:48AM +0200, Michal Simek wrote:
> Hi Tom,
>
> please pull the following patches to your next branch.
> There are a lot of changes especially with Microblaze and having an option
> to disable MANUAL RELOC.
>
> Gitlab CI doesn't show any issue.
>
> And there is merge
We have a single platform that is both in the OMAP3 family of parts, but
has an EMIF4 memory controller. Currently we hard-code the size of
chip select 0. Make this more clear by putting the value in the
function rather than a CONFIG option.
Signed-off-by: Tom Rini
---
arch/arm/mach-omap2/omap
Perform a basic migration of the calls in setup_serial_number() to DM so
that we can switch to using DM_I2C on this platform.
Cc: David Lechner
Signed-off-by: Tom Rini
---
board/lego/ev3/legoev3.c | 15 +--
configs/legoev3_defconfig | 2 +-
2 files changed, 14 insertions(+), 3 del
As the migration deadline has passed, and all platforms have been
migrated, remove the non-DM code here.
Signed-off-by: Tom Rini
---
arch/arm/mach-keystone/ddr3_spd.c| 13
drivers/i2c/Kconfig | 4 +-
drivers/i2c/davinci_i2c.c| 97 ---
This converts the following to Kconfig:
CONFIG_SYS_CACHE_STASHING
Signed-off-by: Tom Rini
---
arch/powerpc/cpu/mpc85xx/Kconfig | 3 +++
configs/P2041RDB_NAND_defconfig | 1 +
configs/P2041RDB_SDCARD_defconfig | 1 +
configs/P2041RDB_SPIFLASH_defconfig | 1 +
c
On p1_p2_rdb_pc platforms, we set ddr_data_init to the "poison" value of
0xdeadbeef rather than a real calculated / derived value. Do this
directly and comment rather than via CONFIG.
Signed-off-by: Tom Rini
---
board/freescale/corenet_ds/p4080ds_ddr.c | 1 -
board/freescale/p1_p2_rdb_pc/ddr.c
There are no platforms using this architecture anymore, remove it.
Signed-off-by: Tom Rini
---
arch/arm/Kconfig|7 -
arch/arm/Makefile |2 -
arch/arm/cpu/sa1100/Makefile|9 -
arch/arm/cpu/sa1100/cpu.c
On Mon, Jun 27, 2022 at 06:33:01AM +0200, Heiko Schocher wrote:
> Hello Nicolas,
>
> On 21.06.22 16:04, Nicolas IOOSS wrote:
> > Hello,
> >
> > I sent some days ago the vulnerability fix below. I have not received any
> > reply yet. Could a maintainer take a look at it, please?
>
> Sorry for th
On Wed, Jun 01, 2022 at 08:26:27PM +0200, Loic Poulain wrote:
> Mark sha1_process as weak to allow hardware specific implementation.
> Add parameter to support for multiple blocks processing.
>
> Signed-off-by: Loic Poulain
Applied to u-boot/next, thanks!
--
Tom
signature.asc
Description: P
On Wed, Jun 01, 2022 at 08:26:28PM +0200, Loic Poulain wrote:
> sha1 digest size is 5*32-bit => 160-bit. Using 64-bit unsigned long
> does not cause issue with the current sha1 implementation, but could
> be problematic for vectorized access.
>
> Signed-off-by: Loic Poulain
Applied to u-boot/ne
On Wed, Jun 01, 2022 at 08:26:29PM +0200, Loic Poulain wrote:
> This patch adds support for the SHA-1 Secure Hash Algorithm for CPUs
> that have support for the SHA-1 part of the ARM v8 Crypto Extensions.
>
> It greatly improves sha-1 based operations, about 10x faster on iMX8M
> evk board. ~12ms
On Wed, Jun 01, 2022 at 08:26:30PM +0200, Loic Poulain wrote:
> Mark sha256_process as weak to allow hardware specific implementation.
> Add parameter for supporting multiple blocks processing.
>
> Signed-off-by: Loic Poulain
Applied to u-boot/next, thanks!
--
Tom
signature.asc
Description:
On Wed, Jun 01, 2022 at 08:26:31PM +0200, Loic Poulain wrote:
> This patch adds support for the SHA-256 Secure Hash Algorithm for CPUs
> that have support for the SHA-256 part of the ARM v8 Crypto Extensions.
>
> It greatly improves sha-256 based operations, about 17x faster on iMX8M
> evk board.
On Thu, Jun 23, 2022 at 03:51:31PM -0400, Tom Rini wrote:
> Now that we can make use of CPU features for sha1/sha256, enable in QEMU
> so that we get some test coverage.
>
> Cc: Loic Poulain
> Cc: Tuomas Tynkkynen
> Signed-off-by: Tom Rini
Applied to u-boot/next, thanks!
--
Tom
signature.
>
> From: Michal Simek
> Sent: 27 June 2022 22:03
> To: David Antliff; u-boot@lists.denx.de
> Subject: Re: Issue with booting U-Boot from SD card, but using QSPI Flash for
> its Environment
>
> Hi,
>
> On 6/27/22 05:01, David Antliff wrote:
> > Hi,
> >
> >
On Thu, 9 Jun 2022 17:09:39 +0800
qianfangui...@163.com wrote:
Hi Qianfan,
> From: qianfan Zhao
>
> dm_spi_claim_bus run spi_set_speed_mode first and then ops->claim_bus,
> but spi clock is enabled when sun4i_spi_claim_bus, that will make
> sun4i_spi_set_speed doesn't work.
Thanks for bringin
On Mon, 9 May 2022 00:29:36 -0500
Samuel Holland wrote:
> The reason here is the same as the reason for changing the clock driver:
> platform data can be provided when binding the driver.
Yes, that's right. Confirmed to be almost completely s/priv/plat/.
> Signed-off-by: Samuel Holland
Revie
On Tue, 3 May 2022 22:20:35 +0100
Andre Przywara wrote:
Hi,
> As George rightfully pointed out [1], the spi-sunxi driver programs the
> speed and mode settings only when the respective functions are called,
> but this gets lost over a call to release_bus(). That asserts the
> reset line, thus f
On Mon, 9 May 2022 00:29:30 -0500
Samuel Holland wrote:
Hi Samuel,
> This series fixes an issue with out-of-bounds access to the gate array
> (patches 1-2), uses the rearranged array size information to remove a
> bunch of duplicate code (patches 3-4), and then simplifies how the reset
> driver
On Mon, 9 May 2022 00:29:35 -0500
Samuel Holland wrote:
> All of the driver private data should really be platform data since it
> is determined statically (selected by the compatible string or extracted
> from the devicetree). Move everything to platform data, so it can be
> provided when bindi
On Mon, 9 May 2022 00:29:37 -0500
Samuel Holland wrote:
Hi,
> The clock and reset drivers use the exact same platform data. Simplify
> them by sharing the object. This is safe because the parent device
> (the clock device) always gets its driver model callbacks run first.
>
> Signed-off-by: Sa
> On Mon, 27 Jun 2022 at 08:55, Neal Liu wrote:
> >
> > > Reviewed-by: Chia-Wei Wang
> > >
> > > The QEMU emulation issue is under investigation by Steven.
> > > The CRC32 and MD5 SW support will be added before we re-enabling HW
> > > crypto drivers.
> > >
> > > Chiawei
> > >
> > > > From: joel.
Hi Andre,
On 6/27/22 7:40 PM, Andre Przywara wrote:
> On Mon, 9 May 2022 00:29:30 -0500
> Samuel Holland wrote:
>
> Hi Samuel,
>
>> This series fixes an issue with out-of-bounds access to the gate array
>> (patches 1-2), uses the rearranged array size information to remove a
>> bunch of duplic
On 6/27/22 20:31, Andre Przywara wrote:
On Tue, 3 May 2022 22:20:35 +0100
Andre Przywara wrote:
Hi,
As George rightfully pointed out [1], the spi-sunxi driver programs the
speed and mode settings only when the respective functions are called,
but this gets lost over a call to release_bus(
Hi Marek
Thank you for your reminder.
Dell is use novuton uboot git repo now.
and request us upstream it.
npcm7xx normal defconfig is poleg_evb_defconfig, so all people use
this config to build uboot.
and poleg_evb_defconfig is in uboot master now.
I separate all the drivers to several commits,a
Hi Chai Wei,
On Wed, 1 Jun 2022 at 08:21, Chia-Wei Wang wrote:
>
> The commit b583348ca8c8 ("image: fit: Align hash output buffers") places
> the hash output buffer at the .bss section. However, AST2600 by default
> executes SPL in the NOR flash XIP way. This results in the hash output
> cannot b
The commit 99e2fbcb69f0 ("linker_lists: Rename sections to remove .
prefix") changed the name of the linker list sections. As the Aspeed SPL
linker wasn't in the tree yet, it missed the change.
This updates the SPL linker to match arch/arm/cpu/u-boot-spl.lds which
Aspeed was copied from.
Fixes: 4
Hi Chai,
On 6/28/22 12:23 AM, Joel Stanley wrote:
Hi Chai Wei,
On Wed, 1 Jun 2022 at 08:21, Chia-Wei Wang wrote:
The commit b583348ca8c8 ("image: fit: Align hash output buffers") places
the hash output buffer at the .bss section. However, AST2600 by default
executes SPL in the NOR flash XIP
Heinrich,
On Mon, Jun 27, 2022 at 12:46:07PM +0200, Heinrich Schuchardt wrote:
> On 6/27/22 12:23, Vincent Stehlé wrote:
> > The UEFI console initialisation has been modified by commit 68edbed454b8
> > ("efi_loader: initialize console size late"). A corresponding workaround is
> > now necessary fo
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