On Sat, 2020-12-12 at 08:39 -0700, Simon Glass wrote:
> Hi Nicolas,
>
> On Thu, 10 Dec 2020 at 04:39, Nicolas Saenz Julienne
> wrote:
> >
> > Add the following functions to get a specific device's DMA ranges:
> > - dev_get_dma_range()
> > - ofnode_get_dma_range()
> > - of_get_dma_range()
> >
Hi,
This driver is connected via spi on one ZynqMP board. Only 8bit SPI
connection is supported now. Spi zynq driver was used for testing this
driver.
We have tested load image via BMP command and also using it as console as
is visible from log in the last patch.
Thanks,
Michal
Changes in v2:
-
Place description below function parameters to make kernel-doc stript
happy. Also rename dev to vid to be aligned with function parameters.
Fixes: 1acafc73bfc7 ("dm: video: Add a video uclass")
Signed-off-by: Michal Simek
---
Changes in v2:
- New patch is series
./scripts/kernel-doc -v -man inc
This patch is preparation for follow up one to support cases where
synchronization can fail.
Suggested-by: Simon Glass
Signed-off-by: Michal Simek
---
Changes in v2:
- New patch is series
drivers/video/vidconsole-uclass.c | 40 ++-
drivers/video/video-uclass.c
Some drivers like LCD connected via SPI requires explicit sync function
which copy framebuffer content over SPI to controller to display.
This hook doesn't exist yet that's why introduce it via video operations.
Signed-off-by: Michal Simek
---
Changes in v2:
- Add support for returning value
- U
Add support for the WiseChip Semiconductor Inc. (UG-6028GDEBF02) display
using the SEPS525 (Syncoam) LCD Controller. Syncoam Seps525 PM-Oled is RGB
160x128 display. This driver has been tested through zynq-spi driver.
ZynqMP> load mmc 1 10 rainbow.bmp
61562 bytes read in 20 ms (2.9 MiB/s)
Zynq
From: Vikhyat Goyal
Added dt binding for seps525 display driver.
Signed-off-by: Vikhyat Goyal
Signed-off-by: Michal Simek
Reviewed-by: Simon Glass
---
(no changes since v1)
MAINTAINERS | 1 +
.../video/syncoam,seps525.txt | 24
Hi Simon,
On 12. 12. 20 16:35, Simon Glass wrote:
> Hi Michal,
>
> On Thu, 3 Dec 2020 at 02:13, Michal Simek wrote:
>>
>> Some drivers like LCD connected via SPI requires explicit sync function
>> which copy framebuffer content over SPI to controller to display.
>> This hook doesn't exist yet th
Hi,
Thanks for sending the patch.
Please fix subject line.
I am missing commit message and your SOB line.
Also below it looks like it is not sent by git send-email.
On 08. 12. 20 1:32, Alessandro Temil wrote:
> diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c
> index
Hi,
On 12/12/20 4:46 PM, grygorii tertychnyi wrote:
> To implement dual-boot strategy we need to know what is the current
> boot partition for U-Boot. It can be easily identified by looking at
> the PARTITION_CONFIG value shown by "mmc partconf dev", but I didn't
> find any way to use it in the bo
It's confused what is optional or mandantary argument.
Update the command's usage to clarify how to use.
Signed-off-by: Jaehoon Chung
---
cmd/mmc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/cmd/mmc.c b/cmd/mmc.c
index 1529a3e05ddd..cb6b59f36a43 100644
--- a/cmd/mm
The driver skips hardware initialization if it is already configured by
the earlier bootloader stage (BL30). Skip the initialization only if the
hardware is really initialized and enabled.
Signed-off-by: Marek Szyprowski
Change-Id: I3e2e2d270ad3e7e7f38e2bc3ce2a924a47b164af
---
drivers/adc/meson-
Save examined button state in 'button' environment variable to enable
checking button state in the scripts.
Signed-off-by: Marek Szyprowski
Change-Id: I78b539e1516573fcfea4401f75469291844daae4
---
cmd/button.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/cmd/button.c b/
Add options required to check the 'Function' button state.
Signed-off-by: Marek Szyprowski
---
configs/khadas-vim3_defconfig | 4
1 file changed, 4 insertions(+)
diff --git a/configs/khadas-vim3_defconfig b/configs/khadas-vim3_defconfig
index 9d7ba72d440..bc174305692 100644
--- a/configs/k
Add minimal driver AO clocks on meson G12A family. Only ADC related clocks
are supported.
Signed-off-by: Marek Szyprowski
Change-Id: I0c91848bc55493e19570db333e7da6020d687907
---
drivers/clk/meson/Makefile | 1 +
drivers/clk/meson/g12a-ao.c | 83 +
2 files c
Hi All,
This patchset adds all building blocks needed for checking the 'Function'
button state in the boot script on Amlogic A311D based VIM3 board. This
button is connected to the ADC lines of the SoC, so it required to enable
meson SARADC, the clocks needed for it and a simple button-adc drivers
Add a simple ADC-based button driver. This driver binds to the 'adc-keys'
device tree node.
Signed-off-by: Marek Szyprowski
Change-Id: I6da7101eff3ce53766d899f49f5839d728d52fb3
---
drivers/button/Kconfig | 8 +++
drivers/button/Makefile | 1 +
drivers/button/button-adc.c | 117 +
Add support for the SARADC variant found on the G12A SoCs family.
Signed-off-by: Marek Szyprowski
Change-Id: If519d333e9773d089f37a8c7b4ccb144be68925b
---
drivers/adc/meson-saradc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/adc/meson-saradc.c b/drivers/adc/meson-saradc.c
inde
dwc3_meson_g12a_force_mode() sets the dr-mode of the USB PHY. However
it skips setting the mode if it matches the one done during driver probe
(stored in private structure). This fails if the mode has been changed
to other value and then back to initial one. Fix this by configuring the
dr-mode alwa
On 08/12/2020 11:08, Pali Rohár wrote:
Hello! I looked at what is initialized and enabled for sd/emmc slots and
I found out that comphy mmc needs to be enabled if at least one slot is
used (e.g. SD card) and then remaining part is slot initialization in
xenon driver.
I wrote quick patch to disab
On 13/12/2020 10:08, Amit Singh Tomar wrote:
> From: Amit Singh Tomar
>
> This commit adds support for MMC controllers found on Actions OWL
> S700 SoC platform.
>
> Signed-off-by: Amit Singh Tomar
> ---
> drivers/mmc/Kconfig | 7 +
> drivers/mmc/Makefile | 1 +
> drivers/mmc/owl_mmc.c |
Hi Jaehoon
Thanks for having a look and providing the comments
Order to the bit number.
Ok, Sure
>
> > +
> > +#define OWL_MMC_OCR (MMC_VDD_32_33 | MMC_VDD_33_34
> | \
> > + MMC_VDD_165_195)
> > +
> > +#define DATA_TRANSFER_TIMEOUT
Hi Jaehoon,
thanks for replying.
On Mon, Dec 14, 2020 at 10:58 AM Jaehoon Chung wrote:
>
> Hi,
>
> On 12/12/20 4:46 PM, grygorii tertychnyi wrote:
> > To implement dual-boot strategy we need to know what is the current
> > boot partition for U-Boot. It can be easily identified by looking at
> > t
Hi,
You could pass a pointer to owl_mmc_priv here, which can hold both those
> values. See below for more more on this.
>
> Did you mean for argument 3rd and 4th but then in that case how one could
have differentiated
between source and destination.
for instance 3rd and 4th arguments are differe
dma_addr_t holds any valid DMA address. If the DMA API only uses 32/64-bit
addresses, dma_addr_t need only be 32/64 bits wide.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
---
arch/riscv/Kconfig | 4
arch/riscv/include/asm/types.h | 4
2 files changed, 8 insertio
This patch set adds Microchip PolarFire SoC Icicle Kit support
to RISC-V U-Boot.
The patches are based upon latest U-Boot tree
(https://gitlab.denx.de/u-boot/u-boot.git) at commit id
5a1a8a63be8f7262a300eddafb18020926b12fb6
All drivers namely: NS16550 Serial, Microchip clock,
Cadence eMMC and Cad
Enable 32-bit or 64-bit DMA in the macb driver based on the macb
hardware compatibility and it is configured with structure macb_config
in the driver.
The Microchip PolarFire SoC Memory Protection Unit(MPU) gives the 64-bit
DMA access with the GEM, the MPU transactions on the AXI bus is 64-bit
not
Read phy address from device tree and use it to find the phy device
if not found then search in the range of 0 to 31.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
drivers/net/macb.c | 13 +
1 file changed, 13 insertions(+)
d
Add clock driver code for the Microchip PolarFire SoC. This driver
handles reset and clock control of the Microchip PolarFire SoC device.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
---
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile
Add device tree for Microchip PolarFire SoC Icicle Kit.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
Reviewed-by: Bin Meng
---
arch/riscv/dts/Makefile | 1 +
.../dts/microchip-mpfs-icicle-kit-u-boot.dtsi | 14 +
arch/riscv/dts/microchip-mpfs-icicle-kit.dts |
This patch adds Microchip MPFS Icicle Kit support. For now, only
NS16550 Serial, Microchip clock, Cadence eMMC and MACB drivers are
enabled. The Microchip MPFS Icicle defconfig by default builds
U-Boot for S-Mode because U-Boot on Microchip PolarFire SoC will run
in S-Mode as payload of HSS + OpenS
This doc describes the procedure to build, flash and
boot Linux using U-boot on Microchip MPFS Icicle Kit.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
---
doc/board/index.rst | 1 +
doc/board/microchip/index.rst | 9 +
doc/board/microchip/mpfs_icicle.rst | 8
Hi,
Thanks for having the detailed look and providing comments:
> According to the datasheet the clock source could also be NAND_PLL,
> depending on bit 9.
> Both PLLs use the same rate calculation, so it's just matter of the PLL
> address offset to use for covering both.
Ok, should I change the
Hi,
On Mon, Dec 14, 2020 at 6:45 AM André Przywara wrote:
>
> On 13/12/2020 09:43, Amit Singh Tomar wrote:
> > This commit introduces get/set_rate callbacks, these are dummy at
> > the moment, and can be used to get/set clock for various devices
> > based on the clk id.
> >
> > Signed-off-by: Ami
Hi Otto,
On Mon, Dec 7, 2020 at 1:43 PM Otto Meier wrote:
[...]
> >> So with the latest u-boot and the kernel from
> >> https://github.com/chewitt/linux/tree/amlogic-5.10.y
> >> commit 725fc8df7898102f9031ba2075f763884ffa3ee8 everything is working
> >> again.
> >> USB does hotplugging as expect
Hello all. Having strange issues when using mkenvimage tool. I have generated
uEnv.txt with three variables defined: var1, var2 and var3. And I am trying to
load it into U-boot. I have done two different tests:
Test1 (null-terminated strings)
OUT=uEnv.txt
echo -ne "var1=1\0" > $OUT
echo -ne "va
On 14/12/2020 14:12, Amit Tomer wrote:
> Hi,
>
> Thanks for having the detailed look and providing comments:
>
>> According to the datasheet the clock source could also be NAND_PLL,
>> depending on bit 9.
>> Both PLLs use the same rate calculation, so it's just matter of the PLL
>> address offset
On 14/12/2020 15:02, Amit Tomar wrote:
> Hi,
>
> You could pass a pointer to owl_mmc_priv here, which can hold both those
>
> values. See below for more more on this.
>
> Did you mean for argument 3rd and 4th but then in that case how one
> could have differentiated
> between source and dest
Hi Heinrich,
I see this failure here:
https://gitlab.denx.de/u-boot/custodians/u-boot-dm/-/jobs/189275
Do you have any ideas?
Regards,
Simon
Hi Chris,
On Sat, 12 Dec 2020 at 11:51, Chris Packham wrote:
>
>
>
> On Sun, 13 Dec 2020, 4:44 AM Simon Glass, wrote:
>>
>> Hi Joseph,
>>
>> On Tue, 8 Dec 2020 at 00:32, Joseph Liu wrote:
>> >
>> > From: Joseph Liu
>> >
>> > If DM_I2C is used, the command "i2c dev" will not reassign
>> > gd->c
Hi Tom,
https://gitlab.denx.de/u-boot/custodians/u-boot-dm/-/pipelines/5567
Note this is for the 'next' tree.
It includes the rename series which would be good to get in early.
Regards,
Simon
The following changes since commit ddaa94978583d07ec515e7226e397221d8cc44c8:
Merge tag 'efi-next'
From: Matthias Brugger
Add support for random number generator RNG200.
This is for example found on RPi4.
Signed-off-by: Matthias Brugger
---
drivers/rng/Kconfig| 6 ++
drivers/rng/Makefile | 1 +
drivers/rng/iproc_rng200.c | 186 +
3 file
From: Matthias Brugger
We find the iProc RNG200 in the Raspberry Pi 4. Add it to all it's
config so that it can be used.
Signed-off-by: Matthias Brugger
---
configs/rpi_4_32b_defconfig | 1 +
configs/rpi_4_defconfig | 1 +
configs/rpi_arm64_defconfig | 1 +
drivers/rng/iproc_rng200.c |
Hello,
Does U-Boot can be built and run as a Legacy BIOS payload, like
GRUB or SeaBios?
Indeed GRUB or SeaBios have a stage 1 binary to be merge in GPT/MBR partition
table. I did not find something like that with U-Boot.
I do not want to use U-Boot with UEFI, I have already done it.
I saw U-boot c
On 14.12.20 17:24, matthias@kernel.org wrote:
> From: Matthias Brugger
>
> We find the iProc RNG200 in the Raspberry Pi 4. Add it to all it's
> config so that it can be used.
>
> Signed-off-by: Matthias Brugger
After applying this patch series to origin/next ddaa9497858
make configs/rpi
This patchset fixes spi_claim_bus() handling of the speed/mode settings
when multiple spi slaves claim the bus consecutively, as reported here:
https://lists.denx.de/pipermail/u-boot/2019-December/393854.html
https://lists.denx.de/pipermail/u-boot/2020-November/431554.html
It also does some minor
Commit 1289e96797bf ("sandbox: spi: Drop command-line SPI option") dropped
support for specifying SPI devices on the command line, removing the only
user of sandbox_spi_parse_spec(). Remove the function too.
Fixes: 1289e96797bf ("sandbox: spi: Drop command-line SPI option")
Signed-off-by: Ovidiu P
Implement sandbox_spi_set_{speed, mode} routines, to be able to keep track
of the current bus speed/mode. This will help determine whether the values
passed from dm_spi_claim_bus() are valid.
Signed-off-by: Ovidiu Panait
---
Changes in v2:
- none
drivers/spi/sandbox_spi.c | 26
Place a second spi slave on the sandbox_spi bus, to be used by the
spi_claim_bus() testcase we are about to introduce. We need to make sure
that jumping between slaves calling spi_claim_bus() sets the bus speed and
mode appropriately. Use different max-hz and mode properties for this new
slave.
Al
Introduce sandbox_spi_get_{speed, mode} public interface to retrieve the
sandbox spi bus internal state. They are meant to be used in sandbox spi
testcases.
Signed-off-by: Ovidiu Panait
Reviewed-by: Simon Glass
---
Changes in v2:
- add reviewed-by tag
arch/sandbox/include/asm/test.h | 16
Currently, when different spi slaves claim the bus consecutively using
spi_claim_bus(), spi_set_speed_mode() will only be executed on the first
two calls, leaving the bus in a bad state starting with the third call.
This patch drops spi_slave->speed member and adds caching of bus
speed/mode in dm_
Add testcase for spi_claim_bus(), which checks that sandbox spi bus
speed/mode settings are updated correctly when multiple slaves use
the bus consecutively. The following configurations are used for the
two spi slaves involved:
* different max_hz / different modes
* different max_hz / same mod
On 14.12.20 17:24, matthias@kernel.org wrote:
> From: Matthias Brugger
>
> Add support for random number generator RNG200.
> This is for example found on RPi4.
>
> Signed-off-by: Matthias Brugger
> ---
>
> drivers/rng/Kconfig| 6 ++
> drivers/rng/Makefile | 1 +
> drivers/r
Hello Heiko,
I hope you are doing well, just curious if you have had a chance to look into
my latest response?
Regards,
-Cooper Duffin
Hello Heiko,
I hope you are doing well, just curious if you have had a chance to look into
my latest response?
Regards,
-Cooper Duffin
-Original Messa
On 14.12.20 18:03, Heinrich Schuchardt wrote:
> On 14.12.20 17:24, matthias@kernel.org wrote:
>> From: Matthias Brugger
>>
>> We find the iProc RNG200 in the Raspberry Pi 4. Add it to all it's
>> config so that it can be used.
>>
>> Signed-off-by: Matthias Brugger
>
> After applying this patc
On 23.10.20 02:29, Tom Rini wrote:
> On Thu, Oct 08, 2020 at 10:05:13PM +0200, Robert Marko wrote:
>> Add support for the hardware pseudo random number generator found in
>> Qualcomm SoC-s.
>
>>
>> Signed-off-by: Robert Marko
>> Cc: Luka Perkov
>
> Applied to u-boot/master, thanks!
>
Hello Robe
On Mon, Dec 14, 2020 at 6:22 PM Heinrich Schuchardt
wrote:
> On 23.10.20 02:29, Tom Rini wrote:
> > On Thu, Oct 08, 2020 at 10:05:13PM +0200, Robert Marko wrote:
> >> Add support for the hardware pseudo random number generator found in
> Qualcomm SoC-s.
> >
> >>
> >> Signed-off-by: Robert Marko
After the conversion to device tree the board information becomes
redundant:
Model: Freescale i.MX6 Quad Plus SABRE Smart Device Board
Board: MX6-SabreSD
Remove the printing of the board information.
Signed-off-by: Fabio Estevam
---
board/freescale/mx6sabresd/mx6sabresd.c | 6 --
1 file ch
This fixes the wrong usage of clrsetbits_le32(), badly setting the set argument.
Fixes: c4c726c26b ("pinctrl: meson: add pinconf support")
Reported-by: Anton Arapov
Reported-by: Otto Meier
Signed-off-by: Neil Armstrong
---
Hi Anton, Otto,
This should fix eMMC booting on Odroid-C2, could you ha
Hi,
On 14/12/2020 12:34, Marek Szyprowski wrote:
> dwc3_meson_g12a_force_mode() sets the dr-mode of the USB PHY. However
> it skips setting the mode if it matches the one done during driver probe
> (stored in private structure). This fails if the mode has been changed
> to other value and then bac
Hi,
On 14/12/2020 12:24, Marek Szyprowski wrote:
> Add minimal driver AO clocks on meson G12A family. Only ADC related clocks
> are supported.
>
> Signed-off-by: Marek Szyprowski
> Change-Id: I0c91848bc55493e19570db333e7da6020d687907
Please drop the Change-Ids
> ---
> drivers/clk/meson/Makefi
On 14/12/2020 12:24, Marek Szyprowski wrote:
> Add support for the SARADC variant found on the G12A SoCs family.
>
> Signed-off-by: Marek Szyprowski
> Change-Id: If519d333e9773d089f37a8c7b4ccb144be68925b
Ditto
> ---
> drivers/adc/meson-saradc.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> di
On 14/12/2020 12:24, Marek Szyprowski wrote:
> The driver skips hardware initialization if it is already configured by
> the earlier bootloader stage (BL30). Skip the initialization only if the
> hardware is really initialized and enabled.
>
> Signed-off-by: Marek Szyprowski
> Change-Id: I3e2e2d2
Hi,
On 14/12/2020 12:24, Marek Szyprowski wrote:
> Add options required to check the 'Function' button state.
>
> Signed-off-by: Marek Szyprowski
> ---
> configs/khadas-vim3_defconfig | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/configs/khadas-vim3_defconfig b/configs/khadas-vi
Hi,
On 07/12/2020 18:15, Stefan Agner wrote:
> Amlogic AGX SoCs seem to have issue communicating with some eMMC
> devices (in particular with a Micron 128GB eMMC 5.1). The device
> is detected with 1-bit bus width, and at higher temperature loading
> pretty much anything from the storage fails: (e
Hi Martin,
Am 13.12.20 um 19:46 schrieb Martin Blumenstingl:
Hi Otto,
On Mon, Dec 7, 2020 at 1:43 PM Otto Meier wrote:
[...]
So with the latest u-boot and the kernel from
https://github.com/chewitt/linux/tree/amlogic-5.10.y
commit 725fc8df7898102f9031ba2075f763884ffa3ee8 everything is workin
Hi Neil,
On 14.12.2020 19:55, Neil Armstrong wrote:
> On 14/12/2020 12:24, Marek Szyprowski wrote:
>> Add options required to check the 'Function' button state.
>>
>> Signed-off-by: Marek Szyprowski
>> ---
>> configs/khadas-vim3_defconfig | 4
>> 1 file changed, 4 insertions(+)
>>
>> diff
Hi Neil,
I tested it and it does fix the issue. I am able to boot from eMMC.
Thanks a lot!
Anton
On Mon, Dec 14, 2020 at 7:48 PM Neil Armstrong wrote:
>
> This fixes the wrong usage of clrsetbits_le32(), badly setting the set
> argument.
>
> Fixes: c4c726c26b ("pinctrl: meson: add pinconf supp
On Fri, Dec 11, 2020 at 3:27 PM Bin Meng wrote:
>
> Hi Padmarao,
>
> On Fri, Dec 11, 2020 at 8:07 PM Padmarao Begari wrote:
> >
> > Hi Bin,
> >
> > On Fri, Dec 11, 2020 at 2:59 PM Bin Meng wrote:
> >>
> >> Hi Padmarao,
> >>
> >> On Fri, Dec 11, 2020 at 4:49 PM Padmarao Begari
> >> wrote:
> >>
On Fri, Nov 27, 2020 at 11:45 PM Harm Berntsen wrote:
>
> When the tftp server did not send any OACK, the tftp_next_ack variable
> was not set to the correct value . As the server was transmitting
> blocks we generated a lot of 'Received unexpected block: $n, expected
> $n+1' error messages. Depen
On 12/14/20 11:45 PM, gr embeter wrote:
> Hi Jaehoon,
> thanks for replying.
>
> On Mon, Dec 14, 2020 at 10:58 AM Jaehoon Chung wrote:
>>
>> Hi,
>>
>> On 12/12/20 4:46 PM, grygorii tertychnyi wrote:
>>> To implement dual-boot strategy we need to know what is the current
>>> boot partition for U-B
On 12/15/20 3:53 AM, Neil Armstrong wrote:
> Hi,
>
> On 14/12/2020 12:24, Marek Szyprowski wrote:
>> Add minimal driver AO clocks on meson G12A family. Only ADC related clocks
>> are supported.
>>
>> Signed-off-by: Marek Szyprowski
>> Change-Id: I0c91848bc55493e19570db333e7da6020d687907
>
> Plea
On 12/15/20 3:54 AM, Neil Armstrong wrote:
> On 14/12/2020 12:24, Marek Szyprowski wrote:
>> Add support for the SARADC variant found on the G12A SoCs family.
>>
>> Signed-off-by: Marek Szyprowski
>> Change-Id: If519d333e9773d089f37a8c7b4ccb144be68925b
>
> Ditto
>
>> ---
>> drivers/adc/meson-sa
On 12/15/20 3:54 AM, Neil Armstrong wrote:
> On 14/12/2020 12:24, Marek Szyprowski wrote:
>> The driver skips hardware initialization if it is already configured by
>> the earlier bootloader stage (BL30). Skip the initialization only if the
>> hardware is really initialized and enabled.
>>
>> Signe
On 12/15/20 3:55 AM, Neil Armstrong wrote:
> Hi,
>
> On 14/12/2020 12:24, Marek Szyprowski wrote:
>> Add options required to check the 'Function' button state.
>>
>> Signed-off-by: Marek Szyprowski
Tested-by: Jaehoon Chung
Reviewed-by: Jaehoon Chung
>> ---
>> configs/khadas-vim3_defconfig |
Am 14. Dezember 2020 16:49:36 MEZ schrieb Simon Glass :
>Hi Heinrich,
>
>I see this failure here:
>
>https://gitlab.denx.de/u-boot/custodians/u-boot-dm/-/jobs/189275
Command
bootefi selftest
did not create output.
Try to run that command in QEMU for the board and git bisect.
Sorry it is alread
Hi Heinrich,
On Mon, 14 Dec 2020 at 15:03, Heinrich Schuchardt wrote:
>
> Am 14. Dezember 2020 16:49:36 MEZ schrieb Simon Glass :
> >Hi Heinrich,
> >
> >I see this failure here:
> >
> >https://gitlab.denx.de/u-boot/custodians/u-boot-dm/-/jobs/189275
>
> Command
>
> bootefi selftest
>
> did not cr
Here are some further cleanups for the GE Bx50v3 board(s):
PATCH 1+2: cleanup preprocessor usage in common/image-fit.c,
introduced after feedback from Simon Glass in PATCHv1
PATCH 3+4: replace magic numbers by analyzing name string from
the fitImage config node
PATCH 5: rel
Add a host_build() function, so that it's possible to
check for software being build with USE_HOSTCC without
relying on preprocessor conditions. In other words
#ifdef USE_HOSTCC
host_only_code();
#endif
can be written like this instead:
if (host_build())
host_only_code();
Thi
Support reusing board_fit_config_name_match() to automatically
select a sensible default configuration for booting fitImages
using 'bootm'.
Signed-off-by: Sebastian Reichel
---
common/image-fit.c | 19 +--
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/common/imag
Instead of hardcoding index magic numbers in the board code,
also rely on board_fit_config_name_match choosing the right
config for the fitImage containing the kernel.
Signed-off-by: Sebastian Reichel
---
board/ge/bx50v3/bx50v3.c| 16 ++--
include/configs/ge_bx50v3.h | 4 ++--
2
The current PHY rework does the following things:
1. Configure 125MHz clock
2. Setup the TX clock delay (RX is enabled by default),
3. Setup reserved bits to avoid voltage peak
The clock delays are nowadays already configured by the
PHY driver (in ar803x_delay_config). The code for that
can simpl
Replace most #ifdef checks for USE_HOSTCC and CONFIG_*
with normal if instructions.
Signed-off-by: Sebastian Reichel
---
common/image-fit.c | 193 +
include/image.h| 4 +
2 files changed, 96 insertions(+), 101 deletions(-)
diff --git a/common/im
On Mon, Dec 14, 2020 at 03:38:44PM +0800, ub...@andestech.com wrote:
> Hi Tom,
>
> Please pull some riscv updates:
>
> - Fix wrong amoswap t1 usage in startup.
> - Reset the board after cratch.
> - Enable distro booting from an attached SCSI disk for QEMU.
> - Support the optional header fields
> Subject: [PATCH] mx6sabresd: Remove unneeded checkboard()
>
> After the conversion to device tree the board information becomes
> redundant:
>
> Model: Freescale i.MX6 Quad Plus SABRE Smart Device Board
> Board: MX6-SabreSD
>
> Remove the printing of the board information.
>
> Signed-off-by:
Hi Michal,
On Mon, 14 Dec 2020 at 01:39, Michal Simek wrote:
>
> Hi Simon,
>
> On 12. 12. 20 16:35, Simon Glass wrote:
> > Hi Michal,
> >
> > On Thu, 3 Dec 2020 at 02:13, Michal Simek wrote:
> >>
> >> Some drivers like LCD connected via SPI requires explicit sync function
> >> which copy framebu
Hi Michal,
On Mon, 14 Dec 2020 at 00:30, Michal Simek wrote:
>
>
>
> On 12. 12. 20 16:35, Simon Glass wrote:
> > Hi Michal,
> >
> > On Thu, 3 Dec 2020 at 02:13, Michal Simek wrote:
> >>
> >> Add support for the WiseChip Semiconductor Inc. (UG-6028GDEBF02) display
> >> using the SEPS525 (Syncoam)
Hi Sughosh,
On Sun, 13 Dec 2020 at 23:23, Sughosh Ganu wrote:
>
> The fsp_types.h header file contains macros for building signatures of
> different widths. These signature macros are architecture agnostic,
> and can be used in all places which use signatures in a data
> structure. Move and renam
On Mon, 14 Dec 2020 at 01:38, Michal Simek wrote:
>
> Place description below function parameters to make kernel-doc stript
> happy. Also rename dev to vid to be aligned with function parameters.
>
> Fixes: 1acafc73bfc7 ("dm: video: Add a video uclass")
> Signed-off-by: Michal Simek
> ---
>
> Cha
On Mon, 14 Dec 2020 at 01:38, Michal Simek wrote:
>
> This patch is preparation for follow up one to support cases where
> synchronization can fail.
>
> Suggested-by: Simon Glass
> Signed-off-by: Michal Simek
>
> ---
>
> Changes in v2:
> - New patch is series
>
> drivers/video/vidconsole-uclass
On Mon, 14 Dec 2020 at 01:38, Michal Simek wrote:
>
> Some drivers like LCD connected via SPI requires explicit sync function
> which copy framebuffer content over SPI to controller to display.
> This hook doesn't exist yet that's why introduce it via video operations.
>
> Signed-off-by: Michal Si
On Sun, 13 Dec 2020 at 06:14, Heinrich Schuchardt wrote:
>
> On x86 the global data pointer is stored in register fs.
> On x86_64 no register is used for the global data pointer.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> doc/develop/global_data.rst | 4 +++-
> 1 file changed, 3 insertions(+
On Sat, 12 Dec 2020 at 01:41, Heinrich Schuchardt wrote:
>
> Convert README.NetConsole to reStructured text and move it to
> doc/usage/netconsole.rst.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> doc/README.NetConsole| 97 --
> doc/usage/netconsole.rst | 10
Hi Jaehoon,
On Mon, 14 Dec 2020 at 03:09, Jaehoon Chung wrote:
>
> It's confused what is optional or mandantary argument.
how about: It's confusing whether arguments are optional or mandatory
> Update the command's usage to clarify how to use.
Are you using <> to indicate optional? I see [] us
Hi Simon,
On 12/15/20 1:00 PM, Simon Glass wrote:
> Hi Jaehoon,
>
> On Mon, 14 Dec 2020 at 03:09, Jaehoon Chung wrote:
>>
>> It's confused what is optional or mandantary argument.
>
> how about: It's confusing whether arguments are optional or mandatory
Okay, will update.
>
>> Update the com
Hi Michael,
On Sat, 12 Dec 2020 at 11:38, Simon Glass wrote:
>
> Hi Michael,
>
> On Sat, 12 Dec 2020 at 10:53, Michael Walle wrote:
> >
> > Hi Simon,
> >
> > Am 2020-12-12 16:39, schrieb Simon Glass:
> > >> Sequence numbers looks good, but PCI still doesnt work on my board.
> > >
> > > Thanks fo
Hi Jaehoon,
On Mon, 14 Dec 2020 at 21:17, Jaehoon Chung wrote:
>
> Hi Simon,
>
> On 12/15/20 1:00 PM, Simon Glass wrote:
> > Hi Jaehoon,
> >
> > On Mon, 14 Dec 2020 at 03:09, Jaehoon Chung wrote:
> >>
> >> It's confused what is optional or mandantary argument.
> >
> > how about: It's confusing w
Hi,
On 12/15/20 3:58 AM, Neil Armstrong wrote:
> Hi,
>
> On 07/12/2020 18:15, Stefan Agner wrote:
>> Amlogic AGX SoCs seem to have issue communicating with some eMMC
>> devices (in particular with a Micron 128GB eMMC 5.1). The device
>> is detected with 1-bit bus width, and at higher temperature
hi Simon,
On Tue, 15 Dec 2020 at 09:25, Simon Glass wrote:
> Hi Sughosh,
>
> On Sun, 13 Dec 2020 at 23:23, Sughosh Ganu
> wrote:
> >
> > The fsp_types.h header file contains macros for building signatures of
> > different widths. These signature macros are architecture agnostic,
> > and can be
Hello Duffin,
Am 14.12.20 um 18:12 schrieb Duffin, CooperX:
> Hello Heiko,
>
> I hope you are doing well, just curious if you have had a chance to look into
> my latest response?
Yep, thanks all fine, just to much workload ... and seems
I forgot to response
>
> Regards,
>
> -Cooper Duffi
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