Enable uart overrun feature which allows to benefits of uart
FIFO usage.
Previously overrun management was disabled, this has to effect
to bypassed the uart FIFO usage even if FIFO was enabled.
In particular configuration, for example when video console is
enabled, copy/pasting a long command line
Uart status register is named USART_ISR on STM32F7, STM32H7
and STM32MP1 SoCs family, but USART_SR only on STM32F4 SoCs.
Use USART_ISR_ prefix instead of USART_SR_ .
Signed-off-by: Patrice Chotard
---
drivers/serial/serial_stm32.c | 10 +-
drivers/serial/serial_stm32.h | 6 +++---
2 f
Hi Alex,
On 19.4.2018 18:48, Alexander Graf wrote:
> On 04/18/2018 03:11 PM, Michal Simek wrote:
>> Xilinx ZynqMP also contains dual Cortex R5 which can run U-Boot.
>> This patch is adding minimal support to get U-Boot boot.
>> DDR needs to be partitioned. Console is done via Cadence uart driver a
On Thu, 2018-04-19 at 05:02 +0200, Marek Vasut wrote:
> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
> >
> > Add the base address map for Statix10 SoC
> >
> > Signed-off-by: Chin Liang See
> > Signed-off-by: Ley Foon Tan
> > ---
> > arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 38
> >
From: Nitin Jain
This patch used for filling the MMU map for DDR at run time based
information read from Device Tree or automatically detected from static
configuration.
Signed-off-by: Nitin Jain
Signed-off-by: Siva Durga Prasad Paladugu
Signed-off-by: Michal Simek
---
arch/arm/cpu/armv8/zy
On Thu, Apr 19, 2018 at 4:19 PM, Marek Vasut wrote:
> On 04/19/2018 07:15 AM, See, Chin Liang wrote:
>> On Thu, 2018-04-19 at 04:47 +0200, Marek Vasut wrote:
>>> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
Add CONFIG_SYS_L2_PL310 conditional build.
>>> Why ?
>>>
>>
>> In ARM64, L2 cache
Hi Ezequiel,
On 19.4.2018 17:16, Ezequiel Garcia wrote:
> Hi Michal,
>
> On 19 April 2018 at 08:10, Michal Simek wrote:
>> From: Ezequiel Garcia
>>
>> This driver is currently broken, refusing to initialize properly.
>>
>> The reason is that get_nand_dev_by_index() was being called before
>> na
STiH410 has 2 PHYs wired on the DWC3 IP, USB2 and USB3 PHYs.
As currently no U-boot driver is available for the USB3 PHY and to avoid
issue during DWC3 drive probe, we use DWC3 IP with only USB2 PHY
using stih410-b2260-u-boot.dtsi file.
Fixes: 2fd4242cc50e ("ubs: xhci-dwc3: Enable USB3 PHY when av
With the recent changes, the size of the U-Boot proper image for
uniphier_v7_defconfig exceeded the current limit, 512KB, then SPL
fails to load the whole of the U-Boot proper. Increase the size.
Signed-off-by: Masahiro Yamada
---
include/configs/uniphier.h | 2 +-
1 file changed, 1 insertion(
From: Hannes Schmelzer
Some IP-core implementations of the SDHCI have different troubles on the
silicon where they are placed.
On ZYNQ platform for example Xilinx doesn't accept the hold timing of an
eMMC chip which operates in High-Speed mode and must be forced to
operate in non high-speed mode
The 'SDHCI_QUIRK_NO_HISPD_BIT' is used wrong here. The purpose of this
quirk is to tell the sdhci-driver that the IP-core doesn't have a "high-
speed-enable" bit in its registers.
With this commit we change this to the correct quirk:
SDHCI_QUIRK_BROKEN_HISPD_MODE
Signed-off-by: Hannes Schmelzer
2018-04-16 17:13 GMT+09:00 Patrick Delaunay :
> Save and use the 3rd parameter of PSCI CPU_ON request: context_id.
>
> The context_id parameter is only meaningful to the caller.
> U-Boot PSCI preserves a copy of the value passed in this parameter.
> Following wakeup from a powerdown state, U-BOOT
2018-04-16 17:15 GMT+09:00 Patrick Delaunay :
> Replace the psci_save_target_pc call by the new function
> psci_save(cpu, pc,context_id)
>
> Signed-off-by: Patrick Delaunay
> ---
>
Acked-by: Masahiro Yamada
--
Best Regards
Masahiro Yamada
___
U-Boot
Usually, the image size tends to increase gradually.
Finally, it is hitting the size limit for my board.
One size consuming part is the clock driver, and it is only used
by the SD/eMMC driver in SPL. By disabling it, I can save lots of space.
Masahiro Yamada (4):
mmc: tmio: move clk_enable(
The size of SPL is hitting the limit (64KB) for uniphier_v7_defconfig.
When booting from SD/eMMC, obviously its clock has been properly set up
by the boot ROM. Acutually, no need to re-initialize the clock in SPL.
Using a clock driver would generalize the SoC specific code, but
solving the memory
I need to differentiate the clock handling for uniphier-sd. Move it
to each driver's probe function from the tmio common code so that
renesas-sdhi will not be affected.
Signed-off-by: Masahiro Yamada
---
drivers/mmc/renesas-sdhi.c | 23 +++
drivers/mmc/tmio-common.c | 22 -
Now that the SD/eMMC driver does not use the clock driver in SPL,
remove u-boot,dm-pre-reloc properties to let the fdtgrep tool drop
the unnecessary nodes.
Signed-off-by: Masahiro Yamada
---
arch/arm/dts/uniphier-v7-u-boot.dtsi | 16
1 file changed, 16 deletions(-)
diff --git
The last clock consumer in SPL, SD/eMMC driver, gave up using the
clock driver. The clock driver is only used in U-Boot proper.
Signed-off-by: Masahiro Yamada
---
drivers/clk/uniphier/Kconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/clk/uniphier/Kconfig b/drivers/clk/uniphier
+CC Marek
2018-04-20 18:14 GMT+09:00 Masahiro Yamada :
> I need to differentiate the clock handling for uniphier-sd. Move it
> to each driver's probe function from the tmio common code so that
> renesas-sdhi will not be affected.
>
> Signed-off-by: Masahiro Yamada
> ---
>
> drivers/mmc/renesas
Some boards support an SD card and an eMMC device at the same time.
Since both belong to 'mmc', they are identified by a device number.
When the device number of the eMMC is 1 instead 0, "mmc dev" command
must be performed to switch the target device before flashing images.
Signed-off-by: Masahiro
On Fri, Apr 20, 2018 at 5:23 AM, Alex Kiernan wrote:
> On Thu, Apr 19, 2018 at 8:39 PM, Tom Rini wrote:
>> On Thu, Apr 19, 2018 at 04:52:30AM +, Alex Kiernan wrote:
>>>
>>> On the face of it, this is a straightforward moveconfig, but because
>>> of how CONFIG_FIT_SIGNATURE, CONFIG_IMAGE_FORMA
Enable watchdog on zcu100 to make sure if there is a bug in the u-boot
there is proper reset.
Watchdog expires and PMU fw is informed and based on setting proper
action is taken.
The patch is enabling reset-on-timeout feature and also fixing fixed
clock rate for watchdog where 100MHz is max (and a
Hi Alexander,
What do you think of these patches? I haven't done testing with the
big kernels / DTBs yet, just that my previously-working kernel still
boots.
Tuomas Tynkkynen (2):
rpi: Fix fdt_high & initrd_high for 64-bit builds
rpi: Change load addresses to make more room for the kernel & D
The magic value that disables relocation is dependent on the CPU word
size, so the current '' is doing the wrong thing on aarch64.
Signed-off-by: Tuomas Tynkkynen
---
include/configs/rpi.h | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/include/configs/r
As of Linux 4.16, a multiplatform AArch64 kernel with our distro config
takes 26M. The current space reservation leaves only 17M for the kernel
and if it goes over it, the initrd gets overwritten when loading the
kernel from the filesystem.
A similar problem happens on ARMv7 with the DTBs taken fr
> Am 20.04.2018 um 09:09 schrieb Michal Simek :
>
> Hi Alex,
>
>> On 19.4.2018 18:48, Alexander Graf wrote:
>>> On 04/18/2018 03:11 PM, Michal Simek wrote:
>>> Xilinx ZynqMP also contains dual Cortex R5 which can run U-Boot.
>>> This patch is adding minimal support to get U-Boot boot.
>>> DDR n
From: Chee Hong Ang
This patch enable FPGA reconfiguration for Stratix10 SoC.
This patch works on top of:
https://lists.denx.de/pipermail/u-boot/2018-April/325900.html
Chee Hong Ang (3):
arm: socfpga: stratix10: Add Stratix10 FPGA Reconfiguration Driver
arm: socfpga: stratix10: Add Stratix10
Has the pending patch for the issue described below ever been released?
Am observing the same issue in the U-Boot version 2015-10.
On 2011/03/18 6:02 AM, Aaron Williams wrote:
> Hi,
>
> I am running into issues in that the CFI code is broken for flash with an 8-
> bit bus. The problem is that t
Hi,
Thanks for reading this email and I would be grateful if you have time to help
me fix the issue.
I am very much new to U-boot world and trying to build U-boot in my machine for
a particular board - 'Marvel Armada 38x'. While I was trying to compile the
u-boot fork for Marvel (in github), I
On 19/04/18 20:34, Fabio Estevam wrote:
From: Fabio Estevam
mx7dsabresd_secure_defconfig was introduced to allow booting NXP kernel
that has CAAM support and needs to boot in secure mode.
Instead of keeping two different config targets for the same board,
remove mx7dsabresd_secure_defconfig
From: Chee Hong Ang
Enable 'fpga' command in u-boot. User will be able to use the
fpga command to program the FPGA on Stratix10 SoC.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/misc.c | 20 +---
arch/arm/mach-socfpga/misc_s10.c | 4
drivers/fpga/altera.c
From: Chee Hong Ang
Enable FPGA reconfiguration support on Stratix10 SoC.
Signed-off-by: Chee Hong Ang
---
drivers/fpga/Kconfig | 10 ++
drivers/fpga/Makefile| 1 +
drivers/fpga/stratix10.c | 298 +++
3 files changed, 309 insertions(+)
cr
From: Chee Hong Ang
Enable Stratix10 FPGA reconfiguration support in defconfig.
Signed-off-by: Chee Hong Ang
---
configs/socfpga_stratix10_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/configs/socfpga_stratix10_defconfig
b/configs/socfpga_stratix10_defconfig
index 46b7999..2
On 18 April 2018 at 11:15, Peter Robinson wrote:
> On Tue, Apr 17, 2018 at 1:01 PM, Ramon Fried wrote:
>> The clock node is used by the serial driver and it's needed
>> before relocation.
>> This patch ensures that the msm-serial driver can actually
>> use the clock node.
>>
>> Signed-off-by: Ram
On 18 April 2018 at 13:15, Jorge Ramirez-Ortiz wrote:
> On 04/18/2018 09:02 AM, Jorge Ramirez-Ortiz wrote:
>>
>> On 04/17/2018 02:01 PM, Ramon Fried wrote:
>>>
>>> The clock node is used by the serial driver and it's needed
>>> before relocation.
>>> This patch ensures that the msm-serial driver c
On 04/20/2018 01:02 PM, Ramon Fried wrote:
On 18 April 2018 at 13:15, Jorge Ramirez-Ortiz wrote:
On 04/18/2018 09:02 AM, Jorge Ramirez-Ortiz wrote:
On 04/17/2018 02:01 PM, Ramon Fried wrote:
The clock node is used by the serial driver and it's needed
before relocation.
This patch ensures that
On 20 April 2018 at 14:14, Jorge Ramirez-Ortiz wrote:
> On 04/20/2018 01:02 PM, Ramon Fried wrote:
>>
>> On 18 April 2018 at 13:15, Jorge Ramirez-Ortiz
>> wrote:
>>>
>>> On 04/18/2018 09:02 AM, Jorge Ramirez-Ortiz wrote:
On 04/17/2018 02:01 PM, Ramon Fried wrote:
>
> The clock n
On 04/20/2018 01:22 PM, Ramon Fried wrote:
On 20 April 2018 at 14:14, Jorge Ramirez-Ortiz wrote:
On 04/20/2018 01:02 PM, Ramon Fried wrote:
On 18 April 2018 at 13:15, Jorge Ramirez-Ortiz
wrote:
On 04/18/2018 09:02 AM, Jorge Ramirez-Ortiz wrote:
On 04/17/2018 02:01 PM, Ramon Fried wrote:
Th
On Thu, 2018-04-12 at 15:12 -0700, Ivan Gorinov wrote:
> Coreboot timestamp functions and Quark memory reference code use
> get_tbclk() to get TSC frequency. This will not work if another
> early timer is selected.
>
> Add tsc_rate_mhz() function and use it in the code that specifically
> needs to
On 04/20/2018 05:22 PM, Ley Foon Tan wrote:
> On Thu, 2018-04-19 at 05:02 +0200, Marek Vasut wrote:
>> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
>>>
>>> Add the base address map for Statix10 SoC
>>>
>>> Signed-off-by: Chin Liang See
>>> Signed-off-by: Ley Foon Tan
>>> ---
>>> arch/arm/mach-soc
On 04/20/2018 09:49 AM, Ley Foon Tan wrote:
> On Thu, Apr 19, 2018 at 4:19 PM, Marek Vasut wrote:
>> On 04/19/2018 07:15 AM, See, Chin Liang wrote:
>>> On Thu, 2018-04-19 at 04:47 +0200, Marek Vasut wrote:
On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
>
> Add CONFIG_SYS_L2_PL310 conditi
Hei hei,
while reviewing what mkenvimage does in detail, I found two small bugs
in input file handling when reading from STDIN.
HTH & Greets
Alex
Alexander Dahl (2):
tools: mkenvimage: Fix read() stdin error handling
tools: mkenvimage: Fix possible segfault on stdin input
tools/mkenvimage.
On success read() returns the number of bytes read or zero for EOF. On
error -1 is returned and errno is set, so the right way to test if read
had failed is to test the return value instead of errno.
Signed-off-by: Alexander Dahl
---
tools/mkenvimage.c | 2 +-
1 file changed, 1 insertion(+), 1 d
The size of 'filebuf' was not increased as more and more bytes are read
from stdin, but 'filebuf' was always reallocated to the same fix size.
This works as long as only less bytes than the initial buffer size come
in, for more input this will segfault. (It actually does, I tested
that.) So for eac
On 04/19/2018 05:14 AM, Tom Rini wrote:
> On Wed, Apr 18, 2018 at 09:57:19PM +0200, Marek Vasut wrote:
>
>> The following changes since commit 8c0a17be0a632b9a823e14628c42f85c3e64f08e:
>>
>> Prepare v2018.05-rc2 (2018-04-16 20:00:14 -0400)
>>
>> are available in the Git repository at:
>>
>> gi
On 20 April 2018 at 14:50, Jorge Ramirez-Ortiz wrote:
> On 04/20/2018 01:22 PM, Ramon Fried wrote:
>>
>> On 20 April 2018 at 14:14, Jorge Ramirez-Ortiz
>> wrote:
>>>
>>> On 04/20/2018 01:02 PM, Ramon Fried wrote:
On 18 April 2018 at 13:15, Jorge Ramirez-Ortiz
wrote:
>
> On
This minimal support will be used by Xilinx ZynqMP R5 cpu.
Signed-off-by: Michal Simek
---
arch/arm/Kconfig | 6 ++
arch/arm/cpu/armv7r/Makefile | 4
arch/arm/cpu/armv7r/config.mk | 3 +++
arch/arm/cpu/armv7r/cpu.c | 24
arch/arm/cpu/armv7r
Xilinx ZynqMP also contains dual Cortex R5 which can run U-Boot.
This patch is adding minimal support to get U-Boot boot.
U-Boot on R5 runs out of DDR with default configuration that's why
DDR needs to be partitioned if there is something else running on arm64.
Console is done via Cadence uart driv
On Fri, Apr 20, 2018 at 03:46:00PM +0200, Marek Vasut wrote:
> On 04/19/2018 05:14 AM, Tom Rini wrote:
> > On Wed, Apr 18, 2018 at 09:57:19PM +0200, Marek Vasut wrote:
> >
> >> The following changes since commit
> >> 8c0a17be0a632b9a823e14628c42f85c3e64f08e:
> >>
> >> Prepare v2018.05-rc2 (2018
diff --git a/configs/xilinx_zynqmp_r5_defconfig
b/configs/xilinx_zynqmp_r5_defconfig
new file mode 100644
index ..46715242e703
--- /dev/null
+++ b/configs/xilinx_zynqmp_r5_defconfig
@@ -0,0 +1,16 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ZYNQMP_R5=y
>>>
On Fri, Apr 20, 2018 at 10:46:00AM +0100, Alex Kiernan wrote:
> On Fri, Apr 20, 2018 at 5:23 AM, Alex Kiernan wrote:
> > On Thu, Apr 19, 2018 at 8:39 PM, Tom Rini wrote:
> >> On Thu, Apr 19, 2018 at 04:52:30AM +, Alex Kiernan wrote:
> >>>
> >>> On the face of it, this is a straightforward mov
On 04/20/2018 03:46 PM, Ramon Fried wrote:
On 20 April 2018 at 14:50, Jorge Ramirez-Ortiz wrote:
On 04/20/2018 01:22 PM, Ramon Fried wrote:
On 20 April 2018 at 14:14, Jorge Ramirez-Ortiz
wrote:
On 04/20/2018 01:02 PM, Ramon Fried wrote:
On 18 April 2018 at 13:15, Jorge Ramirez-Ortiz
wrote:
On Fri, 2018-04-20 at 03:16 +, Prabhakar Kushwaha wrote:
> Thanks Scott for reviewing this patch
>
> > -Original Message-
> > From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Scott
> > Wood
> > Sent: Friday, April 20, 2018 6:40 AM
> > To: Calvin Johnson
> > Cc: U-Boot M
From: Stefan Agner
This patchset adds device tree support to the MXS NAND driver.
This also allows to use fixed ECC strenght usingt he device
tree properties nand-ecc-strength/nand-ecc-step-size and aligns
behavior with the Linux GPMI NAND driver.
This is based on the "mtd: nand: mxs_nand: impro
From: Stefan Agner
This function initializes DMA descriptors so mxs_nand_init_dma is
more precise. It also frees up the rather generic name mxs_nand_init.
Signed-off-by: Stefan Agner
---
drivers/mtd/nand/mxs_nand.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/driver
From: Stefan Agner
Move GPMI and BCH register structs to the driver struct mxs_nand_info
in prepartion for device tree support.
Signed-off-by: Stefan Agner
---
drivers/mtd/nand/mxs_nand.c | 32 +++-
1 file changed, 15 insertions(+), 17 deletions(-)
diff --git a/dr
From: Stefan Agner
In preparation for device tree support separate board init
from controller init similar to other raw NAND drivers.
Signed-off-by: Stefan Agner
---
drivers/mtd/nand/mxs_nand.c | 33 -
1 file changed, 20 insertions(+), 13 deletions(-)
diff --g
From: Stefan Agner
Signed-off-by: Stefan Agner
---
arch/arm/dts/imx7-colibri.dts | 28
1 file changed, 28 insertions(+)
diff --git a/arch/arm/dts/imx7-colibri.dts b/arch/arm/dts/imx7-colibri.dts
index f6c21052ae..a3b5618b45 100644
--- a/arch/arm/dts/imx7-colibri.d
From: Stefan Agner
Add use_minimum_ecc as struct mxs_nand_info field in preparation
for device tree support.
Signed-off-by: Stefan Agner
---
drivers/mtd/nand/mxs_nand.c | 34 --
1 file changed, 20 insertions(+), 14 deletions(-)
diff --git a/drivers/mtd/nand/mx
From: Stefan Agner
Support driver data from device tree. Also support fsl,use-minimal-ecc
similar to Linux' GPMI NAND driver.
Signed-off-by: Stefan Agner
---
drivers/mtd/nand/Kconfig | 7 +++
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/mxs_nand.c| 5 ++
drivers/mtd/nan
From: Stefan Agner
Sync with Linux commit 60cc43fc8884 ("Linux 4.17-rc1").
Signed-off-by: Stefan Agner
---
arch/arm/dts/imx7s.dtsi | 491 +++-
include/dt-bindings/clock/imx7d-clock.h | 15 +-
include/dt-bindings/power/imx7-power.h | 16 +
3 files changed
From: Stefan Agner
Create separate header file so we can use a separate compile
unit for device tree support.
Signed-off-by: Stefan Agner
---
drivers/mtd/nand/mxs_nand.c | 61 ++-
drivers/mtd/nand/mxs_nand.h | 72 +
2 files chang
From: Stefan Agner
Add support for specified ECC strength/size using device tree
properties nand-ecc-strength/nand-ecc-step-size.
This aligns behavior with the mainline driver, such that:
- If fsl,use-minimal-ecc is requested it will use data from
data sheet/ONFI. If this is not available the
Hi Bin,
On Wed, Apr 18, 2018 at 07:05:28PM -0600, Bin Meng wrote:
> >> >
> >> > If there is no ROM image, ucode_base and ucode_size are not initialized
> >> > and
> >> > the microcode update data from DTB applied by microcode_update_intel()
> >> > to the
> >> > bootstrap CPU is not used by the m
On Fri, Apr 20, 2018 at 06:25:08AM -0600, Andy Shevchenko wrote:
> > Coreboot timestamp functions and Quark memory reference code use
> > get_tbclk() to get TSC frequency. This will not work if another
> > early timer is selected.
> >
> > Add tsc_rate_mhz() function and use it in the code that spe
On Fri, Apr 20, 2018 at 10:41 AM, Arunashis Ghose wrote:
> Hi,
>
> Thanks for reading this email and I would be grateful if you have time to
> help me fix the issue.
>
> I am very much new to U-boot world and trying to build U-boot in my machine
> for a particular board - 'Marvel Armada 38x'. Wh
On 20 April 2018 at 17:45, Jorge Ramirez-Ortiz wrote:
> On 04/20/2018 03:46 PM, Ramon Fried wrote:
>>
>> On 20 April 2018 at 14:50, Jorge Ramirez-Ortiz
>> wrote:
>>>
>>> On 04/20/2018 01:22 PM, Ramon Fried wrote:
On 20 April 2018 at 14:14, Jorge Ramirez-Ortiz
wrote:
>
> On
On 20 April 2018 at 21:38, Ramon Fried wrote:
> On 20 April 2018 at 17:45, Jorge Ramirez-Ortiz wrote:
>> On 04/20/2018 03:46 PM, Ramon Fried wrote:
>>>
>>> On 20 April 2018 at 14:50, Jorge Ramirez-Ortiz
>>> wrote:
On 04/20/2018 01:22 PM, Ramon Fried wrote:
>
> On 20 April 2018
The clock node is used by the serial driver and it's needed
before relocation.
This patch ensures that the msm-serial driver can actually
use the clock node.
Signed-off-by: Ramon Fried
---
v2: Moved the u-boot,dm-pre-reloc attribute to the -uboot.dtsi file
arch/arm/dts/dragonboard410c-uboot.dts
The clock node is used by the serial driver and it's needed
before relocation.
This patch ensures that the msm-serial driver can actually
use the clock node.
Signed-off-by: Ramon Fried
---
v2: Moved the u-boot,dm-pre-reloc attribute to the -uboot.dtsi file
v3: Moved the forgotten u-boot,dm-pre-re
When building the mxs platform in thumb mode gcc generates code using
the intra procedure call scratch register (ip/r12) for the calling the
lowlevel_init function. This modifies the lr in flush_dcache which
causes u-boot proper to end in an endless loop.
40002334: e1a0c00emov ip
platform it was observed that there are some thumb-interwork issues
in the handwritten assembly files.
Since the first patch only applies to ARM926EJS and no board on that platform
has thumb enabled for now,it was probably never observed.
The second one applies to the ARM specific assembly memcpy
The current arch implementation of memcpy cannot be called
from thumb code, because it does not use bx instructions on return.
This patch addresses that. Note, that this patch does not touch
the hot loop of memcpy, so performance is not affected.
Tested on MXS (arm926ejs) with and without thumb-mo
On Mon, Apr 16, 2018 at 10:37:11PM +0200, Michael Nazzareno Trimarchi wrote:
> Hi
>
> On Mon, Apr 16, 2018 at 9:55 PM, Maxime Ripard
> wrote:
> > On Fri, Apr 06, 2018 at 07:54:47AM +0200, Maxime Ripard wrote:
> >> Hi Jaehoon,
> >>
> >> On Wed, Mar 21, 2018 at 12:18:58PM +0100, Maxime Ripard wrote
Hi
On Fri, Apr 20, 2018 at 10:10 PM, Maxime Ripard
wrote:
> On Mon, Apr 16, 2018 at 10:37:11PM +0200, Michael Nazzareno Trimarchi wrote:
>> Hi
>>
>> On Mon, Apr 16, 2018 at 9:55 PM, Maxime Ripard
>> wrote:
>> > On Fri, Apr 06, 2018 at 07:54:47AM +0200, Maxime Ripard wrote:
>> >> Hi Jaehoon,
>> >
This converts IMAGE_FORMAT_LEGACY to Kconfig
Signed-off-by: Alex Kiernan
---
Convert CONFIG_IMAGE_FORMAT_LEGACY to Kconfig. We also drop
CONFIG_DISABLE_IMAGE_LEGACY as this can now be handled through
configuration.
Green Travis build:
https://travis-ci.org/akiernan/u-boot/builds/369244180
Chan
Hi Jagan,
On Fri, Apr 20, 2018 at 09:37:29PM +, Jagan Teki wrote:
> On Thu, Mar 22, 2018 at 8:13 PM, Angelo Dureghello wrote:
> > This patch adds DM support to cf_spi.c.
> > To be able to build spi driver with DM support, a new config
> > option has been introdiced (DM_NO_DT) since m68k archi
On 04/20/2018 09:51 PM, Klaus Goger wrote:
> When building the mxs platform in thumb mode gcc generates code using
> the intra procedure call scratch register (ip/r12) for the calling the
> lowlevel_init function. This modifies the lr in flush_dcache which
> causes u-boot proper to end in an endles
> On 20.04.2018, at 23:55, Marek Vasut wrote:
>
> On 04/20/2018 09:51 PM, Klaus Goger wrote:
>> When building the mxs platform in thumb mode gcc generates code using
>> the intra procedure call scratch register (ip/r12) for the calling the
>> lowlevel_init function. This modifies the lr in flus
On Fri, 20 Apr 2018, 10:55 PM Arunashis Ghose, wrote:
> Hi,
>
> Thanks for reading this email and I would be grateful if you have time to
> help me fix the issue.
>
> I am very much new to U-boot world and trying to build U-boot in my
> machine for a particular board - 'Marvel Armada 38x'. While
On Fri, Apr 20, 2018 at 3:43 AM, Mehmet Ali İPİN
wrote:
> Dear Fabio
>
> Thank you very much for your directives and helps.
>
> I applied the steps in WARP board readme file, for the command
>
> => ums 0 mmc 2
>
> I received Unknown command 'ums' - try 'help'
>
> I compared with WARP7 defconfig a
Hello,
I'm trying to get verified-boot working using u-boot 2016.03 on an imx6.
So far I've managed to figure out that I need the following additional
config settings:
#define CONFIG_DM
#define CONFIG_ENABLE_VBOOT
#define CONFIG_RSA
#define CONFIG_FIT
#define CONFIG_OF_CONTROL
#define CONFIG_FIT
Okay. I found my first mistake. I would help if I could spell properly!
Turns out it was:
#define CONFIG_OF_SEPARATE
and not
#define CONFIG_OF_SEPERATE
but now I'm getting an error:
LD test/dm/built-in.o
CC examples/standalone/stubs.o
LD examples/standalone/libstubs.o
CC
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