On 03.02.18 02:47, Jonathan Gray wrote:
> On Sun, Jan 28, 2018 at 01:54:25PM -0500, Tom Rini wrote:
>> On Tue, Jan 23, 2018 at 06:05:21PM +0100, Alexander Graf wrote:
>>
>>> The bcm283x family of SoCs have a GPIO controller that also acts as
>>> pinctrl controller.
>>>
>>> This patch introduces a
BCM6362 is a dual core BCM63xx SoC.
v2: Introduce changes suggested by Daniel Schwierzeck:
- Use setbits_be32()
Álvaro Fernández Rojas (3):
dm: cpu: bmips: add BCM6362 support
MIPS: add support for Broadcom MIPS BCM6362 SoC family
MIPS: add BMIPS Netgear DGND3700v2 board
arch/mips/dts/Ma
Signed-off-by: Álvaro Fernández Rojas
---
v2: no changes
drivers/cpu/bmips_cpu.c | 51 +
1 file changed, 51 insertions(+)
diff --git a/drivers/cpu/bmips_cpu.c b/drivers/cpu/bmips_cpu.c
index 4ad291a56e..6c612bacdc 100644
--- a/drivers/cpu/bmips_c
Signed-off-by: Álvaro Fernández Rojas
---
v2: Introduce changes suggested by Daniel Schwierzeck:
- Use setbits_be32()
arch/mips/dts/Makefile | 1 +
arch/mips/dts/netgear,dgnd3700v2.dts | 121 +++
arch/mips/mach-bmips/Kconfig | 1
Signed-off-by: Álvaro Fernández Rojas
---
v2: no changes
arch/mips/dts/brcm,bcm6362.dtsi| 186 +
arch/mips/mach-bmips/Kconfig | 12 ++
include/configs/bmips_bcm6362.h| 25 +++
include/dt-bindings/clock/bcm6362-c
On 01.02.2018 20:47, Maxime Ripard wrote:
> On Thu, Feb 01, 2018 at 11:06:14AM +0100, Simon Goldschmidt wrote:
>> On 23.01.2018 21:17, Maxime Ripard wrote:
>> > Now that we have everything in place in the code, let's allow to build
>> > multiple environments backend through Kconfig.
>> >
>> > Revie
On 02/02/2018 21:04, York Sun wrote:
> On 02/02/2018 10:51 AM, Maxime Ripard wrote:
>
>
>
>
Simon,
This patch looks correct. But it doesn't fix NOR flash. Do you have plan
to add .get_char function to other drivers? Without that function, we
cannot get env variables
On Sat, Feb 03, 2018 at 09:02:25AM +0100, Alexander Graf wrote:
>
>
> On 03.02.18 02:47, Jonathan Gray wrote:
> > On Sun, Jan 28, 2018 at 01:54:25PM -0500, Tom Rini wrote:
> >> On Tue, Jan 23, 2018 at 06:05:21PM +0100, Alexander Graf wrote:
> >>
> >>> The bcm283x family of SoCs have a GPIO contro
To support the integrated phy, it is necessary that the gmac need
to get 50M clock rate from internal PLL, the integrated phy can't
generate 50M clock itself.
David Wu (14):
net: rockchip: Separate rmii and rgmii speed setup
net: rockchip: Add rmii interface and rmii speed setup for rk3228 an
The rk3228 and rk3328 Socs both have rmii interface, that might be used,
so add them for usage.
Signed-off-by: David Wu
---
drivers/net/gmac_rockchip.c | 115
1 file changed, 115 insertions(+)
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/g
Some Socs both have rgmii and rmii interface, so we need to
separate their speed setting.
Signed-off-by: David Wu
---
drivers/net/gmac_rockchip.c | 62 +++--
1 file changed, 43 insertions(+), 19 deletions(-)
diff --git a/drivers/net/gmac_rockchip.c b/dri
Some rockchio Socs have integrated phy inside, to support it,
add the integrated phy ops.
Signed-off-by: David Wu
---
drivers/net/gmac_rockchip.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index 5a
The rk3228 and rk3328 Socs both support integrated phy, implement
their power up function to support it.
Signed-off-by: David Wu
---
drivers/net/gmac_rockchip.c | 122
1 file changed, 122 insertions(+)
diff --git a/drivers/net/gmac_rockchip.c b/driv
It seems that the "CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)" always
should not been active.
Signed-off-by: David Wu
---
drivers/clk/rockchip/clk_rk3036.c | 2 +-
drivers/clk/rockchip/clk_rk322x.c | 4 ++--
drivers/clk/rockchip/clk_rk3288.c | 2 +-
drivers/clk/rockchip/clk_rk3328.c | 4 ++--
dri
The SCLK_MAC_SRC is the same as the SCLK_MAC, it is requested
by the integrated phy usuage.
Signed-off-by: David Wu
---
drivers/clk/rockchip/clk_rk322x.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/rockchip/clk_rk322x.c
b/drivers/clk/rockchip/clk_rk322x.c
index 4022065..727
There is a wrong selection for gmac pll source, fix it.
Signed-off-by: David Wu
---
drivers/clk/rockchip/clk_rk322x.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk_rk322x.c
b/drivers/clk/rockchip/clk_rk322x.c
index 4bbcaf8..72c8757 100644
--- a/dr
The gmac for integrated phy need 50M clock, it seems that only
come from CPLL 600M, the GPLL is not suitable.
Signed-off-by: David Wu
---
arch/arm/include/asm/arch-rockchip/cru_rk322x.h | 1 +
drivers/clk/rockchip/clk_rk322x.c | 11 +++
2 files changed, 8 insertions(+), 4
To support the integrated phy for rk322x, add their reset and clock
property at dtsi level.
Signed-off-by: David Wu
---
arch/arm/dts/rk322x.dtsi | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/rk322x.dtsi b/arch/arm/dts/rk322x.dtsi
index 22324f9..b0254a3
The gmac2phy is connected with integrated with phy, we can
fix the phy node at dtsi level.
Signed-off-by: David Wu
---
arch/arm/dts/rk3328.dtsi | 35 +++
1 file changed, 35 insertions(+)
diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi
index 5de1
In fact, the evb-rk3229 is default supported the integrated phy,
not need to change any hardware. So it is better to enbale it and
disable external 1000M phy.
Signed-off-by: David Wu
---
arch/arm/dts/rk3229-evb.dts | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch
Implement the setting parent and rate for gmac2phy clock, and
add internal pll div set for gmac2phy clk.
Signed-off-by: David Wu
---
drivers/clk/rockchip/clk_rk3328.c | 86 +++
1 file changed, 86 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3328.c
The integtated phy inside the rk3229 and rk3328 need the reset
request for power up.
Signed-off-by: David Wu
---
configs/evb-rk3229_defconfig | 1 +
configs/evb-rk3328_defconfig | 1 +
2 files changed, 2 insertions(+)
diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig
ind
In fact, the rk3328-evb is default supported the integrated phy,
not need to change any hardware. So it is better to enbale it and
disable external 1000M phy.
Signed-off-by: David Wu
---
arch/arm/dts/rk3328-evb.dts | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/dts/rk3
Signed-off-by: Álvaro Fernández Rojas
---
v2: add missing Huawei HG556a
configs/comtrend_ar5315u_ram_defconfig | 1 +
configs/comtrend_ar5387un_ram_defconfig | 1 +
configs/comtrend_ct5361_ram_defconfig| 1 +
configs/comtrend_vr3032u_ram_defconfig | 1 +
configs/comtrend_wap5813n_ram_d
On Sat, Feb 3, 2018 at 5:29 AM, Lukasz Majewski wrote:
> The goal of this patch is to clean up the code related to choosing SPL
> MMC boot mode.
>
> The spl_boot_mode() now is called only in spl_mmc_load_image() function,
> which is only compiled in if CONFIG_SPL_MMC_SUPPORT is enabled.
>
> To ach
Hi Tom,
On 26 January 2018 at 17:50, Tom Rini wrote:
> On Fri, Jan 26, 2018 at 02:45:29PM -0700, Simon Glass wrote:
>
>> Hi Tom,
>>
>> Here are some additions to logging and 64-bit sandbox support.
>>
>>
>> The following changes since commit ab12aa24e619b5e81cbde7de88c6d9a19f04313b:
>>
>> ARM:
At present dtc produces these warnings when compiling sandbox:
arch/sandbox/dts/test.dtb: Warning (reg_format): "reg" property in
/chosen/chosen-test has invalid length (8 bytes) (#address-cells == 2,
#size-cells == 1)
arch/sandbox/dts/test.dtb: Warning (avoid_default_addr_size): Relying on
def
At present dtc produces these warnings when compiling sandbox:
arch/sandbox/dts/test.dtb: Warning (gpios_property):
Could not get phandle node for /base-gpios:num-gpios(cell 0)
arch/sandbox/dts/test.dtb: Warning (gpios_property):
Missing property '#gpio-cells' in node /reset-ctl or
On Sat, Feb 03, 2018 at 10:12:41AM -0700, Simon Glass wrote:
> Hi Tom,
>
> On 26 January 2018 at 17:50, Tom Rini wrote:
> > On Fri, Jan 26, 2018 at 02:45:29PM -0700, Simon Glass wrote:
> >
> >> Hi Tom,
> >>
> >> Here are some additions to logging and 64-bit sandbox support.
> >>
> >>
> >> The fol
Hi Simon, Philipp,
When I try to convert to live dt, I fount there are many APIs work
in fdt are missing in live dt,
do you have any suggestion to add these APIs in live dt quickly? I need:
fdtdec_get_addr_size_auto_noparent
fdt_alloc_phandle
fdt_device_is_available
fdt_for_each_subnode
fdt_
Hi David,
On 02/03/2018 02:56 PM, David Wu wrote:
> Use this driver to fit all Rockchip SOCs and to support
> the desired pinctrl configuration via DTS.
>
> Signed-off-by: David Wu
Reviewed-by: Kever Yang
Tested-by: Kever Yang
Thanks,
- Kever
> ---
>
> drivers/pinctrl/Kconfig|
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