To support the integrated phy, it is necessary that the gmac need
to get 50M clock rate from internal PLL, the integrated phy can't
generate 50M clock itself.
David Wu (14):
net: rockchip: Separate rmii and rgmii speed setup
net: rockchip: Add rmii interface and rmii speed setup for rk3228 and
rk3328
net: rockchip: Add integrated phy ops
net: rockchip: Add integrated phy for rk3228 and rk3328
cllk: rockchip: Change the defined name for CONFIG_RESET_ROCKCHIP
clk: rockchip: fix the gmac selection of pll source for rk322x
clk: rockchip: Init CPLL 600M for rk322x
clk: rockchip: Add SCLK_MAC_SRC clock rate setup
ARM: dts: rockchip: Add integrated phy reset and clock for rk322x
ARM: dts: rockchip: Enable integrated phy support for rk3229-evb
clk: rk3328: Implement the gmac2phy clock assignment
ARM: dts: rockchip: Add gmac2phy dts node for rk3328
ARM: dts: rockchip: Enable gmac2phy feature for rk3328-evb
rockchip: defconfig: Enable CONFIG_RESET_ROCKCHIP for rk3329-evb and
rk3328-evb
arch/arm/dts/rk3229-evb.dts | 22 ++
arch/arm/dts/rk322x.dtsi | 8 +-
arch/arm/dts/rk3328-evb.dts | 10 +
arch/arm/dts/rk3328.dtsi | 35 +++
arch/arm/include/asm/arch-rockchip/cru_rk322x.h | 1 +
configs/evb-rk3229_defconfig | 1 +
configs/evb-rk3328_defconfig | 1 +
drivers/clk/rockchip/clk_rk3036.c | 2 +-
drivers/clk/rockchip/clk_rk322x.c | 18 +-
drivers/clk/rockchip/clk_rk3288.c | 2 +-
drivers/clk/rockchip/clk_rk3328.c | 90 ++++++-
drivers/clk/rockchip/clk_rk3368.c | 2 +-
drivers/clk/rockchip/clk_rk3399.c | 2 +-
drivers/clk/rockchip/clk_rv1108.c | 2 +-
drivers/net/gmac_rockchip.c | 328 ++++++++++++++++++++++--
15 files changed, 487 insertions(+), 37 deletions(-)
--
2.7.4
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