From: Boris Brezillon
The NAND framework provides several helpers to query timing modes supported
by a NAND chip, but this implies that all NAND controller drivers have
to implement the same timings selection dance. Also currently NAND
devices can be resetted at arbitrary places which also resets
From: Boris Brezillon
Drivers setting NAND_ECC_CUSTOM_PAGE_ACCESS are supposed to handle the
full read/write page sequence, and waiting for a page to actually be
programmed is part of this write-page sequence.
This is also what is done in ->write_oob_xxx() hooks, so let's do that in
->write_page_
I largely reworked the Denali NAND controller driver in Linux.
This commit imports the improvements from Linux. The code is
almost synced with Linux 4.15-rc1.
Signed-off-by: Masahiro Yamada
---
drivers/mtd/nand/Kconfig | 11 -
drivers/mtd/nand/denali.c | 2028 +--
From: Sascha Hauer
Currently we have no data structure to fully describe a NAND timing.
We only have struct nand_sdr_timings for NAND timings in SDR mode,
but nothing for DDR mode and also no container to store both types
of timing.
This patch adds struct nand_data_interface which stores the timi
From: Sascha Hauer
struct nand_data_interface is the designated type to pass to
the NAND drivers to configure the timing. To simplify further
patches convert the onfi_sdr_timings array from type struct
nand_sdr_timings nand_data_interface.
Signed-off-by: Sascha Hauer
Signed-off-by: Boris Brezil
From: Boris Brezillon
Cached programming is always skipped, so drop the associated code until
we decide to really support it.
Signed-off-by: Boris Brezillon
[Linux commit: 0b4773fd1649e0d418275557723a7ef54f769dc9]
[masahiro: modify davinci_nand.c for U-Boot]
Signed-off-by: Masahiro Yamada
---
On 11/21/2017 09:41 AM, Joakim Tjernlund wrote:
> On Tue, 2017-11-21 at 17:32 +, York Sun wrote:
>> CAUTION: This email originated from outside of the organization. Do not
>> click links or open attachments unless you recognize the sender and know the
>> content is safe.
>>
>>
>> On 11/21/201
From: Boris Brezillon
The ->errstat() hook is no longer implemented NAND controller drivers.
Get rid of it before someone starts abusing it.
Signed-off-by: Boris Brezillon
[Linux commit: 7d135bcced20be2b50128432c5426a7278ec4f6d]
[masahiro: modify davinci_nand.c for U-Boot]
Signed-off-by: Masahi
From: Boris Brezillon
The generic NAND DT bindings allows one to tweak the ECC strength and
step size to their need. It can be used to lower the ECC strength to
match a bootloader/firmware config, but might also be used to get a better
reliability.
In the latter case, the user might want to use
From: Sascha Hauer
When NAND devices are resetted some initialization may have to be done,
like for example they have to be configured for the timing mode that
shall be used. To get a common place where this initialization can be
implemented create a nand_reset() function. This currently only iss
On Tue, 2017-11-21 at 17:32 +, York Sun wrote:
> CAUTION: This email originated from outside of the organization. Do not click
> links or open attachments unless you recognize the sender and know the
> content is safe.
>
>
> On 11/21/2017 09:29 AM, Joakim Tjernlund wrote:
> > On Tue, 2017-1
Add stubs to the header in case CONFIG_SYS_NAND_ONFI_DETECTION is
disabled. This is much easier than adding around #ifdef to the
caller side.
Also, I removed the #ifdef around onfi_params. In Linux, onfi_params
and jedec_params are unified as union. It will be the right thing
to do.
Signed-off
Driver are responsible for setting up ECC parameters correctly.
Those include:
- Check if ECC parameters specified (usually by DT) are valid
- Meet the chip's ECC requirement
- Maximize ECC strength if NAND_ECC_MAXIMIZE flag is set
The logic can be generalized by factoring out common code.
On Tue, 2017-11-21 at 17:45 +, York Sun wrote:
>
> On 11/21/2017 09:41 AM, Joakim Tjernlund wrote:
> > On Tue, 2017-11-21 at 17:32 +, York Sun wrote:
> > > CAUTION: This email originated from outside of the organization. Do not
> > > click links or open attachments unless you recognize th
On 11/21/2017 09:52 AM, Joakim Tjernlund wrote:
> On Tue, 2017-11-21 at 17:45 +, York Sun wrote:
>>
>> On 11/21/2017 09:41 AM, Joakim Tjernlund wrote:
>>> On Tue, 2017-11-21 at 17:32 +, York Sun wrote:
CAUTION: This email originated from outside of the organization. Do not
click
On Tue, 2017-11-21 at 18:04 +, York Sun wrote:
>
>
> On 11/21/2017 09:52 AM, Joakim Tjernlund wrote:
> > On Tue, 2017-11-21 at 17:45 +, York Sun wrote:
> > >
> > > On 11/21/2017 09:41 AM, Joakim Tjernlund wrote:
> > > > On Tue, 2017-11-21 at 17:32 +, York Sun wrote:
> > > > > CAUTION
On 11/21/2017 10:20 AM, Joakim Tjernlund wrote:
> On Tue, 2017-11-21 at 18:04 +, York Sun wrote:
>>
>>
>> On 11/21/2017 09:52 AM, Joakim Tjernlund wrote:
>>> On Tue, 2017-11-21 at 17:45 +, York Sun wrote:
On 11/21/2017 09:41 AM, Joakim Tjernlund wrote:
> On Tue, 2017-11-21 at
On Tue, 2017-11-21 at 18:35 +, York Sun wrote:
> CAUTION: This email originated from outside of the organization. Do not click
> links or open attachments unless you recognize the sender and know the
> content is safe.
>
>
> On 11/21/2017 10:20 AM, Joakim Tjernlund wrote:
> > On Tue, 2017-1
On 11/21/2017 10:40 AM, Joakim Tjernlund wrote:
> On Tue, 2017-11-21 at 18:35 +, York Sun wrote:
>> CAUTION: This email originated from outside of the organization. Do not
>> click links or open attachments unless you recognize the sender and know the
>> content is safe.
>>
>>
>> On 11/21/201
If 'file' cannot be allocated due to an out of memory
situation, do not dereference it.
When debugging this patch also avoids a misleading message
"cannot find next direntry, error %d" in case of an out of
memory situation. It is sufficent to write
"%s: Error, no memory for malloc!\n" in this case
This short series fixes a few issues related to our caching code - with
regards to DMA coherence, instruction cache coherence & systems with no
caches at all.
Applies atop u-boot-mips/next as of d7d9fc01a4ef ("Update Paul Burton's
email address").
Paul Burton (3):
MIPS: Ensure cache ops comple
A typical use of cache maintenance functions is to force writeback of
data which a device is about to read using DMA - for example a
descriptor or command structure. Such users of cache maintenance
functions require that operations on the cache have completed before
they proceed to instruct a devic
When writing code, for example during relocation, we ensure that the
icache has a coherent view of the new instructions with a call to
flush_cache(). This handles the bulk of the work to ensure the new
instructions will execute as expected, however it does not ensure that
the CPU pipeline doesn't a
Compilation of U-Boot fails with the appended .config
LOCK_PREFIX is defined in arch/x86/include/asm/bitops.h.
which is not included in rch/x86/include/asm/atomic.h.
The Linux kernel defines LOCK_PREFIX in
arch/x86/include/asm/alternative.h
included both in
arch/x86/include/asm/atomic.h
and in
a
If we run on a CPU which doesn't implement a particular cache then we
would previously get stuck in an infinite loop, executing a cache op on
the first "line" of the missing cache & then incrementing the address by
0. This was being avoided for the L2 caches, but not for the L1s. Fix
this by genera
Am 21.11.2017 um 20:18 schrieb Paul Burton:
> This short series fixes a few issues related to our caching code - with
> regards to DMA coherence, instruction cache coherence & systems with no
> caches at all.
>
> Applies atop u-boot-mips/next as of d7d9fc01a4ef ("Update Paul Burton's
> email add
Hi Daniel,
On Tue, Nov 21, 2017 at 08:57:15PM +0100, Daniel Schwierzeck wrote:
> Am 21.11.2017 um 20:18 schrieb Paul Burton:
> > This short series fixes a few issues related to our caching code - with
> > regards to DMA coherence, instruction cache coherence & systems with no
> > caches at all.
>
On Tue, Nov 21, 2017 at 07:45:03PM +0100, Heinrich Schuchardt wrote:
> If 'file' cannot be allocated due to an out of memory
> situation, do not dereference it.
>
> When debugging this patch also avoids a misleading message
> "cannot find next direntry, error %d" in case of an out of
> memory situ
This series fixes some issues with PCIe support on the MIPS Boston
development board, adds a driver for the EG20T GPIO controller that we
use to control ethernet PHY reset & enables support for ethernet on the
Boston board.
Note that QEMU currently (as of v2.10) does not emulate the EG20T
ethernet
On some systems aligning PCI memory to a 1MB boundary every time a
bridge is encountered may lead to exhausting the available memory space
before all devices have been assigned addresses.
For example on the MIPS Boston development board we have an Intel EG20T
Platform Controller Hub connected to a
Add a driver for the GPIO controller found in the Intel EG20T Platform
Controller Hub. This is used on the MIPS Boston development board to
provide GPIOs including ethernet PHY reset.
Signed-off-by: Paul Burton
Cc: Daniel Schwierzeck
Cc: Simon Glass
Cc: u-boot@lists.denx.de
Signed-off-by: Paul
Whilst the pcie_xilinx driver was sufficient to run under QEMU, it was
failing on FPGA because it wasn't configuring the root bridge, and
access from the PCI auto-configuration code to subordinate busses would
lead to data bus errors. Fix this by configuring the root bridge to
allow access to all p
Add support to the pch_gbe driver for resetting the PHY using a GPIO
specified in the device tree. This matches the support already in Linux.
Signed-off-by: Paul Burton
Cc: Daniel Schwierzeck
Cc: Joe Hershberger
Cc: Simon Glass
Cc: u-boot@lists.denx.de
Signed-off-by: Paul Burton
---
drivers
Allow for drivers to make use of driver model GPIOs when they're enabled
& available without needing to #ifdef on CONFIG_DM_GPIO by providing
dummy functions covering GPIO requests. Each will simply return -ENODEV
or -EINVAL, depending upon which the real implementation returns when a
GPIO isn't fo
On the MIPS Boston development board we have an Intel EG20T Platform
Controller Hub connected to a Xilinx AXI to PCIe root port which is only
assigned a 1MB memory region. The Intel EG20T contains a bridge device
beneath which all of its peripheral devices can be found, and that
bridge device conta
Generally we load Linux kernels on Boston boards in the form of FIT
images containing a compressed kernel binary. Linux is linked at
0x8010 and so we need to decompress the kernel binary to that
address, however this is our default load address which means that
unless explicitly avoided we hit
Add compatible strings for the PCIe bridges & EG20T ethernet controller
such that the devices are probed during boot, without the user needing
to manually cause that to happen by running "pci enum" after boot. This
allows for use of the ethernet controller without the manual PCI
enumeration step.
The pch_gbe driver has 4 paths which open-code the equivalent of
wait_for_bit(). Replace these with use of wait_for_bit() in order to
shorten the code & avoid duplication.
Signed-off-by: Paul Burton
Cc: Daniel Schwierzeck
Cc: Joe Hershberger
Cc: u-boot@lists.denx.de
---
drivers/net/pch_gbe.c
U-Boot is generally flashed to a MIPS Boston development board by means
of a .mcs file which Xilinx Vivado software can write to the flash
present on the board. As such we'd generally want to produce an mcs file
when building U-Boot to target the Boston board. Introduce a make target
for u-boot.mcs
Dear Heinrich,
In message <20171121184503.3193-1-xypron.g...@gmx.de> you wrote:
> If 'file' cannot be allocated due to an out of memory
> situation, do not dereference it.
>
> When debugging this patch also avoids a misleading message
> "cannot find next direntry, error %d" in case of an out of
>
On Tue, Nov 21, 2017 at 10:16:40PM +0100, Wolfgang Denk wrote:
> Dear Heinrich,
>
> In message <20171121184503.3193-1-xypron.g...@gmx.de> you wrote:
> > If 'file' cannot be allocated due to an out of memory
> > situation, do not dereference it.
> >
> > When debugging this patch also avoids a misl
On 21.11.2017 21:37, Paul Burton wrote:
> U-Boot is generally flashed to a MIPS Boston development board by means
> of a .mcs file which Xilinx Vivado software can write to the flash
> present on the board. As such we'd generally want to produce an mcs file
> when building U-Boot to target the Bo
On 11/21/2017 10:16 PM, Wolfgang Denk wrote:
Dear Heinrich,
In message <20171121184503.3193-1-xypron.g...@gmx.de> you wrote:
If 'file' cannot be allocated due to an out of memory
situation, do not dereference it.
When debugging this patch also avoids a misleading message
"cannot find next di
On 21.11.2017 21:35, Paul Burton wrote:
> Generally we load Linux kernels on Boston boards in the form of FIT
> images containing a compressed kernel binary. Linux is linked at
> 0x8010 and so we need to decompress the kernel binary to that
> address, however this is our default load address
On 11/21/2017 09:23 PM, Ladislav Michl wrote:
On Tue, Nov 21, 2017 at 07:45:03PM +0100, Heinrich Schuchardt wrote:
If 'file' cannot be allocated due to an out of memory
situation, do not dereference it.
When debugging this patch also avoids a misleading message
"cannot find next direntry, err
+cc Michal for Xilinx stuff
On 21.11.2017 21:33, Paul Burton wrote:
> Whilst the pcie_xilinx driver was sufficient to run under QEMU, it was
> failing on FPGA because it wasn't configuring the root bridge, and
> access from the PCI auto-configuration code to subordinate busses would
> lead to data
On 21.11.2017 21:33, Paul Burton wrote:
> The pch_gbe driver has 4 paths which open-code the equivalent of
> wait_for_bit(). Replace these with use of wait_for_bit() in order to
> shorten the code & avoid duplication.
>
> Signed-off-by: Paul Burton
> Cc: Daniel Schwierzeck
> Cc: Joe Hershberge
On Tue, Nov 21, 2017 at 10:29:51PM +0100, Heinrich Schuchardt wrote:
>
>
> On 11/21/2017 09:23 PM, Ladislav Michl wrote:
> > On Tue, Nov 21, 2017 at 07:45:03PM +0100, Heinrich Schuchardt wrote:
> > > If 'file' cannot be allocated due to an out of memory
> > > situation, do not dereference it.
> >
On 21.11.2017 21:33, Paul Burton wrote:
> Add support to the pch_gbe driver for resetting the PHY using a GPIO
> specified in the device tree. This matches the support already in Linux.
>
> Signed-off-by: Paul Burton
> Cc: Daniel Schwierzeck
> Cc: Joe Hershberger
> Cc: Simon Glass
> Cc: u-bo
If 'file' cannot be allocated due to an out of memory
situation, NULL is dereferenced.
Variables file and dentry are not needed at all.
So let's eliminate them.
When debugging this patch also avoids a misleading message
"cannot find next direntry, error %d" in case of an out of
memory situation.
On 21.11.2017 21:33, Paul Burton wrote:
> Add a driver for the GPIO controller found in the Intel EG20T Platform
> Controller Hub. This is used on the MIPS Boston development board to
> provide GPIOs including ethernet PHY reset.
>
> Signed-off-by: Paul Burton
> Cc: Daniel Schwierzeck
> Cc: Si
On 21.11.2017 21:33, Paul Burton wrote:
> Allow for drivers to make use of driver model GPIOs when they're enabled
> & available without needing to #ifdef on CONFIG_DM_GPIO by providing
> dummy functions covering GPIO requests. Each will simply return -ENODEV
> or -EINVAL, depending upon which th
On 21.11.2017 21:33, Paul Burton wrote:
> On some systems aligning PCI memory to a 1MB boundary every time a
> bridge is encountered may lead to exhausting the available memory space
> before all devices have been assigned addresses.
>
> For example on the MIPS Boston development board we have a
GCC 7.1 seems to be smart enough to track val through the various
static inline functions, but not smart enough to see that val will
always be initialised when no error is returned. This triggers
the following warning:
env/mmc.c: In function 'mmc_get_env_addr':
env/mmc.c:121:12: warning: 'val'
U-Boot is generally flashed to a MIPS Boston development board by means
of a .mcs file which Xilinx Vivado software can write to the flash
present on the board. As such we'd generally want to produce an mcs file
when building U-Boot to target the Boston board. Introduce a make target
for u-boot.mcs
> setup_boot_mode function use the same logic but different
> mode register address across all the rockchip platforms,
> so it's better to make this function reused across all the
> platforms, and let the mode register address setting from
> the config file.
>
> Signed-off-by: Andy Yan
> Reviewed
> Rockchip bootrom will enter download mode if it returns from
> spl/tpl with a non-zero value and couldn't find a valid image
> in the backup partition.
> This patch provide a method to instruct the system to back to
> bootrom download mode by checking the BROM_DOWNLOAD_FLAG register.
> As the boo
> Enter download mode if the download key pressed.
>
> Signed-off-by: Andy Yan
> Acked-by: Philipp Tomsich
> Reviewed-by: Philipp Tomsich
> ---
>
> Changes in v3: None
> Changes in v2:
> - more document
> - move adc key detect as the default
>
> arch/arm/mach-rockchip/boot_mode.c | 43
> +++
On Tue, Nov 21, 2017 at 11:06:35PM +0100, Heinrich Schuchardt wrote:
> If 'file' cannot be allocated due to an out of memory
> situation, NULL is dereferenced.
>
> Variables file and dentry are not needed at all.
> So let's eliminate them.
>
> When debugging this patch also avoids a misleading me
On Fri, 3 Nov 2017, Kever Yang wrote:
From: Elaine Zhang
Create driver to support all Rockchip SoCs soft reset.
Example of usage:
i2c driver:
ret = reset_get_by_name(dev, "i2c", &reset_ctl);
if (ret) {
error("reset_get_by_name() failed: %d\n", ret);
}
On Fri, 3 Nov 2017, Kever Yang wrote:
From: Elaine Zhang
all rockchip socs add device_bind_driver_to_node,
to bound device rockchip reset to clock-controller.
Signed-off-by: Elaine Zhang
Signed-off-by: Kever Yang
Acked-by: Philipp Tomsich
Reviewed-by: Philipp Tomsich
See below for re
Hi Lukasz,
Thanks for your quick comments on this topic.
On 11/21/2017 06:29 PM, Lukasz Majewski wrote:
Hi Kever,
Hi Guys,
I try to understand why we need to do the relocate in U-Boot.
From the document README/crt0.S, I think the relocation feature comes
from some SoC have limite
Hi Michal,
On Wed, 2017-11-08 at 07:27 +0100, Michal Simek wrote:
> On 8.11.2017 03:54, Wilson Lee wrote:
> >
> > Initial platform creation for NIZYNQ.
> >
> > Signed-off-by: Joe Hershberger
> > Signed-off-by: Keng Soon Cheah
> > Signed-off-by: Wilson Lee
> > Cc: Chen Yee Chew
> > Cc: Albert
Hi Michal,
On Wed, 2017-11-08 at 07:27 +0100, Michal Simek wrote:
> On 8.11.2017 03:54, Wilson Lee wrote:
> >
> > Initial platform creation for NIZYNQ.
> >
> > Signed-off-by: Joe Hershberger
> > Signed-off-by: Keng Soon Cheah
> > Signed-off-by: Wilson Lee
> > Cc: Chen Yee Chew
> > Cc: Albert
Hello Bhaskar
Please find feedback below.
Regards
Poonam
> -Original Message-
> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Bhaskar
> Upadhaya
> Sent: Tuesday, November 21, 2017 2:56 PM
> To: u-boot@lists.denx.de
> Cc: Bhaskar Upadhaya
> Subject: [U-Boot] [PATCH v2]
Zero partition_signature in the efi_device_path_hard_drive_path
structure when signature_type is 0 (no signature) as required by the
UEFI specification.
This is required so that efi_dp_match() will work as expected
when doing memcmp() comparisons. Previously uninitialised memory
would cause it no
Validates PPA, MC, DPC, Bootscript, DPL and Kernel images in ESBC phase
using esbc_validate command.
Enable validation of boot.scr script prior to its execution dependent
on "secureboot" flag in environment
Add header address for PPA to be validated during ESBC phase for LS1088A
platform based on
Add the secure boot defconfigs for QSPI boot on LS1088ARDB
and LS1088AQDS platforms.
Signed-off-by: Udit Agarwal
Signed-off-by: Vinitha Pillai-B57223
---
Changes in v4:
Adds Distro boot support defconfigs.
Adds config to unset CONFIG_BOOTCOOMAND.
Keeping defconfig options in sorted manner.
boa
Adds config CONFIG_FSL_LS_PPA and CONFIG_FSL_CAAM in
LS2080AQDS and LS2080ARDB secure boot defconfig.
Removes CONFIG_FIT, as with CONFIG_FSL_LS_PPA enabled,
CONFIG_FIT is selected.
Removes CONFIG_SPL_RSA as in NOR boot SPL boot is not done.
Signed-off-by: Udit Agarwal
---
Changes in v3:
Correct
Add fall back option, to boot from NOR/QSPI/SD for LS1043, LS1046,
LS1021 in case of distro boot failure.
LS1046: Add kernel validation in case of secure boot in sd_bootcmd
and qspi_bootcmd
LS1043 and LS1021: Add kernel validation in case of secure boot in
sd_bootcmd, qspi_bootcmdand nor_bootcmd
This patch series fixes bug which fails tftp sometimes
while using the pfe interfaces and also has some code clean up.
Calvin Johnson (3):
drivers: net: pfe_eth: add pfe_rx_done to clear bd after packet
processing
drivers: net: pfe_eth: use writel/readl to access hw bds
drivers: net: pf
writel/readl accessors should be used to access hardware
buffer descriptors.
Signed-off-by: Calvin Johnson
Signed-off-by: Anjaneyulu Jagarlmudi
---
drivers/net/pfe_eth/pfe_driver.c | 70
1 file changed, 35 insertions(+), 35 deletions(-)
diff --git a/dr
Create pfe_rx_done function to clear buffer descriptor
after the packet is processed by the network stack.
Signed-off-by: Calvin Johnson
Signed-off-by: Anjaneyulu Jagarlmudi
---
drivers/net/pfe_eth/pfe_driver.c | 35 ++-
drivers/net/pfe_eth/pfe_eth.c| 1 +
Typos are corrected.
Some sentences are rephrased.
Proper indentation added.
Signed-off-by: Calvin Johnson
---
drivers/net/pfe_eth/pfe_driver.c | 33 +++--
drivers/net/pfe_eth/pfe_eth.c| 12 ++--
2 files changed, 21 insertions(+), 24 deletions(-)
diff --
This patch series cleans up unused PFE code under CONFIG_PFE_WARN_WA
and CONFIG_UTIL_PE_DISABLED.
Calvin Johnson (2):
drivers: net: pfe_eth: remove unused code under
CONFIG_UTIL_PE_DISABLED
drivers: net: pfe_eth: remove unused code under CONFIG_PFE_WARN_WA
drivers/net/pfe_eth/pfe.c
remove unused code under CONFIG_UTIL_PE_DISABLED
Signed-off-by: Calvin Johnson
---
drivers/net/pfe_eth/pfe.c | 98 --
drivers/net/pfe_eth/pfe_cmd.c | 16 +--
drivers/net/pfe_eth/pfe_driver.c | 15 --
drivers/net/pfe_eth/pfe_firmware.c
remove unused code under CONFIG_PFE_WARN_WA
Signed-off-by: Calvin Johnson
---
drivers/net/pfe_eth/pfe_cmd.c | 28 +---
1 file changed, 1 insertion(+), 27 deletions(-)
diff --git a/drivers/net/pfe_eth/pfe_cmd.c b/drivers/net/pfe_eth/pfe_cmd.c
index 03a2690..559f8f0 1006
Hi,
On 22.11.2017 04:06, Wilson Lee wrote:
> Hi Michal,
>
> On Wed, 2017-11-08 at 07:27 +0100, Michal Simek wrote:
>> On 8.11.2017 03:54, Wilson Lee wrote:
>>>
>>> Initial platform creation for NIZYNQ.
>>>
>>> Signed-off-by: Joe Hershberger
>>> Signed-off-by: Keng Soon Cheah
>>> Signed-off-by:
On Wed, Nov 22, 2017 at 2:59 PM, Kever Yang wrote:
> Hi Lukasz,
>
>
> Thanks for your quick comments on this topic.
> On 11/21/2017 06:29 PM, Lukasz Majewski wrote:
>>
>> Hi Kever,
>>
>>> Hi Guys,
>>>
>>> I try to understand why we need to do the relocate in U-Boot.
>>> From the docume
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