On 21.11.2017 21:33, Paul Burton wrote: > Add a driver for the GPIO controller found in the Intel EG20T Platform > Controller Hub. This is used on the MIPS Boston development board to > provide GPIOs including ethernet PHY reset. > > Signed-off-by: Paul Burton <paul.bur...@imgtec.com> > Cc: Daniel Schwierzeck <daniel.schwierz...@gmail.com> > Cc: Simon Glass <s...@chromium.org> > Cc: u-boot@lists.denx.de > Signed-off-by: Paul Burton <paul.bur...@mips.com> > --- > > drivers/gpio/Kconfig | 8 +++ > drivers/gpio/Makefile | 1 + > drivers/gpio/eg20t-gpio.c | 139 > ++++++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 148 insertions(+) > create mode 100644 drivers/gpio/eg20t-gpio.c >
Reviewed-by: Daniel Schwierzeck <daniel.schwierz...@gmail.com> nits below > diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig > index 6240c39539..ac7c911951 100644 > --- a/drivers/gpio/Kconfig > +++ b/drivers/gpio/Kconfig > @@ -294,4 +294,12 @@ config MPC85XX_GPIO > > The driver has been tested on MPC85XX, but it is likely that other > PowerQUICC III devices will work as well. > + > +config EG20T_GPIO > + bool "Intel EG20T GPIO driver" > + depends on DM_GPIO && DM_PCI > + help > + Enable this to support the GPIO controller found in the Intel EG20T > + Platform Controller Hub. > + > endmenu > diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile > index 81f55a576b..150c7b3eb5 100644 > --- a/drivers/gpio/Makefile > +++ b/drivers/gpio/Makefile > @@ -60,3 +60,4 @@ obj-$(CONFIG_MVEBU_GPIO) += mvebu_gpio.o > obj-$(CONFIG_MSM_GPIO) += msm_gpio.o > obj-$(CONFIG_$(SPL_)PCF8575_GPIO) += pcf8575_gpio.o > obj-$(CONFIG_PM8916_GPIO) += pm8916_gpio.o > +obj-$(CONFIG_EG20T_GPIO) += eg20t-gpio.o > diff --git a/drivers/gpio/eg20t-gpio.c b/drivers/gpio/eg20t-gpio.c > new file mode 100644 > index 0000000000..958541689a > --- /dev/null > +++ b/drivers/gpio/eg20t-gpio.c > @@ -0,0 +1,139 @@ > +/* > + * Copyright (C) 2016 Imagination Technologies > + * > + * SPDX-License-Identifier: GPL-2.0 > + */ > + > +#include <common.h> > +#include <dm.h> > +#include <errno.h> > +#include <pci.h> > +#include <asm/io.h> > +#include <asm/gpio.h> > + > +enum { > + REG_IEN = 0x00, > + REG_ISTATUS = 0x04, > + REG_IDISP = 0x08, > + REG_ICLR = 0x0c, > + REG_IMASK = 0x10, > + REG_IMASKCLR = 0x14, > + REG_PO = 0x18, > + REG_PI = 0x1c, > + REG_PM = 0x20, > +}; > + > +struct eg20t_gpio_priv { > + void *base; > +}; > + > +static int eg20t_gpio_get_value(struct udevice *dev, unsigned int offset) > +{ > + struct eg20t_gpio_priv *priv = dev_get_priv(dev); > + u32 pm, pval; > + > + pm = readl(priv->base + REG_PM); > + if ((pm >> offset) & 0x1) > + pval = readl(priv->base + REG_PO); > + else > + pval = readl(priv->base + REG_PI); > + > + return (pval >> offset) & 0x1; > +} > + > +static int eg20t_gpio_set_value(struct udevice *dev, unsigned int offset, > + int value) > +{ > + struct eg20t_gpio_priv *priv = dev_get_priv(dev); > + u32 po; > + > + po = readl(priv->base + REG_PO); > + if (value) > + po |= 1 << offset; > + else > + po &= ~(1 << offset); > + writel(po, priv->base + REG_PO); you could use the macros setbits_32() and co. which are available for MIPS. If we get another user for this driver, he could add possibly missing macros to his architecture (e.g. ARM only has setbits_le32() but not setbits_32()). > + return 0; > +} > + > +static int eg20t_gpio_direction_input(struct udevice *dev, unsigned int > offset) > +{ > + struct eg20t_gpio_priv *priv = dev_get_priv(dev); > + u32 pm; > + > + pm = readl(priv->base + REG_PM); > + pm &= ~(1 << offset); > + writel(pm, priv->base + REG_PM); > + return 0; > +} > + > +static int eg20t_gpio_direction_output(struct udevice *dev, unsigned int > offset, > + int value) > +{ > + struct eg20t_gpio_priv *priv = dev_get_priv(dev); > + u32 pm; > + > + pm = readl(priv->base + REG_PM); > + pm |= 1 << offset; > + writel(pm, priv->base + REG_PM); > + > + return eg20t_gpio_set_value(dev, offset, value); > +} > + > +static int eg20t_gpio_get_function(struct udevice *dev, unsigned int offset) > +{ > + struct eg20t_gpio_priv *priv = dev_get_priv(dev); > + u32 pm; > + > + pm = readl(priv->base + REG_PM); > + > + if ((pm >> offset) & 0x1) > + return GPIOF_OUTPUT; > + > + return GPIOF_INPUT; > +} > + > +static const struct dm_gpio_ops eg20t_gpio_ops = { > + .direction_input = eg20t_gpio_direction_input, > + .direction_output = eg20t_gpio_direction_output, > + .get_value = eg20t_gpio_get_value, > + .set_value = eg20t_gpio_set_value, > + .get_function = eg20t_gpio_get_function, > +}; > + > +static int eg20t_gpio_probe(struct udevice *dev) > +{ > + struct eg20t_gpio_priv *priv = dev_get_priv(dev); > + struct gpio_dev_priv *uc_priv = dev->uclass_priv; > + > + priv->base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_1, PCI_REGION_MEM); > + if (!priv->base) { > + debug("failed to map GPIO registers\n"); > + return -EINVAL; > + } > + > + uc_priv->gpio_count = 12; > + uc_priv->bank_name = "eg20t"; > + return 0; > +} > + > +static const struct udevice_id eg20t_gpio_ids[] = { > + { .compatible = "intel,eg20t-gpio" }, > + { } > +}; > + > +U_BOOT_DRIVER(eg20t_gpio) = { > + .name = "eg20t-gpio", > + .id = UCLASS_GPIO, > + .of_match = eg20t_gpio_ids, > + .probe = eg20t_gpio_probe, > + .priv_auto_alloc_size = sizeof(struct eg20t_gpio_priv), > + .ops = &eg20t_gpio_ops, > +}; > + > +static struct pci_device_id eg20t_gpio_supported[] = { > + { PCI_VENDOR_ID_INTEL, 0x8803 }, > + { }, > +}; > + > +U_BOOT_PCI_DEVICE(eg20t_gpio, eg20t_gpio_supported); > -- - Daniel
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