Using the ENV offset from rockchip legacy U-Boot for all SoCs,
the offset is 4MB-32KB
Signed-off-by: Kever Yang
---
include/configs/rockchip-common.h | 15 +++
1 file changed, 3 insertions(+), 12 deletions(-)
diff --git a/include/configs/rockchip-common.h
b/include/configs/rockchi
All Rockchip SoCs use 32KB as CONFIG_ENV_SIZE.
Signed-off-by: Kever Yang
---
include/configs/evb_rk3229.h | 2 --
include/configs/kylin_rk3036.h| 2 --
include/configs/lion_rk3368.h | 1 -
include/configs/rk3036_common.h | 1 -
include/configs/rk3128_common.h | 1 -
include/con
On Tue, Oct 31, 2017 at 5:06 AM, Icenowy Zheng wrote:
> Some H5 boards are designed to start at 1.1V CPUx voltage (e.g. Nano Pi
> NEO2), which may not work properly at 1008MHz if the chip's quality is
> not so good.
>
> Lower the default CPUx frequency of H5 to 816MHz.
>
> Signed-off-by: Icenowy Z
When I use Orange Pi Prime to do some heavy compliation tasks, the gcc
compiler sometimes mysteriously segfaults, and memtester catches memory
error. As the lima-memtester cannot support H5 (Mali-450 GPU equipped),
there's no really reliable way to detect DRAM stability except try and
error.
Lower
On Mon, Oct 30, 2017 at 5:23 PM, Rajat Srivastava
wrote:
>> On Mon, Oct 30, 2017 at 11:52 AM, Jagan Teki
>> wrote:
>> > On Mon, Oct 16, 2017 at 12:54 PM, Rajat Srivastava
>> > wrote:
>> >> The S25FS-S family physical sectors may be configured as a hybrid
>> >> combination of eight 4-kB parameter
在 2017-10-31 15:57，Jagan Teki 写道：
On Tue, Oct 31, 2017 at 5:06 AM, Icenowy Zheng wrote:
Some H5 boards are designed to start at 1.1V CPUx voltage (e.g. Nano
Pi
NEO2), which may not work properly at 1008MHz if the chip's quality is
not so good.
Lower the default CPUx frequency of H5 to 816MHz.
On Tue, Oct 31, 2017 at 03:56:08PM +0800, Icenowy Zheng wrote:
> When I use Orange Pi Prime to do some heavy compliation tasks, the gcc
> compiler sometimes mysteriously segfaults, and memtester catches memory
> error. As the lima-memtester cannot support H5 (Mali-450 GPU equipped),
> there's no re
在 2017-10-31 16:09，Maxime Ripard 写道：
On Tue, Oct 31, 2017 at 03:56:08PM +0800, Icenowy Zheng wrote:
When I use Orange Pi Prime to do some heavy compliation tasks, the gcc
compiler sometimes mysteriously segfaults, and memtester catches
memory
error. As the lima-memtester cannot support H5 (Mali
On Mon, Oct 30, 2017 at 5:12 PM, Marek Vasut wrote:
> On 10/30/2017 12:36 PM, Jagan Teki wrote:
>> On Mon, Oct 30, 2017 at 4:24 PM, Marek Vasut wrote:
>>> On 10/30/2017 07:04 AM, Jagan Teki wrote:
On Sat, Oct 28, 2017 at 5:09 PM, Marek Vasut wrote:
> On 10/27/2017 03:54 PM, Eugeniy Palt
User do not need to access the reserved part in system, remove them
from partition table.
Rename atf to trust as generic name for armv7 do not use ATF.
Signed-off-by: Kever Yang
---
include/configs/rockchip-common.h | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/inclu
On Tue, Oct 31, 2017 at 1:35 PM, wrote:
> 在 2017-10-31 15:57，Jagan Teki 写道：
>>
>> On Tue, Oct 31, 2017 at 5:06 AM, Icenowy Zheng wrote:
>>>
>>> Some H5 boards are designed to start at 1.1V CPUx voltage (e.g. Nano Pi
>>> NEO2), which may not work properly at 1008MHz if the chip's quality is
>>> n
On Tue, Oct 31, 2017 at 1:26 PM, Icenowy Zheng wrote:
> When I use Orange Pi Prime to do some heavy compliation tasks, the gcc
> compiler sometimes mysteriously segfaults, and memtester catches memory
> error. As the lima-memtester cannot support H5 (Mali-450 GPU equipped),
> there's no really rel
于 2017年10月31日 GMT+08:00 下午4:59:34, Jagan Teki
写到:
On Tue, Oct 31, 2017 at 1:26 PM, Icenowy Zheng wrote:
When I use Orange Pi Prime to do some heavy compliation tasks, the
gcc
compiler sometimes mysteriously segfaults, and memtester catches
memory
error. As the lima-memtester cannot suppo
于 2017年10月31日 GMT+08:00 下午4:53:57, Jagan Teki
写到:
On Tue, Oct 31, 2017 at 1:35 PM, wrote:
在 2017-10-31 15:57，Jagan Teki 写道：
On Tue, Oct 31, 2017 at 5:06 AM, Icenowy Zheng
wrote:
Some H5 boards are designed to start at 1.1V CPUx voltage (e.g.
Nano Pi
NEO2), which may not work properl
On Tue, Oct 24, 2017 at 3:33 PM, Siva Durga Prasad Paladugu
wrote:
> This patch adds qspi driver support for ZynqMP SoC. This
> driver is responsible for communicating with qspi flash
> devices.
Legacy question, what is your approach for dual memory setup? Did you
write another flash driver?
I s
Hi Marek,
> -Original Message-
> From: Marek Vasut [mailto:ma...@denx.de]
> Sent: Monday, October 30, 2017 6:55 PM
> To: Ran Wang
> Cc: bmeng...@gmail.com
> Subject: Re: About the way to fix platform specific issue in source file
> xhci.c
> (U-Boot)
>
> On 10/30/2017 09:39 AM, Ran Wang
On Tue, Oct 31, 2017 at 2:50 PM, Siva Durga Prasad Paladugu
wrote:
> Hi Jagan,
>
>> -Original Message-
>> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
>> Sent: Tuesday, October 31, 2017 2:40 PM
>> To: Siva Durga Prasad Paladugu
>> Cc: u-boot@lists.denx.de; Liam Beguin ; Siva
>> Durg
On 10/31/2017 10:15 AM, Ran Wang wrote:
> Hi Marek,
Hi!
>> -Original Message-
>> From: Marek Vasut [mailto:ma...@denx.de]
>> Sent: Monday, October 30, 2017 6:55 PM
>> To: Ran Wang
>> Cc: bmeng...@gmail.com
>> Subject: Re: About the way to fix platform specific issue in source file
>> xh
On 10/31/2017 09:27 AM, Jagan Teki wrote:
> On Mon, Oct 30, 2017 at 5:12 PM, Marek Vasut wrote:
>> On 10/30/2017 12:36 PM, Jagan Teki wrote:
>>> On Mon, Oct 30, 2017 at 4:24 PM, Marek Vasut wrote:
On 10/30/2017 07:04 AM, Jagan Teki wrote:
> On Sat, Oct 28, 2017 at 5:09 PM, Marek Vasut w
Hi
> -Original Message-
> From: Marek Vasut [mailto:marek.va...@gmail.com]
> Sent: Tuesday, October 31, 2017 5:31 PM
> To: Ran Wang ; Marek Vasut
> Cc: open list
> Subject: Re: [U-Boot] About the way to fix platform specific issue in source
> file xhci.c (U-Boot)
>
> On 10/31/2017 10:15
Hi Tom, Stefan,
On 31/10/2017 03:47, Tom Rini wrote:
> On Mon, Oct 30, 2017 at 09:59:04AM +0100, Stefan Agner wrote:
>> Hi Tom, Stefano,
>>
>> Any chance to get this still into 2017.11? It allows to use 2017.11 on
>> my board...
>
> Stefano, this is your call, thanks!
I looking into the list to
Hi all,
I just noticed that commit [1] breaks e-mmc support for db410c.
If you need emmc access you can work around it by reducing the timeout
on completion (to just a few tenths of usecs) and returning 0 instead of
-ETIMEDOUT.
I am trying to understand why the condition is not met as per th
Please see inline, fixing all comments in next version.
Regards
Ashish
-Original Message-
From: York Sun
Sent: Monday, October 30, 2017 8:25 PM
To: Ashish Kumar ; u-boot@lists.denx.de
Cc: Raghav Dogra ; Prabhakar Kushwaha
Subject: Re: [u-boot-release] [Patch V4 1/2] armv8: ls1088ardb:
Hi Fabio,
On 30/10/2017 23:42, Fabio Estevam wrote:
> Hi Stefano,
>
> On Fri, Oct 13, 2017 at 10:27 AM, Fabio Estevam wrote:
>> From: Fabio Estevam
>>
>> Commit 001cdbbb32ef1f6 ("imx: mx6slevk: enable more DM drivers") breaks
>> MMC support in U-Boot proper on the mx6slevk_spl_defconfig target:
On 30/10/2017 19:47, Otavio Salvador wrote:
> On Sat, Oct 14, 2017 at 9:17 AM, Fabio Estevam wrote:
>> From: Fabio Estevam
>>
>> Add support for the latest MX6QP wandboard variant.
>>
>> Based on Richard Hu's work from Technexion's U-Boot tree.
>>
>> Signed-off-by: Fabio Estevam
>
> Stefano, pl
On Tue, Oct 31, 2017 at 04:17:06PM +0800, icen...@aosc.io wrote:
> 在 2017-10-31 16:09，Maxime Ripard 写道：
> > On Tue, Oct 31, 2017 at 03:56:08PM +0800, Icenowy Zheng wrote:
> > > When I use Orange Pi Prime to do some heavy compliation tasks, the gcc
> > > compiler sometimes mysteriously segfaults, an
On 10/31/2017 10:43 AM, Ran Wang wrote:
> Hi
>> -Original Message-
>> From: Marek Vasut [mailto:marek.va...@gmail.com]
>> Sent: Tuesday, October 31, 2017 5:31 PM
>> To: Ran Wang ; Marek Vasut
>> Cc: open list
>> Subject: Re: [U-Boot] About the way to fix platform specific issue in source
Hi Jagan,
> -Original Message-
> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
> Sent: Tuesday, October 31, 2017 2:40 PM
> To: Siva Durga Prasad Paladugu
> Cc: u-boot@lists.denx.de; Liam Beguin ; Siva
> Durga Prasad Paladugu
> Subject: Re: [UBOOT PATCH 1/2] spi: zynqmp_qspi: Add sup
Hi,
We are currently integrating a new board fitted with Micron NOR Flash
(MT28EW01GABA) and the current u-boot baseline is having issues in protecting
the flash (hangs indefinitely during startup when CONFIG_SYS_FLASH_PROTECTION
is enabled) and timeouts during erase. By contrast, a somewhat ol
在 2017-10-31 18:21，Maxime Ripard 写道：
On Tue, Oct 31, 2017 at 04:17:06PM +0800, icen...@aosc.io wrote:
在 2017-10-31 16:09，Maxime Ripard 写道：
> On Tue, Oct 31, 2017 at 03:56:08PM +0800, Icenowy Zheng wrote:
> > When I use Orange Pi Prime to do some heavy compliation tasks, the gcc
> > compiler some
Hi Nikolay,
On 10/10/2017 16:27, Nikolay Petukhov wrote:
> Hi, all
>
> This patch enables HDMI on CPU without VPU.
> A similar patch for the mainline
> kernel:https://patchwork.kernel.org/patch/9874831/
> Tested on MCIMX6Q4AVT10AD.
>
This is stored in the commit message if I apply. Please rewri
From: Tien Fong Chee
This patch adds description on properties about location of FPGA RBFs are
stored, type and functionality of RBF used to configure FPGA.
Signed-off-by: Tien Fong Chee
---
doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt | 11 +++
1 file changed, 11 inse
From: Tien Fong Chee
This patchset adding FPGA and SDRAM drivers, enable fpga loadfs to program FPGA
, SPL loading U-boot and booting to U-boot console. This version mainly resolved
comments from Dinh and Marek in [v3].
This series is working on top of u-boot-socfpga.git -
http://git.denx.de/u-b
From: Tien Fong Chee
fpga-mgr node is required in SPL, because SPL needs information
from the node to configure FPGA in Arria 10.
Signed-off-by: Tien Fong Chee
---
arch/arm/dts/socfpga_arria10.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/socfpga_arria10.dtsi
b/arch/ar
From: Tien Fong Chee
These FPGA bitstream properties would help bootloader to understand
how to configure FPGA and where to look the FPGA RBF files during
booting.
Signed-off-by: Tien Fong Chee
---
arch/arm/dts/socfpga_arria10.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/
From: Tien Fong Chee
Commit 2baa997240d ("arm: socfpga: Add FPGA driver support for Arria 10")
Polling on wrong cleared bit. Fix with correct polling on bit is set.
Fixes: 2baa997240d ("arm: socfpga: Add FPGA driver support for Arria 10")
Signed-off-by: Tien Fong Chee
---
drivers/fpga/socfpga
From: Tien Fong Chee
Current sdram driver is only applied to gen5 device, hence it is better
to rename sdram driver to more specific name which is related to gen5
device.
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/include/mach/sdram.h | 432 +
.../inclu
From: Tien Fong Chee
This patch enables DDR Kconfig support for Arria 10.
Signed-off-by: Tien Fong Chee
Reviewed-by: Dinh Nguyen
---
arch/arm/mach-socfpga/Kconfig | 1 +
drivers/ddr/altera/Kconfig| 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/K
From: Tien Fong Chee
Adding some details about size in bytes to each section.
Signed-off-by: Tien Fong Chee
Reviewed-by: Dinh Nguyen
---
arch/arm/mach-socfpga/include/mach/boot0.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/boot0.
From: Tien Fong Chee
Enable generic filesystem interface drivers(fs.c and fat/) build
for SPL. This would allow generic filesystem being used in SPL.
Signed-off-by: Tien Fong Chee
Reviewed-by: Simon Glass
---
common/spl/Kconfig | 8
doc/README.SPL | 1 +
fs/Makefile| 1 +
From: Tien Fong Chee
Enable memory allocation in SPL for preparation to enable FAT
in SPL. Memory allocation is needed by FAT to work properly.
Signed-off-by: Tien Fong Chee
Reviewed-by: Dinh Nguyen
---
include/configs/socfpga_common.h | 22 +-
1 file changed, 21 insertion
From: Tien Fong Chee
Add function for both multiple DRAM bank and single DRAM bank size
initialization. This common functionality could be used by every single
SOCFPGA board.
Signed-off-by: Tien Fong Chee
Tested-by: Ley Foon Tan
---
arch/arm/mach-socfpga/board.c| 7 +++
include/config
From: Tien Fong Chee
This patch removes the static declation on spl_mmc_find_device_function
so this function is accessible by the caller from other file. This patch
is required for later patch.
Signed-off-by: Tien Fong Chee
---
common/spl/spl_mmc.c | 2 +-
include/spl.h| 2 ++
2 files
From: Tien Fong Chee
Enhance preloader header with both additional program length and program
entry offset attributes, which offset is relative to the start of program
header.
Signed-off-by: Tien Fong Chee
Reviewed-by: Dinh Nguyen
---
arch/arm/mach-socfpga/include/mach/boot0.h | 7 +++
1
From: Tien Fong Chee
Add DDR driver support for Arria 10.
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/include/mach/sdram.h | 2 +
arch/arm/mach-socfpga/include/mach/sdram_arria10.h | 2 +
drivers/ddr/altera/Makefile| 1 +
drivers/ddr/altera/sdr
From: Tien Fong Chee
Enable SPL successfully boot to U-boot.
Signed-off-by: Tien Fong Chee
---
configs/socfpga_arria10_defconfig | 41 ++-
1 file changed, 36 insertions(+), 5 deletions(-)
diff --git a/configs/socfpga_arria10_defconfig
b/configs/socfpga_arr
From: Tien Fong Chee
Clock frequency info is required in U-Boot because info would be erased
when transition from SPL to U-Boot.
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/board.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/m
From: Tien Fong Chee
SPL configures DDR by programming peripheral raw binary file
and calibrating DDR.
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/spl.c | 48 +++
configs/socfpga_arria10_defconfig | 15 +---
2 files changed, 60 inse
From: Tien Fong Chee
SoC FPGA info is required in both SPL and U-Boot.
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/board.c| 4
arch/arm/mach-socfpga/misc_arria10.c | 5 -
arch/arm/mach-socfpga/spl.c | 6 ++
3 files changed, 10 insertions(+), 5 deletion
Hi Tom,
please pull these fixes from u-boot-imx, thanks !
The following changes since commit b79372ae94fbc9e30d014ad8ce830d2062539eb9:
scripts/get_maintainer.pl: enable find_maintainer_files (2017-10-29
10:13:10 -0400)
are available in the git repository at:
git://www.denx.de/git/u-boot-im
From: Tien Fong Chee
Generic firmware loader framework contains some common functionality
which is reusable by any specific driver file system firmware loader.
Specific driver file system firmware loader handling can be defined
with both weak function fsloader_preprocess and fs_loading.
Signed-o
From: Tien Fong Chee
Add FPGA drivers to support FPGA loadfs to program FPGA.
The drivers are designed based on generic firmware loader framework,
specific firmware loader handling is defined in fpga_manager_arria10.c.
These drivers can handle FPGA program operation from
loading RBF image in flas
From: Tien Fong Chee
Add code necessary into the FPGA driver framework in U-Boot
so it can be used via the 'fpga' command for programing Arria 10
SoCFPGA.
Signed-off-by: Tien Fong Chee
---
cmd/fpga.c| 2 +-
drivers/fpga/altera.c | 40
drive
On 10/31/2017 11:52 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> Generic firmware loader framework contains some common functionality
> which is reusable by any specific driver file system firmware loader.
> Specific driver file system firmware loader handling can be defined
> w
On 10/31/2017 11:48 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> Add code necessary into the FPGA driver framework in U-Boot
> so it can be used via the 'fpga' command for programing Arria 10
> SoCFPGA.
>
> Signed-off-by: Tien Fong Chee
Why am I receiving this email outside o
On 10/31/2017 11:52 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> Generic firmware loader framework contains some common functionality
> which is reusable by any specific driver file system firmware loader.
> Specific driver file system firmware loader handling can be defined
> w
On Sel, 2017-10-31 at 12:02 +0100, Marek Vasut wrote:
> On 10/31/2017 11:48 AM, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Add code necessary into the FPGA driver framework in U-Boot
> > so it can be used via the 'fpga' command for programing Arria 10
> > SoCFPGA.
> >
On Sel, 2017-10-31 at 12:01 +0100, Marek Vasut wrote:
> On 10/31/2017 11:52 AM, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Generic firmware loader framework contains some common
> > functionality
> > which is reusable by any specific driver file system firmware
> > load
On Sel, 2017-10-31 at 12:02 +0100, Marek Vasut wrote:
> On 10/31/2017 11:52 AM, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Generic firmware loader framework contains some common
> > functionality
> > which is reusable by any specific driver file system firmware
> > load
Hi Joe,
On Mon, Oct 30, 2017 at 9:42 PM, Fabio Estevam wrote:
> Do you think this one can be applied for 2017.11?
Stefano has applied it:
http://git.denx.de/?p=u-boot/u-boot-imx.git;a=commit;h=41b93679fd69bbb8c335eb212a3f8aa6c9c662db
Thanks
___
U-Boo
On 10/31/2017 12:15 PM, Chee, Tien Fong wrote:
> On Sel, 2017-10-31 at 12:01 +0100, Marek Vasut wrote:
>> On 10/31/2017 11:52 AM, tien.fong.c...@intel.com wrote:
>>>
>>> From: Tien Fong Chee
>>>
>>> Generic firmware loader framework contains some common
>>> functionality
>>> which is reusable by a
On 10/31/2017 12:16 PM, Chee, Tien Fong wrote:
> On Sel, 2017-10-31 at 12:02 +0100, Marek Vasut wrote:
>> On 10/31/2017 11:52 AM, tien.fong.c...@intel.com wrote:
>>>
>>> From: Tien Fong Chee
>>>
>>> Generic firmware loader framework contains some common
>>> functionality
>>> which is reusable by a
Dear Stefano,
> Hi Lukasz,
>
> On 20/10/2017 14:46, Lukasz Majewski wrote:
> > This commit provides support for LWN's IMX6Q based DISPLAY5 board.
> >
> > Signed-off-by: Lukasz Majewski
> > ---
> >
> > arch/arm/dts/imx6q-display5.dts | 18 ++
> > arch/arm/mach-imx/mx6/Kconfig | 7
On Sel, 2017-10-31 at 12:35 +0100, Marek Vasut wrote:
> On 10/31/2017 12:16 PM, Chee, Tien Fong wrote:
> >
> > On Sel, 2017-10-31 at 12:02 +0100, Marek Vasut wrote:
> > >
> > > On 10/31/2017 11:52 AM, tien.fong.c...@intel.com wrote:
> > > >
> > > >
> > > > From: Tien Fong Chee
> > > >
> > > >
On Sel, 2017-10-31 at 12:35 +0100, Marek Vasut wrote:
> On 10/31/2017 12:15 PM, Chee, Tien Fong wrote:
> >
> > On Sel, 2017-10-31 at 12:01 +0100, Marek Vasut wrote:
> > >
> > > On 10/31/2017 11:52 AM, tien.fong.c...@intel.com wrote:
> > > >
> > > >
> > > > From: Tien Fong Chee
> > > >
> > > >
Hello,
Since I've been supporting a u-boot for the Renesas RZ/A1 SoC for a
while now, I thought I'd start upstreaming the drivers/patches I've acquired
over the years.
But, where should the core files and Kconfig go?
The RZ/A1 series has a Cortex-A9.
At first, I had made a directory under arch
This series adds support for the GE PPD. The initial patches in this
series resolve issues found during development and testing, extend
existing support and add new support for devices in the PPD. The final
patch in the series adds the board support for the PPD.
Ian Ray (2):
ext4: recover from f
From: Nandor Han
Add support for S35392A RTC. The driver supports both U-Boot driver
models.
Signed-off-by: Nandor Han
Signed-off-by: Martyn Welch
Cc: Heiko Schocher
---
drivers/rtc/Kconfig | 6 +
drivers/rtc/Makefile | 1 +
drivers/rtc/s35392a.c | 360
Add register definitions require for video configuration.
Signed-off-by: Nandor Han
Signed-off-by: Martyn Welch
Cc: Stefano Babic
---
arch/arm/include/asm/arch-mx5/crm_regs.h | 9 +
arch/arm/include/asm/arch-mx5/imx-regs.h | 28
2 files changed, 37 inserti
From: Peter Senna Tschudin
Create board support for GE PPD, based on mx53loco.
Use mx53ppd_defconfig make target to configure for this board.
Signed-off-by: Peter Senna Tschudin
Signed-off-by: Ian Ray
Signed-off-by: Nandor Han
Signed-off-by: Martyn Welch
Cc: Stefano Babic
---
Changes for v
From: Ian Ray
Add support for bootcounter on an EXT filesystem.
Sync configuration whitelist.
Signed-off-by: Ian Ray
Signed-off-by: Martyn Welch
---
Changes for v2:
- Adding Kconfig for EXT bootcount.
README| 7 +
drivers/Kconfig | 2 ++
From: Ian Ray
Some fixes when reading EXT files and directory entries were identified
after using e2fuzz to corrupt an EXT3 filesystem:
- Stop reading directory entries if the offset becomes badly aligned.
- Avoid overwriting memory by clamping the length used to zero the buffer
in ext4fs_
From: Nandor Han
Tweak the i2c transfer to work for devices that want to read data
without addressing a register.
Signed-off-by: Nandor Han
Signed-off-by: Martyn Welch
Cc: Heiko Schocher
Cc: Stefano Babic
---
Changes for v2:
- Replacing '!= -1' with '>= 0'.
drivers/i2c/mxc_i2c.c | 25 ++
Add missing parts for i.MX53 PWM support
Acked-by: Nandor Han
Signed-off-by: Martyn Welch
Cc: Stefano Babic
---
arch/arm/include/asm/arch-mx5/imx-regs.h | 19 +++
drivers/pwm/pwm-imx-util.c | 2 ++
2 files changed, 21 insertions(+)
diff --git a/arch/arm/include/
This commit provides generic function to set the RGMII/HSIC IO voltage
level on iMX6 devices.
Signed-off-by: Lukasz Majewski
---
arch/arm/include/asm/arch-mx6/iomux.h | 13 +
arch/arm/include/asm/arch-mx6/sys_proto.h | 11 +++
2 files changed, 24 insertions(+)
diff --gi
Hello Martyn,
Am 31.10.2017 um 13:16 schrieb Martyn Welch:
From: Nandor Han
Tweak the i2c transfer to work for devices that want to read data
without addressing a register.
Signed-off-by: Nandor Han
Signed-off-by: Martyn Welch
Cc: Heiko Schocher
Cc: Stefano Babic
---
Changes for v2:
-
> -Original Message-
> From: Heiko Schocher [mailto:h...@denx.de]
> Sent: 31 October 2017 06:28
> To: Martyn Welch
> Cc: u-boot@lists.denx.de; Han, Nandor (GE Healthcare)
> ; Martyn Welch ;
> Stefano Babic
> Subject: EXT: Re: [PATCH 1/7] imx: mxc_i2c: tweak the i2c transfer method
>
>
On Tue, Oct 31, 2017 at 06:22:51PM +0800, Icenowy Zheng wrote:
> 在 2017-10-31 18:21，Maxime Ripard 写道：
> > On Tue, Oct 31, 2017 at 04:17:06PM +0800, icen...@aosc.io wrote:
> > > 在 2017-10-31 16:09，Maxime Ripard 写道：
> > > > On Tue, Oct 31, 2017 at 03:56:08PM +0800, Icenowy Zheng wrote:
> > > > > When
On Tue, Oct 31, 2017 at 04:05:36PM +0800, icen...@aosc.io wrote:
> 在 2017-10-31 15:57，Jagan Teki 写道：
> > On Tue, Oct 31, 2017 at 5:06 AM, Icenowy Zheng wrote:
> > > Some H5 boards are designed to start at 1.1V CPUx voltage (e.g. Nano
> > > Pi
> > > NEO2), which may not work properly at 1008MHz if
Hey all,
It's the morning after release day and v2017.11-rc3 is out. I tagged
and pushed last night, but forgot to hit send on the email. I see a few
bug fixes that've come by recently and I expect to grab, but things look
otherwise quiet and on track for rc4 on November 6th and release on the
1
On Sun, Oct 29, 2017 at 7:08 PM, Benoît Thébaudeau
wrote:
> The following error has been observed on i.MX25 with a high-speed SDSC
> card:
> Data Write Failed in PIO Mode.
>
> It was caused by the timeout set on PRSSTAT.BWEN, which was triggered
> because this bit takes 15 ms to be set after w
On 10/31/2017 02:55 AM, Ashish Kumar wrote:
> Signed-off-by: Ashish Kumar
> Signed-off-by: Amrita Kumari
> ---
> v2: Rebase to top
> v3: Consolidate defines in common file
>
> include/configs/ls1088a_common.h | 11 +++
> 1 file changed, 11 insertions(+)
>
> diff --git a/include/configs
On Tue, Oct 31, 2017 at 12:13:22PM +, Chris Brandt wrote:
> Hello,
>
> Since I've been supporting a u-boot for the Renesas RZ/A1 SoC for a
> while now, I thought I'd start upstreaming the drivers/patches I've acquired
> over the years.
>
> But, where should the core files and Kconfig go?
>
On Mon, Oct 30, 2017 at 2:38 AM, Benoît Thébaudeau
wrote:
> The following error has been observed on i.MX25 with a high-speed SDSC
> card:
> Data Write Failed in PIO Mode.
>
> It was caused by the timeout set on PRSSTAT.BWEN, which was triggered
> because this bit takes 15 ms to be set after w
Hi Jagan,
> -Original Message-
> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
> Sent: Tuesday, October 31, 2017 3:01 PM
> To: Siva Durga Prasad Paladugu
> Cc: u-boot@lists.denx.de; Liam Beguin
> Subject: Re: [UBOOT PATCH 1/2] spi: zynqmp_qspi: Add support for
> ZynqMP qspi driver
>
Hi everyone,
I'm currently using a UBIFS root file system (stored on SPI-NOR flash)
and would like to perform a full integrity check before booting it.
The rootfs is read-only and until now, I've been computing an md5sum on
the whole mtd device from an initramfs and comparing it to a stored
md5su
Hi Tom,
Thanks for the reply!
On Tuesday, October 31, 2017 1, Tom Rini wrote:
> On Tue, Oct 31, 2017 at 12:13:22PM +, Chris Brandt wrote:
> > Hello,
> >
> > Since I've been supporting a u-boot for the Renesas RZ/A1 SoC for a
> > while now, I thought I'd start upstreaming the drivers/patches I
This commit provides support for LWN's IMX6Q based DISPLAY5 board.
Signed-off-by: Lukasz Majewski
---
Changes in v4:
- Refactor obscure sw/hw rev code for display5 board
- replace get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); with
imx_ddr_size()
- remove PHYS_SDRAM_SIZE from d
Am 31.10.2017 um 00:58 schrieb Paul Burton:
> MIPS is no longer a part of Imagination Technologies, and as such my
> @imgtec.com email address will soon cease to function. This patch
> updates occurrances of it with my new @mips.com email address, and adds
> an entry in .mailmap such that git (&
Hi Tom,
On Thu, Oct 26, 2017 at 10:09:10AM -0400, Tom Rini wrote:
> On Thu, Oct 26, 2017 at 10:38:45AM +0200, Maxime Ripard wrote:
> > Hi Tom,
> >
> > Thanks for your feedback.
> >
> > On Wed, Oct 25, 2017 at 11:32:03AM -0400, Tom Rini wrote:
> > > On Wed, Oct 25, 2017 at 02:25:57PM +0200, Maxim
Hi Wolfgang,
On Wed, Oct 25, 2017 at 05:26:46PM +0200, Wolfgang Denk wrote:
> Dear Maxime,
>
> In message <20171025122601.28224-4-maxime.rip...@free-electrons.com> you
> wrote:
> > The current environment has been hardcoded to an offset that starts to be
> > an issue given the current size of ou
On Tue, Oct 31, 2017 at 4:18 PM, Jagan Teki wrote:
> On Mon, Oct 30, 2017 at 2:38 AM, Benoît Thébaudeau
> wrote:
>> The following error has been observed on i.MX25 with a high-speed SDSC
>> card:
>> Data Write Failed in PIO Mode.
>>
>> It was caused by the timeout set on PRSSTAT.BWEN, which w
Alexey,
I tested the patch on PowerPC. Seems to work fine, but you have to make sure
to set the proper order of arguments for when the EHCI registers are big
endian: __raw_writel(cpu_to_be32(b), a)
To test this patch I had to verify that __raw_ functions are supported for
PowerPC, so I created
> Remove CONFIG_ENV_OFFSET for there already have one in rockchip_common.h
>
> Signed-off-by: Kever Yang
> ---
>
> include/configs/evb_rk3328.h | 6 --
> 1 file changed, 6 deletions(-)
>
Acked-by: Philipp Tomsich
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> The API for get priv pointer is wrong, fix it.
>
> Signed-off-by: Kever Yang
> ---
>
> arch/arm/mach-rockchip/rk3328/clk_rk3328.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Acked-by: Philipp Tomsich
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> The RK3368-uQ7 uses a KSZ9031 PHY on-module. Enable PHY_MICREL_KSZ90X1
> in the associated defconfig.
>
> References: da3b9e7f ("Move PHY_MICREL and PHY_MICREL_KSZ90X1 to Kconfig")
> Signed-off-by: Philipp Tomsich
> ---
>
> configs/lion-rk3368_defconfig | 1 +
> 1 file changed, 1 insertion(+
> Init the CPU and its buses to speed up the boot time.
> Move rkclk_init() to a place after rk3399_configure_cpu has defined
> at the same time, or else there will be a warning.
>
> Signed-off-by: Kever Yang
> Reviewed-by: Simon Glass
> ---
>
> drivers/clk/rockchip/clk_rk3399.c | 157
> +
> The RK3368-uQ7 uses a KSZ9031 PHY on-module. Enable PHY_MICREL_KSZ90X1
> in the associated defconfig (this somehow got lost with da3b9e7f).
>
> References: da3b9e7f ("Move PHY_MICREL and PHY_MICREL_KSZ90X1 to Kconfig")
> Signed-off-by: Philipp Tomsich
> ---
>
> configs/puma-rk3399_defconfig
> Remove CONFIG_ENV_OFFSET for there already have one in rockchip_common.h
>
> Signed-off-by: Kever Yang
> ---
>
> include/configs/evb_rk3328.h | 6 --
> 1 file changed, 6 deletions(-)
>
Reviewed-by: Philipp Tomsich
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U-Boot mailing list
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> Init the CPU and its buses to speed up the boot time.
> Move rkclk_init() to a place after rk3399_configure_cpu has defined
> at the same time, or else there will be a warning.
>
> Signed-off-by: Kever Yang
> Reviewed-by: Simon Glass
> ---
>
> drivers/clk/rockchip/clk_rk3399.c | 157
> +
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