On Tue, Oct 25, 2016 at 3:59 AM, André Przywara wrote:
> On 21/10/16 11:28, Hans de Goede wrote:
>> Hi,
>>
>> On 21-10-16 12:06, Andre Przywara wrote:
>>> Hi,
>>>
>>> On 21/10/16 10:31, Jagan Teki wrote:
On Fri, Oct 21, 2016 at 5:41 AM, Andre Przywara
wrote:
> The sun8i-emac driver
On Thu, Oct 20, 2016 at 5:08 PM, S Durga Prasad Paladugu
wrote:
> Hi Jagan,
>
> On Wed, Jul 27, 2016 at 3:26 PM, Jagan Teki
> wrote:
>>
>> On 27 July 2016 at 14:31, Siva Durga Prasad Paladugu
>> wrote:
>> > Hi Jagan,
>> >
>> >> -Original Message-
>> >> From: Jagan Teki [mailto:jagannadh.
On Fri, Oct 14, 2016 at 4:18 PM, R, Vignesh wrote:
>
>
> On 10/14/2016 12:27 PM, Jagan Teki wrote:
>> On Fri, Oct 14, 2016 at 10:54 AM, Vignesh R wrote:
> ...
> DECLARE_GLOBAL_DATA_PTR;
>
> @@ -118,7 +119,7 @@ static void ti_spi_set_speed(struct ti_qspi_priv
> *priv, uint hz)
>>
On 10/26/2016 02:07 AM, André Przywara wrote:
On 25/10/16 08:52, Alexander Graf wrote:
Hi Alex,
thanks for looking at this!
On 25/10/2016 02:51, Andre Przywara wrote:
On systems using the generic timer routines defined in lib/time.c we
use timebase_l and timebase_h fields from the gd to dete
On Fri, Oct 14, 2016 at 8:49 AM, Chris Packham wrote:
> Set the appropriate bits in the interface config register based
> on the SPI_ mode flags.
>
> Signed-off-by: Chris Packham
> ---
>
> arch/arm/include/asm/arch-mvebu/spi.h | 4
> drivers/spi/kirkwood_spi.c| 13 +
The purpose of this patch set is to add the pinctrl driver for AT91
PIO controller.
Changes in v3:
- Add support for OUTPUT config
Changes in v2:
- Add more information for the PINCTRL_AT91 option's help.
- Add more comments for the callback of struct at91_pinctrl_mux_ops.
- Use clrsetbits_le
The intention of this patch is the preparation to introduce
the pinctrl driver for AT91 PIO.
Use "union" to make the PIO3 and PIO2's registers be together
and make their offset aligned.
Signed-off-by: Wenyou Yang
---
Changes in v3: None
Changes in v2: None
arch/arm/mach-at91/include/mach/at91
AT91 PIO controller is a combined gpio-controller, pin-mux and
pin-config module. The peripheral's pins are assigned through
per-pin based muxing logic.
Each soc will have to describe the SoC limitation and pin
configuration via DT. This will allow to do not need to touch
the C code when adding ne
To keep the compatibles aligned with kernel, add more compatibles.
Signed-off-by: Wenyou Yang
---
drivers/clk/at91/pmc.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/clk/at91/pmc.c b/drivers/clk/at91/pmc.c
index 76ba91a..f866959 100644
--- a/drivers/clk/at91/pmc.c
+++ b/dri
On Wed, Sep 28, 2016 at 4:39 PM, Yuan Yao wrote:
> From: Yuan Yao
>
> The QSPI support the direct 4bytes address command for flash
> read/write/erase.
> And the address can cover the whole QSPI memory space.
>
> Signed-off-by: Yuan Yao
> ---
> drivers/spi/fsl_qspi.c | 8 ++--
> 1 file chang
Hi,
On 26-10-16 09:00, Jagan Teki wrote:
On Tue, Oct 25, 2016 at 3:59 AM, André Przywara wrote:
On 21/10/16 11:28, Hans de Goede wrote:
Hi,
On 21-10-16 12:06, Andre Przywara wrote:
Hi,
On 21/10/16 10:31, Jagan Teki wrote:
On Fri, Oct 21, 2016 at 5:41 AM, Andre Przywara
wrote:
The sun8i-
Hi,
On 10/24/2016 11:13 PM, Simon Glass wrote:
> On 24 October 2016 at 10:24, Sylvain Lesne wrote:
>>
>> (Also, this is kind of unrelated, but it looks like the error
>> message 'MMC: block number 0xx exceeds max(0xx)' has a formatting
>> issue!)
>>
>> ---
>> drivers/mmc/socfpga_dw_mmc.c | 2 ++
In case we want to force a particular value on a regulator
irrespective of the min/max constraints for testing purposes
one can call regulator_set_value_force function.
Signed-off-by: Keerthy
---
cmd/regulator.c| 5 -
drivers/power/regulator/regulator-uclass.c |
Currently the specific set ops functions are directly
called without any check for voltage limits for a regulator.
Check for them and proceed.
Signed-off-by: Keerthy
---
drivers/power/regulator/regulator-uclass.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/power/regulator/re
On Wed, Oct 12, 2016 at 7:45 PM, wrote:
> From: Radu Bacrau
>
> This commit adds support for the Macronix MX66U51235F, MX66L1G45G and Micron
> MT25QU02G flash parts.
>
> Signed-off-by: Radu Bacrau
> Cc: Chin Liang See
> Cc: Dinh Nguyen
> Cc: Jagan Teki
> Cc: Radu Bacrau
> ---
> drivers/mt
Currently the specific set ops functions are directly
called without any check for min/max current limits for a regulator.
Check for them and proceed.
Signed-off-by: Keerthy
---
drivers/power/regulator/regulator-uclass.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/power/regu
On Wed, Sep 28, 2016 at 4:39 PM, Yuan Yao wrote:
> From: Yuan Yao
>
> Some new flash don't support bar register but use 4bytes address to
> support exceed 16MB flash size.
> So add flash flag:
> ADDR_4B
> for some flash which support 4bytes address.
>
> Signed-off-by: Yuan Yao
> ---
> drivers/m
On Wed, Oct 26, 2016 at 3:39 PM, Jagan Teki wrote:
> On Wed, Sep 28, 2016 at 4:39 PM, Yuan Yao wrote:
> > From: Yuan Yao
> >
> > The QSPI support the direct 4bytes address command for flash
> > read/write/erase.
> > And the address can cover the whole QSPI memory space.
> >
> > Signed-off-by: Yua
The dts file is copied from the kernel, do the following changes.
- add reg property for pinctrl node.
- move the gpio (pioA, pioB, pioC ...) nodes from the pinctrl
child's nodes to its slibling nodes.
- add pinctrl node for the cs pin of spi0.
- fix the compile warning.
Signed-off-by: Weny
The purpose of the patchset is add the dts files for boards,
sama5d4 Xplained board and sama5d4ek board.
Wenyou Yang (2):
ARM: dts: at91: add dts file for sama5d4 Xplained board
ARM: dts: at91: add dts file for sama5d4ek board
arch/arm/dts/Makefile |6 +
arch/arm/dts/at
The dts file is copied from the kernel, do the following changes.
- add pinctrl node for the cs pin of spi0.
- fix the compile warning.
Signed-off-by: Wenyou Yang
---
arch/arm/dts/Makefile | 3 +
arch/arm/dts/at91-sama5d4ek.dts | 340
2 fil
If enabled Driver Model for GPIO, CONFIG_AT91_GPIO should be defined
by configs/*_defconfig file.
Signed-off-by: Wenyou Yang
---
include/configs/at91-sama5_common.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/configs/at91-sama5_common.h
b/include/configs/at91-sama5_common.h
i
The purpose of patch set is to convert the board to support Device
Tree and Driver Model.
They are based on the following patches:
1./ [PATCH v3 0/2] pinctrl: at91: Add pinctrl driver
http://lists.denx.de/pipermail/u-boot/2016-October/270991.html
2./ [PATCH v1 0/2] ARM: dts
On Wednesday 12 October 2016 11:14 AM, Keerthy wrote:
On Tuesday 11 October 2016 05:49 AM, Simon Glass wrote:
Hi Keerthy,
On 15 September 2016 at 05:16, Keerthy wrote:
On Thursday 15 September 2016 04:38 PM, Keerthy wrote:
On Thursday 15 September 2016 04:26 PM, Przemyslaw Marczak w
Move the config options to configs/sama5d4_xplained_*_defconfig files.
Signed-off-by: Wenyou Yang
---
board/atmel/sama5d4_xplained/sama5d4_xplained.c | 2 ++
configs/sama5d4_xplained_mmc_defconfig | 24 +++-
configs/sama5d4_xplained_nandflash_defconfig| 26
Enable early debug UART to debug problems when an ICE or other
debug mechanism is not available.
Signed-off-by: Wenyou Yang
---
board/atmel/sama5d4_xplained/sama5d4_xplained.c | 15 ++-
configs/sama5d4_xplained_mmc_defconfig | 6 ++
configs/sama5d4_xplained_nandflash_d
Move the config options to configs/sama5d4ek_*_defconfig files.
Signed-off-by: Wenyou Yang
---
board/atmel/sama5d4ek/sama5d4ek.c | 2 ++
configs/sama5d4ek_mmc_defconfig | 24 +++-
configs/sama5d4ek_nandflash_defconfig | 24 +++-
configs/sama5d4
Since the introduction of pinctrl and clk driver, and the dts file,
remove unneeded the pin configurations and the clock enabling code.
Signed-off-by: Wenyou Yang
---
board/atmel/sama5d4_xplained/sama5d4_xplained.c | 109 +---
1 file changed, 1 insertion(+), 108 deletions(-)
Since the introduction of pinctrl and clk driver, and the dts file,
remove unneeded the pin configurations and the clock enabling code.
Signed-off-by: Wenyou Yang
---
board/atmel/sama5d4ek/sama5d4ek.c | 111 +-
1 file changed, 1 insertion(+), 110 deletions(-)
Enable early debug UART to debug problems when an ICE or other
debug mechanism is not available.
Signed-off-by: Wenyou Yang
---
board/atmel/sama5d4ek/sama5d4ek.c | 15 ++-
configs/sama5d4ek_mmc_defconfig | 6 ++
configs/sama5d4ek_nandflash_defconfig | 6 ++
confi
Move CONFIG_SYS_NO_FLASH to the configs/sama5d4*_defconfig file.
Signed-off-by: Wenyou Yang
---
configs/sama5d4_xplained_mmc_defconfig | 1 +
configs/sama5d4_xplained_nandflash_defconfig | 1 +
configs/sama5d4_xplained_spiflash_defconfig | 1 +
configs/sama5d4ek_mmc_defconfig
The patch-set does the following:
1. Add NOR secure boot target on ls1046aqds platform.
2. Add QSPI secure boot target on ls1046ardb platform.
Changes in v2:
Split patches logically from 2 to 3.
Sumit Garg (3):
SECURE_BOOT: Enable chain of trust on LS1046A platform
LS1046AQDS: Add NOR Secure
Add NOR secure boot target. Also enable sec init.
Signed-off-by: Vinitha Pillai
Signed-off-by: Sumit Garg
---
Changes in v2:
Split patches logically from 2 to 3.
board/freescale/ls1046aqds/MAINTAINERS | 4
board/freescale/ls1046aqds/ls1046aqds.c | 18 ++
configs/ls104
Add QSPI Secure Boot target. Also enable sec init.
Signed-off-by: Vinitha Pillai
Signed-off-by: Sumit Garg
---
Changes in v2:
Split patches logically from 2 to 3.
board/freescale/ls1046ardb/MAINTAINERS| 4
board/freescale/ls1046ardb/ls1046ardb.c | 19 +++
c
Define bootscript and its header addresses for QSPI target. Also
define PPA header address to enable PPA validation.
Signed-off-by: Vinitha Pillai
Signed-off-by: Sumit Garg
---
Changes in v2:
Split patches logically from 2 to 3.
arch/arm/include/asm/arch-fsl-layerscape/config.h | 2 +-
arch/
From: Soren Brinkmann
The new FW interface returns the IDCODE and version register, leaving
extracting bitfields to the caller.
Cc: Michal Simek
Cc: Siva Durga Prasad Paladugu
Signed-off-by: Soren Brinkmann
Signed-off-by: Michal Simek
---
board/xilinx/zynqmp/zynqmp.c | 11 +++
incl
Signed-off-by: Michal Simek
---
board/xilinx/zynqmp/zynqmp.c | 4
1 file changed, 4 insertions(+)
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index b0acaa5b7721..7e6728870931 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -422,6
Do not setup use_alt bit which copy alternative boot mode to
boot mode. The reason is that this bit is cleared after POR
but not after any software reset which will cause
that after SW reset bootrom will look for different boot image.
This patch setups alternative boot mode selection (purely SW
ha
Autogenerated files contain casting issues and missing function
declaration and even usleep implementation. Suppress them for now
till these files are fixed.
Signed-off-by: Michal Simek
---
board/xilinx/zynqmp/Makefile | 3 +++
board/xilinx/zynqmp/xil_io.h | 9 +
2 files changed, 12 ins
From: Siva Durga Prasad Paladugu
Add support for SD1 with level shifters bootmode.
Signed-off-by: Siva Durga Prasad Paladugu
Signed-off-by: Michal Simek
---
arch/arm/include/asm/arch-zynqmp/hardware.h | 1 +
board/xilinx/zynqmp/zynqmp.c| 3 +++
2 files changed, 4 insertions(+
Zynq 7000S (Single A9 core) devices is using different ID code.
This patch adds this new codes and assign them.
Signed-off-by: Michal Simek
---
board/xilinx/zynq/board.c | 12
include/zynqpl.h | 18 ++
2 files changed, 30 insertions(+)
diff --git a/board/x
This patch adds support to check the buswidth on nand flash
at runtime based on nand MIO configurations done by FSBL.
User needs to correctly configure the MIO's based on the
buswidth supported by the nand flash which is present on the board.
Added nand8 and nand16 @periph names on slcr driver.
From: Siva Durga Prasad Paladugu
Modify the nwcfg bit definitions to have 32-bit
by removing the extra nibble.
Signed-off-by: Siva Durga Prasad Paladugu
Signed-off-by: Michal Simek
---
drivers/net/zynq_gem.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a
From: Siva Durga Prasad Paladugu
Correct the SGMII enable bit position to 27 instead
of 31.
Signed-off-by: Siva Durga Prasad Paladugu
Signed-off-by: Michal Simek
---
drivers/net/zynq_gem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/zynq_gem.c b/drivers/ne
From: Siva Durga Prasad Paladugu
Clear ecc ON bit while sending read command as all types
of read command(like reading spare) doesnt need ECC to be
enabled. It has been anyway taken care in other places
whereever required using arasan_nand_enable_ecc().
Signed-off-by: Siva Durga Prasad Paladugu
Hi: york
Best Regards
Wenbin Song
> -Original Message-
> From: york sun
> Sent: Wednesday, October 26, 2016 4:35 AM
> To: Wenbin Song ; albert.u.b...@aribaud.net;
> Mingkai Hu ; u-boot@lists.denx.de
> Subject: Re: [PATCH v4 1/2] armv8/ls1043a: fixup GIC offset according to SVR
> and SCFG
Select the newly introduced ARM_GIC option to the relevant MACH
configurations.
Signed-off-by: Antoine Tenart
---
arch/arm/Kconfig | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6a5e53280679..b329d3c29fce 100644
--- a/arch/arm/Kconfig
+++ b/
Implement three atomic functions to allow making an atomic operation
that returns the value. Adds: atomic_add_return(), atomic_sub_return(),
atomic_inc_return() and atomic_dec_return().
Signed-off-by: Antoine Tenart
---
arch/arm/include/asm/atomic.h | 34 ++
1 fil
Introducing the ARM_GIC configuration option, use it to only use GIC
specific code in ARM PSCI function when the SoC has a GIC.
Signed-off-by: Antoine Tenart
---
arch/arm/cpu/armv7/nonsec_virt.S | 6 ++
arch/arm/cpu/armv7/virt-v7.c | 42 ++--
2 files
sun5i now implements the psci suspend function. In order to be used by
the kernel, we should now boot in non-secure mode. Enable it by default.
Signed-off-by: Antoine Tenart
---
board/sunxi/Kconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
i
Some SoC does not have a GIC. Adds a configuration option to denote
this, allowing to remove code configuring the GIC when it's not
possible.
Signed-off-by: Antoine Tenart
---
arch/arm/Kconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index d7a9b1
Hi all,
This series adds an implementation of the psci suspend function for both
sun5i and sun7i. This was tested on Nextthing's CHIP and on a A20, using
cpuidle in Linux. My tests showed a power consumption reduced by nearly
a factor 2 on the CHIP when the system was idle. It went from ~1W withou
Select the newly introduced ARM_GIC option to the relevant sunxi
MACH configurations.
Signed-off-by: Antoine Tenart
---
board/sunxi/Kconfig | 7 +++
1 file changed, 7 insertions(+)
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index c0ffebfc..cd8330c3944f 100644
--- a/board/sun
Select the newly introduced ARM_GIC option to the relevant configuration
which also have a psci implementation.
Signed-off-by: Antoine Tenart
---
arch/arm/mach-tegra/tegra124/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-tegra/tegra124/Kconfig
b/arch/arm/mach-tegra
Add the suspend psci function for sun5i and sun7i. Thus function
switches the cpu clk source to osc24M or to losc depending on the
SoC family.
Signed-off-by: Antoine Tenart
---
arch/arm/cpu/armv7/sunxi/Makefile | 9 ++-
arch/arm/cpu/armv7/sunxi/psci.c | 2 +-
arch/a
Select the newly introduced ARM_GIC option to the relevant configuration
which also have a psci implementation.
Signed-off-by: Antoine Tenart
---
arch/arm/mach-exynos/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index ce2
The sun5i SoCs can take advantage of the newly introduce PSCI suspend
function. Add defines used by the PSCI code.
Signed-off-by: Antoine Tenart
---
include/configs/sun5i.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/configs/sun5i.h b/include/configs/sun5i.h
index d2576599036a
On Wed, Oct 26, 2016 at 3:39 PM, Jagan Teki wrote:
> On Wed, Sep 28, 2016 at 4:39 PM, Yuan Yao wrote:
> > From: Yuan Yao
> >
> > Some new flash don't support bar register but use 4bytes address to
> > support exceed 16MB flash size.
> > So add flash flag:
> > ADDR_4B
> > for some flash which supp
On 25/10/2016 02:09, Peng Fan wrote:
> Hi Stefano,
> On Mon, Oct 24, 2016 at 04:05:53PM +0200, Stefano Babic wrote:
>> Hi Peng,
>>
>> On 11/10/2016 08:29, Peng Fan wrote:
>>> Add plugin support for imximage.
>>>
>>> Define CONFIG_USE_IMXIMG_PLUGIN in defconfig to enable using plugin.
>>>
>>> Signed
On 10/26/2016 06:10 AM, Antoine Tenart wrote:
Select the newly introduced ARM_GIC option to the relevant configuration
which also have a psci implementation.
This doesn't look right; all Tegras have a GIC, so it's not a
board-specific option. Perhaps TEGRA_COMMON or TEGRA_ARMV[78]_COMMON
shou
Hello,
On Wed, Oct 26, 2016 at 08:55:27AM -0600, Stephen Warren wrote:
> On 10/26/2016 06:10 AM, Antoine Tenart wrote:
> > Select the newly introduced ARM_GIC option to the relevant configuration
> > which also have a psci implementation.
>
> This doesn't look right; all Tegras have a GIC, so it'
On 10/26/2016 08:59 AM, Antoine Tenart wrote:
Hello,
On Wed, Oct 26, 2016 at 08:55:27AM -0600, Stephen Warren wrote:
On 10/26/2016 06:10 AM, Antoine Tenart wrote:
Select the newly introduced ARM_GIC option to the relevant configuration
which also have a psci implementation.
This doesn't look
Hi Jagan,
On 25/10/2016 08:23, Jagan Teki wrote:
> From: Jagan Teki
>
> Add NAND support for Engicam i.CoreM6 qdl board.
>
> Boot Log:
>
>
> U-Boot SPL 2016.09-rc2-30755-gd3dc581-dirty (Sep 28 2016 - 23:00:43)
> Trying to boot from NAND
> NAND : 512 MiB
>
> U-Boot 2016.09-rc2-30755-
Hi,
On Wed, Oct 26, 2016 at 02:10:24PM +0200, Antoine Tenart wrote:
> Implement three atomic functions to allow making an atomic operation
> that returns the value. Adds: atomic_add_return(), atomic_sub_return(),
> atomic_inc_return() and atomic_dec_return().
>
> Signed-off-by: Antoine Tenart
I
Add support for device tree fixup for the DPAA1 QBMan nodes in ARM platforms
Signed-off-by: Roy Pledge
---
arch/arm/cpu/armv8/fsl-layerscape/fdt.c| 89
.../arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c |3 +
.../include/asm/arch-fsl-layerscape/immap_lsch2.
On a Raspberry Pi 2 disagreements on cell endianness can be observed:
U-Boot> fdt print /soc/gpio@7e20 phandle
phandle = <0x000d>
U-Boot> fdt get value myvar /soc/gpio@7e20 phandle; printenv myvar
myvar=0x0D00
Fix this by always treating the pointer as __be32 and convertin
Let get_maintainers.pl pick up the new cmd/fdt.c.
Cc: Simon Glass
Signed-off-by: Andreas Färber
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 8e67202..3d18f28 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -273,7 +273,7 @@ F:
Hi,
Am 26.10.2016 um 22:17 schrieb Sumit Garg:
> The patch-set does the following:
>
> 1. Add NOR secure boot target on ls1046aqds platform.
> 2. Add QSPI secure boot target on ls1046ardb platform.
Please double-check your clock, you are posting in the future.
Regards,
Andreas
--
SUSE Linux G
Hi Felix,
On 19 October 2016 at 04:12, Felix Brack wrote:
> This patch adds support for the PDU001 board.
>
> Signed-off-by: Felix Brack
> ---
>
> arch/arm/Kconfig | 1 +
> arch/arm/cpu/armv7/am33xx/Kconfig | 9 ++
> board/eets/pdu001/Kconfig | 66 ++
> boa
On 20 October 2016 at 20:07, Wenyou Yang wrote:
> The CONFIG_AT91_GPIO option is used to select AT91 PIO GPIO driver.
>
> Signed-off-by: Wenyou Yang
> ---
>
> drivers/gpio/Kconfig | 13 +
> 1 file changed, 13 insertions(+)
Reviewed-by: Simon Glass
__
Hi,
On 19 October 2016 at 00:47, Paolo De Luca Bosso
wrote:
> Hi!
>
> Yes, i have a question about U-Boot.
>
> Can i use U-Boot as bootloader for a proprietary operating system?
Yes.
>
> I want use bootm command and a bin file. In particular the Image kernel is
> produced by mkimage command wit
Hi Wenyou,
On 20 October 2016 at 20:07, Wenyou Yang wrote:
> Add the device tree support.
>
> Signed-off-by: Wenyou Yang
> ---
>
> drivers/gpio/at91_gpio.c | 15 +++
> 1 file changed, 15 insertions(+)
Reviewed-by: Simon Glass
>
> diff --git a/drivers/gpio/at91_gpio.c b/drivers/gp
On 20 October 2016 at 20:07, Wenyou Yang wrote:
> Add the clock support.
>
> Signed-off-by: Wenyou Yang
> ---
>
> drivers/gpio/at91_gpio.c | 13 +
> 1 file changed, 13 insertions(+)
Reviewed-by: Simon Glass
___
U-Boot mailing list
U-Boot@
Hi,
On 21 October 2016 at 01:10, Marek Vasut wrote:
> On 10/21/2016 08:52 AM, Marcel Ziswiler wrote:
>> Hi Simon
>>
>> On Thu, 2016-10-20 at 13:06 -0600, Simon Glass wrote:
>>> Only three serial drivers remain to be converted. This series drops
>>> two of those, since the boards appear to be unma
Hi Tom,
On 23 October 2016 at 18:40, Tom Rini wrote:
> On Mon, Oct 17, 2016 at 08:12:33PM -0600, Simon Glass wrote:
>
>> This series moves a number of console-related CONFIG options to Kconfig.
>> Those that are not currently used are removed.
>>
>> A few unused video drivers are also removed and
On 23 October 2016 at 20:45, Vagrant Cascadian wrote:
> Signed-off-by: Vagrant Cascadian
> ---
>
> fs/ubifs/ubifs.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Simon Glass
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On 23 October 2016 at 20:45, Vagrant Cascadian wrote:
> Signed-off-by: Vagrant Cascadian
> ---
>
> cmd/bootm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Simon Glass
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On 23 October 2016 at 23:08, Jaehoon Chung wrote:
> mshc_0 node should be overwriten the defined node in exynos4.dtsi.
I think you mean 'The mshc_0 node overwrites the defined node...'
> It's meaningless. So removed this node. Instead, use the node in exynos4.dtsi.
'So remove this node'
>
> Si
On 23 October 2016 at 23:08, Jaehoon Chung wrote:
> Changed the compatible from generic thing to meaning compatible.
> "samsung,exynos-mmc" should be removed.
>
> Signed-off-by: Jaehoon Chung
> ---
> arch/arm/dts/exynos4.dtsi | 25 +++--
> 1 file changed, 15 insertions(+), 10
On 23 October 2016 at 23:08, Jaehoon Chung wrote:
> Didn't overwrite the node. Just reuse the parent node.
> And add the Exynos Series specific properties.
>
> Signed-off-by: Jaehoon Chung
> ---
> arch/arm/dts/exynos4210-origen.dts | 24 -
> arch/arm/dts/exynos4210-trats.dts
On 23 October 2016 at 20:45, Vagrant Cascadian wrote:
> Cover-Letter: Fixes several spelling errors for the words "resetting",
> "extended", "occur", and "multiple".
>
> Signed-off-by: Vagrant Cascadian
> ---
>
> arch/arm/mach-exynos/dmc_init_ddr3.c| 2 +-
> arch/arm/mach-socfpga/misc.c
On 26 October 2016 at 01:12, Keerthy wrote:
> In case we want to force a particular value on a regulator
> irrespective of the min/max constraints for testing purposes
> one can call regulator_set_value_force function.
>
> Signed-off-by: Keerthy
> ---
> cmd/regulator.c
On 23 October 2016 at 23:08, Jaehoon Chung wrote:
> To use the CONFIG_BLK/CONFIG_DM_MMC/CONFIG_DM_MMC_OPS, add the
> configurations for exynos4 series.(by default)
>
> Signed-off-by: Jaehoon Chung
> ---
> configs/odroid_defconfig | 3 +++
> configs/origen_defconfig | 3 +++
> configs/smdkv31
On 26 October 2016 at 01:12, Keerthy wrote:
> Currently the specific set ops functions are directly
> called without any check for voltage limits for a regulator.
> Check for them and proceed.
>
> Signed-off-by: Keerthy
> ---
> drivers/power/regulator/regulator-uclass.c | 5 +
> 1 file chang
On 23 October 2016 at 20:45, Vagrant Cascadian wrote:
> Signed-off-by: Vagrant Cascadian
> ---
>
> board/sysam/amcore/amcore.c | 2 +-
> tools/mkimage.c | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Simon Glass
_
Hi Keerthy,
On 26 October 2016 at 01:12, Keerthy wrote:
> Currently the specific set ops functions are directly
> called without any check for min/max current limits for a regulator.
> Check for them and proceed.
>
> Signed-off-by: Keerthy
> ---
> drivers/power/regulator/regulator-uclass.c | 5
Hi Tom,
On 24 October 2016 at 13:13, Tom Rini wrote:
> Add 'PCI' as a menu option and migrate all existing users.
>
> Signed-off-by: Tom Rini
> ---
> Tegra is in a funny spot here. TEGRA_COMMON will select DM_PCI and
> DM_PCICOMPAT. But adding PCI to the list here results in the following:
>
On 10/21/2016 04:37 PM, york sun wrote:
> On 10/18/2016 07:48 PM, Hamish Martin wrote:
>> This erratum is already implemented for other ARM based QorIQ
>> platforms with the Gen4 DDR controller. Port the fix to the Gen3
>> controller and enable it for T2080 and T2081.
>>
>> Reviewed-by: Chris Packh
On 10/26/2016 03:39 AM, Wenbin Song wrote:
>>> +
>>> +ENTRY(smp_kick_all_cpus)
>>> + /* Kick secondary cpus up by SGI 0 interrupt */
>>> + mov x29, lr /* Save LR */
>>> + bl fix_gic_offset
>>> + bl gic_kick_secondary_cpus
>>> + mov lr, x29
On Wed, Oct 26, 2016 at 8:38 PM, Stefano Babic wrote:
> Hi Jagan,
>
>
> On 25/10/2016 08:23, Jagan Teki wrote:
>> From: Jagan Teki
>>
>> Add NAND support for Engicam i.CoreM6 qdl board.
>>
>> Boot Log:
>>
>>
>> U-Boot SPL 2016.09-rc2-30755-gd3dc581-dirty (Sep 28 2016 - 23:00:43)
>> Tryin
On 10/24/2016 09:30 PM, Calvin Johnson wrote:
I wonder why we don't see ECC errors before this patch. We have
LS1043A boots on NAND, SD.
>>>
>>> OCRAM has a requirement of initializing before first time "read".
>>> If user reads OCRAM before **initializing**; ECC error will come. (
On 10/07/2016 11:56 PM, Alison Wang wrote:
> To support loading a 32-bit OS, the execution state will change from
> AArch64 to AArch32 when jumping to kernel.
>
> The architecture information will be got through checking FIT image,
> then U-Boot will load 32-bit OS or 64-bit OS automatically.
>
> S
On 10/24/2016 02:16 PM, york@nxp.com wrote:
>> +
>> +#ifdef CONFIG_SYS_FSL_ERRATUM_A007907
>> +flush_dcache();
>> +mtspr(L1CSR2, (mfspr(L1CSR2) & ~L1CSR2_DCSTASHID));
>> +sync();
>> +#endif
>> +
>
> My erratum document shows a second step is to insert sync instruction
> before each
From: Stephen Warren
Travis CI seems to be confused when there's a colon in an echo command,
and this is currently worked around using a variable that contains the
text we want to echo. Use = syntax instead so that we can remove the
work-around; it's rather confusing until you find out what it's
From: Stephen Warren
Any time an x86 toolchain is used, we need to edit ~/.buildman to
reference it. Move the editing logic into a central place so that it
doesn't have to be duplicated everywhere that uses the x86 toolchain;
future patches will add additional cases where it's used.
It would be
From: Stephen Warren
This places build results into a board-specific directory rather than a
buildman-thread-specific directory. This is required so that we can
access the directory from test.py, and there's no risk of a particular
build's results being over-written by another build performed by
From: Stephen Warren
Invoking exit prevents any subsequent build commands from running, and
future patches will add extra commands.
Signed-off-by: Stephen Warren
---
.travis.yml | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/.travis.yml b/.travis.yml
index 6e72e0bb233f.
From: Stephen Warren
The phrase "if [ $? -ne 0 ]; then exit $?; fi" doesn't work correctly;
by the time the "exit" statement runs, $? has already been over-written
by the result of the [ command. Fix this by explicitly storing $? and
then using that stored value in both the test and the error-cas
From: Stephen Warren
Use buildman to compile any U-Boot binary tested by test/py. This
re-uses all the work done elsewhere to make buildman work within
Travis-CI, in particular related to toolchain downloading and buildman
config file creation.
Signed-off-by: Stephen Warren
---
.travis.yml | 8
On 10/24/2016 02:13 PM, Tom Rini wrote:
Add 'PCI' as a menu option and migrate all existing users.
Signed-off-by: Tom Rini
---
Tegra is in a funny spot here. TEGRA_COMMON will select DM_PCI and
DM_PCICOMPAT. But adding PCI to the list here results in the following:
aarch64: (for 61/61 boar
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