Hi Marek & Lukasz,
I have an issue running fastboot on my board (which is USB_SPEED_HIGH):
=> fastboot0
failed to enable in ep
failed to enable in ep
failed to enable in ep
Because of this, fastboot does not even initialize properly, and I need
to "^C" to break out…
I have tr
On Saturday, January 16, 2016 at 07:13:51 PM, Wills Wang wrote:
> Reviewed-by: Thomas Chou
>
> Signed-off-by: Wills Wang
> ---
>
> Changes in v7:
> - Define spi_cs_activate/spi_cs_deactivate
> - Rename MHZ to ATH79_SPI_MHZ
> - Use clrsetbits_32
The driver gets stuck if I do:
=> sf probe
=> sf
On Wednesday, January 27, 2016 at 01:35:55 AM, Steve Rae wrote:
> Hi Marek & Lukasz,
>
>
> I have an issue running fastboot on my board (which is USB_SPEED_HIGH):
>
> => fastboot0
>
> failed to enable in ep
>
> failed to enable in ep
>
> failed to enable in ep
>
> Because of
On Tue, Jan 26, 2016 at 04:20:38PM +0100, Clemens Gruber wrote:
>This is a follow-up patch to e92029c0f4 and adds a prototype for
>the weak mmc_get_env_dev function.
>
>Cc: Tom Rini
>Cc: Stephen Warren
>
>Signed-off-by: Clemens Gruber
>---
> include/mmc.h | 1 +
> 1 file changed, 1 insertion(+)
>
Hi Tom,
On Tue, Jan 26, 2016 at 10:47 PM, Tom Rini wrote:
> On Tue, Jan 26, 2016 at 12:26:07PM +0800, Bin Meng wrote:
>> Hi Tom,
>>
>> On Mon, Jan 25, 2016 at 10:12 PM, Tom Rini wrote:
>> > On Mon, Jan 25, 2016 at 11:18:26AM +0800, Bin Meng wrote:
>> >> Hi Tom,
>> >>
>> >> On Mon, Jan 25, 2016 a
On 16-01-26 05:35 PM, Marek Vasut wrote:
On Wednesday, January 27, 2016 at 01:35:55 AM, Steve Rae wrote:
Hi Marek & Lukasz,
I have an issue running fastboot on my board (which is USB_SPEED_HIGH):
=> fastboot0
failed to enable in ep
failed to enable in ep
failed to ena
On Tue, Jan 26, 2016 at 08:51:38PM +0100, Hans de Goede wrote:
> Hi Tom,
>
> Here is the first sunxi pull-req for v2016.04, it
> contains various fixes / improvements all over the place.
>
> The following changes since commit ac01603da4598b4b34ff3a5c428aa925daa12b60:
>
> checkpatch: ignore re
To avoid the duplicated code, add the PLLB handle functions.
Signed-off-by: Wenyou Yang
Reviewed-by: Andreas Bießmann
---
Changes in v2: None
arch/arm/mach-at91/arm926ejs/clock.c | 38 +
arch/arm/mach-at91/include/mach/clk.h |2 ++
2 files changed, 40 in
To reduce the duplicated code, add PLLB enable/disable functions,
replace the UTMI PLL handle code with these functions.
It is based on the following patch set.
[PATCH 0/5] ARM: at91: improve peripheral and system clock handle
functions
[PATCH 0/4] ARM: at91: add UTMI PLL handle f
Due to introducing the new PLLB clock handle functions,
use these functions to clean up the PLLB enable code.
Signed-off-by: Wenyou Yang
Reviewed-by: Andreas Bießmann
---
Changes in v2:
- collect Reviewed-by from Andreas.
board/siemens/smartweb/smartweb.c |6 +-
board/siemens/taurus/
On Wed, Jan 27, 2016 at 09:55:02AM +0800, Bin Meng wrote:
> Hi Tom,
>
> On Tue, Jan 26, 2016 at 10:47 PM, Tom Rini wrote:
> > On Tue, Jan 26, 2016 at 12:26:07PM +0800, Bin Meng wrote:
> >> Hi Tom,
> >>
> >> On Mon, Jan 25, 2016 at 10:12 PM, Tom Rini wrote:
> >> > On Mon, Jan 25, 2016 at 11:18:26
Due to introducing the new PLLB clock handle functions,
use these functions to clean up the PLLB enable/disable code.
Signed-off-by: Wenyou Yang
---
Changes in v2:
- add return value for timeout checking at91_pllb_clk_enable/disable().
drivers/usb/host/ohci-at91.c | 22 +++--
On Wednesday, January 27, 2016 at 02:58:38 AM, Steve Rae wrote:
> On 16-01-26 05:35 PM, Marek Vasut wrote:
> > On Wednesday, January 27, 2016 at 01:35:55 AM, Steve Rae wrote:
> >> Hi Marek & Lukasz,
> >>
> >> I have an issue running fastboot on my board (which is USB_SPEED_HIGH):
> >> => fast
Add explicit cpu_to_be32()/be32_to_cpu() conversion to BE EHCI I/O
accessors to align them with their LE counterpart. No functional
change.
Signed-off-by: Marek Vasut
Cc: Daniel Schwierzeck
Cc: Hans de Goede
---
drivers/usb/host/ehci.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
This patch makes sure that the flush/invalidate_dcache_range() functions
can handle corner-case calls like this -- invalidate_dcache_range(0, 0, 0);
This call is valid and is happily produced by USB EHCI code for example.
The expected behavior of the cache function(s) in this case is that they
will
If the USB EHCI is configured for little endian MMIO, make sure to
clear the USBMODE_BE flag from the USBMODE register.
Signed-off-by: Marek Vasut
Cc: Daniel Schwierzeck
Cc: Hans de Goede
---
drivers/usb/host/ehci-hcd.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/usb/host/ehc
Some architectures, like MIPS, require remapping of the registers.
Add the map_physmem() call to handle it.
Signed-off-by: Marek Vasut
Cc: Daniel Schwierzeck
Cc: Hans de Goede
Cc: Masahiro Yamada
Cc: Alexey Brodkin
---
drivers/usb/host/ehci-generic.c | 4 +++-
1 file changed, 3 insertions(+)
Certain processor architectures, like MIPS, require that the USB
structures and transfer buffers are passed with their PA to the
USB controller. If VA is passed, the USB will not work. Add the
necessary virt_to_phys() calls into the USB EHCI code to make it
work.
Signed-off-by: Marek Vasut
Cc: Da
On Tue, Jan 26, 2016 at 05:40:49PM +0100, Albert ARIBAUD wrote:
> Some armv7 targets are missing a cache line size declaration.
> In preparation for "arm: cache: Implement cache range check for v7"
> patch, add these declarations with the appropriate value for
> the target's SoC or CPU.
>
> Signe
Fix error handling for mxs_nand_init.
The original error handling is wrong for err2 and err1.
Should first free desc[x], then free desc.
This patch also correctly handle err3, should use
MXS_DMA_CHANNEL_AHB_APBH_GPMI0 as the check point.
Cc: Stefano Babic
CC: Fabio Estevam
Cc: Scott Wood
Cc:
This patch removes the uart clock enable from serial driver & move it in the
board code.
Signed-off-by: Vikas Manocha
---
arch/arm/include/asm/arch-stm32f4/stm32_defs.h | 15
arch/arm/include/asm/arch-stm32f4/stm32_periph.h | 27 +++
arch/arm/mach-stm32/stm32f4/clock.c
On Tue, Jan 26, 2016 at 10:12:10AM -0500, Tom Rini wrote:
>On Tue, Jan 26, 2016 at 10:58:47AM +0800, Peng Fan wrote:
>> On Mon, Jan 25, 2016 at 09:45:47PM -0500, Tom Rini wrote:
>> >On Tue, Jan 26, 2016 at 09:55:43AM +0800, Peng Fan wrote:
>> >> Hi Simon,
>> >>
>> >> On Mon, Jan 25, 2016 at 06:11:
On Wednesday, January 27, 2016 at 03:38:02 AM, Peng Fan wrote:
> Fix error handling for mxs_nand_init.
>
> The original error handling is wrong for err2 and err1.
> Should first free desc[x], then free desc.
>
> This patch also correctly handle err3, should use
> MXS_DMA_CHANNEL_AHB_APBH_GPMI0 as
On 01/25/2016 01:36 PM, Lubomir Rintel wrote:
> It seems like the P5 header was not present on "Model B" any board prior
> to Revision 2.0, there's no need for a separate device tree.
>
> Also, it looks like "rev2" is incorrectly used to only cover the 512MiB
> memory models; there also were 256Mi
Pull the code which displays U-Boot prompt and reads the command line
into a separate function. No functional change.
Signed-off-by: Marek Vasut
---
common/cli_hush.c | 21 -
1 file changed, 16 insertions(+), 5 deletions(-)
diff --git a/common/cli_hush.c b/common/cli_hush.c
Add trivial support for changing the U-Boot command prompt string
by setting PS1 and PS2 environment variables. Only static variables
are supported.
Signed-off-by: Marek Vasut
---
README| 8
common/cli_hush.c | 10 ++
2 files changed, 18 insertions(+)
diff --git a/
On 01/16/2016 08:09 PM, Stefan Brüns wrote:
> The first patch fixes an out-of-bounds access, and makes the calculation of
> maximum transfer size more straightforward. It also makes overriding the
> maximum transfer size easier for split transactions
Sorry I haven't been keeping up on the U-Boot d
On Wednesday, January 27, 2016 at 04:52:03 AM, Stephen Warren wrote:
> On 01/16/2016 08:09 PM, Stefan Brüns wrote:
> > The first patch fixes an out-of-bounds access, and makes the calculation
> > of maximum transfer size more straightforward. It also makes overriding
> > the maximum transfer size e
On Wednesday, January 27, 2016 at 05:14:00 AM, Ramneek Mehresh wrote:
> > -Original Message-
> > From: Marek Vasut [mailto:ma...@denx.de]
> > Sent: Tuesday, January 26, 2016 4:58 PM
> > To: Ramneek Mehresh
> > Cc: u-boot@lists.denx.de
> > Subject: Re: [PATCH 2/2] include:configs: Add usb d
Add device tree node's for lpuart on Vybrid platform
Signed-off-by: Bhuvanchandra DV
Acked-by: Stefan Agner
Reviewed-by: Bin Meng
---
arch/arm/dts/vf.dtsi | 43 +++
1 file changed, 43 insertions(+)
diff --git a/arch/arm/dts/vf.dtsi b/arch/arm/dts/vf.dts
Changes since v3:
- Add missing space in device tree.
- Reorder the patchset to avoid broken state.
Changes since v2:
- Split the patch for updating the license string.
- Reorder the patchset to avoid broken state.
Changes since v1:
- Update the license string in device tree's.
- Update all lpuar
Since SPDX license is already there, drop the full one.
Signed-off-by: Bhuvanchandra DV
Acked-by: Stefan Agner
Reviewed-by: Bin Meng
---
arch/arm/dts/vf-colibri.dtsi | 5 -
arch/arm/dts/vf.dtsi | 5 -
arch/arm/dts/vf500-colibri.dts | 5 -
arch/arm/dts/vf610-colibri.dts
- Enable lpuart support on Toradex Colibri VF50/VF61
- Use UART0 for stdout.
Signed-off-by: Bhuvanchandra DV
Reviewed-by: Bin Meng
---
arch/arm/dts/vf-colibri.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/dts/vf-colibri.dtsi b/arch/arm/dts/vf-colibri.dtsi
index f
- Add device tree files for Phytec phyCORE-Vybrid Board.
- Enable lpuart support for Phytec phyCORE-Vybrid Board.
- Use UART1 for stdout.
Signed-off-by: Bhuvanchandra DV
Reviewed-by: Bin Meng
---
arch/arm/dts/Makefile | 3 ++-
arch/arm/dts/pcm052.dts | 22 ++
2 files chan
Remove the legacy way of enabling GPIO, SPI and UART on Vybrid
based boards since these driver's now only supports DT mode.
Signed-off-by: Bhuvanchandra DV
Acked-by: Stefan Agner
Reviewed-by: Bin Meng
---
include/configs/colibri_vf.h | 13 -
include/configs/pcm052.h | 3 ---
i
Let's go with pure DT solution for board's
based on NXP/Freescale Vybrid platform.
- Merge the DT defconfig with non-DT defconfig for Toradex
Colibri VF50/VF61 and drop the non-DT defconfig.
- Update the legacy defconfigs for NXP/Freescale VF610 Tower
Board with DT.
- Update the legacy defconf
- Add device tree files for NXP/Freescale VF610 Tower Board.
- Enable lpuart support on NXP/Freescale VF610 Tower Board.
- Use UART1 as stdout.
Signed-off-by: Bhuvanchandra DV
Reviewed-by: Bin Meng
---
arch/arm/dts/Makefile | 3 ++-
arch/arm/dts/vf610-twr.dts | 22 ++
All boards using this driver are with device tree support,
hence drop the legacy code in driver to have a pure DT solution.
Signed-off-by: Bhuvanchandra DV
Reviewed-by: Bin Meng
---
drivers/gpio/vybrid_gpio.c | 18 --
1 file changed, 18 deletions(-)
diff --git a/drivers/gpio/vy
All boards using this driver are with device tree support,
hence drop the legacy code in driver to have a pure DT solution.
Signed-off-by: Bhuvanchandra DV
Reviewed-by: Bin Meng
---
drivers/serial/serial_lpuart.c | 101 +
1 file changed, 2 insertions(+),
Hi Tom,
On Wed, Jan 27, 2016 at 10:08 AM, Tom Rini wrote:
> On Wed, Jan 27, 2016 at 09:55:02AM +0800, Bin Meng wrote:
>> Hi Tom,
>>
>> On Tue, Jan 26, 2016 at 10:47 PM, Tom Rini wrote:
>> > On Tue, Jan 26, 2016 at 12:26:07PM +0800, Bin Meng wrote:
>> >> Hi Tom,
>> >>
>> >> On Mon, Jan 25, 2016 a
On Tuesday, January 26, 2016 at 05:40:49 PM, Albert ARIBAUD wrote:
> Some armv7 targets are missing a cache line size declaration.
> In preparation for "arm: cache: Implement cache range check for v7"
> patch, add these declarations with the appropriate value for
> the target's SoC or CPU.
>
> Sig
On Fri, 2015-11-27 at 15:22 +0800, Chin Liang See wrote:
> Enable SDMMC calibration to determine the best setting for
> drvsel and smplsel. Calibration will be triggered if the
> drvsel and smplsel node are not available in DTS.
We have a Cyclone V based board and on the latest revision the SD car
> -Original Message-
> From: Marek Vasut [mailto:ma...@denx.de]
> Sent: Wednesday, January 27, 2016 9:57 AM
> To: Ramneek Mehresh
> Cc: Ramneek Mehresh ; u-
> b...@lists.denx.de; Simon Glass
> Subject: Re: [PATCH 2/2] include:configs: Add usb device-tree fixup for all
> fsl
> platforms
> -Original Message-
> From: Marek Vasut [mailto:ma...@denx.de]
> Sent: Tuesday, January 26, 2016 4:58 PM
> To: Ramneek Mehresh
> Cc: u-boot@lists.denx.de
> Subject: Re: [PATCH 2/2] include:configs: Add usb device-tree fixup for all
> fsl
> platforms
>
> On Tuesday, January 26, 2016 at
Hello Hans,
Am 26.01.2016 um 18:05 schrieb Hans de Goede:
Hi Heiko,
Your fix for the checkpatch issues in one of my patches (sorry about those)
has broken mvtwsi support.
Uh! Sorry!
This patch fixes this, I'm currently preparing a sunxi pull-req, and I
plan to include this fix, so this is m
On Wed, Jan 27, 2016 at 2:10 AM, Stephen Warren wrote:
> From: Stephen Warren
>
> With CONFIG_DM_PCI enabled, PCI buses are not enumerated at boot, as they
> are without that config option enabled. No command exists to enumerate the
> PCI buses. Hence, unless some board-specific code causes PCI e
Hello Hans,
Am 26.01.2016 um 18:05 schrieb Hans de Goede:
"Fix mvtwsi not working on sun6i and newer sunxi SoCs" includes the following:
@@ -189,7 +200,8 @@ static int twsi_start(struct i2c_adapter *adap, int
expected_status)
/* globally set TWSIEN in case it was not */
twsi_co
Hello Wenyou,
Am 27.01.2016 um 03:04 schrieb Wenyou Yang:
To avoid the duplicated code, add the PLLB handle functions.
Signed-off-by: Wenyou Yang
Reviewed-by: Andreas Bießmann
---
Changes in v2: None
arch/arm/mach-at91/arm926ejs/clock.c | 38 +
arch/arm
Hello Wenyou,
Am 27.01.2016 um 03:04 schrieb Wenyou Yang:
Due to introducing the new PLLB clock handle functions,
use these functions to clean up the PLLB enable/disable code.
Signed-off-by: Wenyou Yang
---
Changes in v2:
- add return value for timeout checking at91_pllb_clk_enable/disable(
Hello Wenyou,
Am 27.01.2016 um 03:04 schrieb Wenyou Yang:
Due to introducing the new PLLB clock handle functions,
use these functions to clean up the PLLB enable code.
Signed-off-by: Wenyou Yang
Reviewed-by: Andreas Bießmann
---
Changes in v2:
- collect Reviewed-by from Andreas.
board/s
Hello Marek,
Am 27.01.2016 um 04:47 schrieb Marek Vasut:
Pull the code which displays U-Boot prompt and reads the command line
into a separate function. No functional change.
Signed-off-by: Marek Vasut
---
common/cli_hush.c | 21 -
1 file changed, 16 insertions(+), 5 del
Hello Heiko,
Thank you for your test.
> -Original Message-
> From: Heiko Schocher [mailto:h...@denx.de]
> Sent: 2016年1月27日 14:31
> To: Yang, Wenyou
> Cc: U-Boot Mailing List
> Subject: Re: [U-Boot] [PATCH v2 1/3] ARM: at91: clock: add PLLB enable/disable
> functions
>
> Hello Wenyou,
>
Hello Marek,
Am 27.01.2016 um 04:47 schrieb Marek Vasut:
Add trivial support for changing the U-Boot command prompt string
by setting PS1 and PS2 environment variables. Only static variables
are supported.
Signed-off-by: Marek Vasut
---
README| 8
common/cli_hush.c | 1
Hi Dennis,
On 15.01.2016 02:20, Dennis Gilmore wrote:
> Switch all of the mvebu boards to support disto generic booting
> This will enable Fedora, Debian and other distros to support
> mvebu systems easier. Tested on SolidRun ClearFog
Sorry for the late review. I have a few issues with this patch
On 20.01.2016 08:13, Stefan Roese wrote:
This patch adds support for the Armada XP (MV78260) based theadorable
board. Its equipped with onboard DDR3, UART, ethernet, I2C, SPI NOR,
LCD and SATA (SSD) interfaces / devices.
Two defconfigs are added:
theadorable_defconfig:
The production U-Boot ver
Hi Tom,
please pull the following patch.
Thanks,
Stefan
The following changes since commit 9e4de7fd4acc8f99b6d383c711d21c0159849629:
Merge branch 'master' of http://git.denx.de/u-boot-sunxi (2016-01-26
17:45:37 -0500)
are available in the git repository at:
git://www.denx.de/git/u-boot
> -Original Message-
> From: Tom Rini [mailto:tr...@konsulko.com]
> Sent: Monday, January 25, 2016 9:06 PM
> To: Aneesh Bansal
> Cc: u-boot@lists.denx.de; Ruchika Gupta
> Subject: Re: [U-Boot] [PATCH v3 0/7] Determine Boot mode at run time
>
> On Fri, Jan 22, 2016 at 04:37:21PM +0530, An
Hi Jagan,
Up to now, I didn't find the 4-Byte addressing mode support.
Do you know if anybody have schedule to add it?
if no, could you please apply this patch, due to as I have said when do the
warm
boot up, the SPI flash will be kept in 4-Byte addressing mode that kernel
driver set,
while t
From: Shaohui Xie
To use AQR405 PHY's interrupt, we need to invert the relative IRQ pins
polarity by setting IRQCR register, because AQR405 interrupt is low active
but GIC accepts high active.
Signed-off-by: Shaohui Xie
---
board/freescale/ls2080ardb/ls2080ardb.c | 4
include/configs/ls20
On Wednesday, January 27, 2016 at 05:30:51 AM, Ramneek Mehresh wrote:
> > -Original Message-
> > From: Marek Vasut [mailto:ma...@denx.de]
> > Sent: Wednesday, January 27, 2016 9:57 AM
> > To: Ramneek Mehresh
> > Cc: Ramneek Mehresh ; u-
> > b...@lists.denx.de; Simon Glass
> > Subject: Re:
Hello Marek,
On Wed, 27 Jan 2016 05:10:59 +0100, Marek Vasut wrote:
> On Tuesday, January 26, 2016 at 05:40:49 PM, Albert ARIBAUD wrote:
> > Some armv7 targets are missing a cache line size declaration.
> > In preparation for "arm: cache: Implement cache range check for v7"
> > patch, add these d
Some armv7 targets are missing a cache line size declaration.
In preparation for "arm: cache: Implement cache range check for v7"
patch, add these declarations with the appropriate value for
the target's SoC or CPU.
Signed-off-by: Albert ARIBAUD
---
Changes in v2:
- fix include/configs/at91-sama
201 - 262 of 262 matches
Mail list logo
