Add support for DWC3 XHCI controller driver
Signed-off-by: Ramneek Mehresh
---
drivers/usb/host/Makefile| 1 +
drivers/usb/host/xhci-dwc3.c | 74
include/linux/usb/dwc3.h | 4 +++
3 files changed, 79 insertions(+)
create mode 100644 drivers
Add xhci driver support for all FSL socs
Signed-off-by: Ramneek Mehresh
---
Changes for v3:
- use FSL_USB_XHCI_ADDR for controller addr
- corrected multiline comment
drivers/usb/host/Makefile| 1 +
drivers/usb/host/xhci-fsl.c | 109
Add base register address information for USB
XHCI controller on LS1021A
Signed-off-by: Ramneek Mehresh
---
arch/arm/include/asm/arch-ls102xa/config.h| 1 +
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 10 ++
2 files changed, 11 insertions(+)
diff --git a/arch/arm/includ
Enable USB IP support for both EHCI and XHCI for
ls1021atwr platform
Signed-off-by: Ramneek Mehresh
---
Changes for v3:
- corrected multiline comment
- moved out xhci controller soc specific
base addresse(s) to soc file
include/configs/ls1021atwr.h | 38 +++
Enable USB IP support for both EHCI and XHCI for
ls1021aqds platform
Signed-off-by: Ramneek Mehresh
---
include/configs/ls1021aqds.h | 22 +-
1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 5de41
Hi Simon,
On Tue, Apr 28, 2015 at 6:48 AM, Simon Glass wrote:
> It is useful to be able to keep track of the available CPUs in a multi-CPU
> system. This uclass is mostly intended for use with SMP systems.
>
> The uclass provides methods for getting basic information about each CPU.
>
> Signed-of
On Tue, Apr 28, 2015 at 6:48 AM, Simon Glass wrote:
> Add a simple command which provides access to a list of available CPUs along
> with descriptions and basic information.
>
> Signed-off-by: Simon Glass
> ---
>
> common/Kconfig | 8
> common/Makefile | 1 +
> common/cmd_cpu.c | 113
On Tue, Apr 28, 2015 at 6:48 AM, Simon Glass wrote:
> Add a subset of this header file from Linux 4.0 to support atomic operations
> in U-Boot.
>
> Signed-off-by: Simon Glass
> ---
>
> arch/x86/include/asm/atomic.h | 115
> ++
> 1 file changed, 115 insert
On Tue, Apr 28, 2015 at 6:48 AM, Simon Glass wrote:
> Add MSR numbers for the fixed MTRRs.
>
> Signed-off-by: Simon Glass
> ---
>
> arch/x86/include/asm/mtrr.h | 14 ++
> 1 file changed, 14 insertions(+)
>
> diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h
> ind
Hi Simon,
On Tue, Apr 28, 2015 at 6:48 AM, Simon Glass wrote:
> Provide access to this x86 instruction from C code.
>
> Signed-off-by: Simon Glass
> ---
>
> arch/x86/include/asm/cpu.h | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm
On Tue, Apr 28, 2015 at 6:48 AM, Simon Glass wrote:
> When we start up additional CPUs we want them to use the same Global
> Descriptor Table. Store the address of this in global_data so we can
> reference it later.
>
> Signed-off-by: Simon Glass
> ---
>
> arch/x86/cpu/cpu.c | 1
On 27 April 2015 at 21:06, Jagannadha Sutradharudu Teki
wrote:
> Upto now flash sector_size is assigned from params which isn't
> necessarily a sector size from vendor, so based on the SECT_*
> flags from flash_params the erase_size will compute and it will
> become the sector_size finally.
>
> Bu
On 24 April 2015 at 17:21, Bin Meng wrote:
> Add a new member 'flags' in struct spi_flash to store the flash flags
> during spi_flash_validate_params().
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v2:
> - New patch to save flash flags to struct spi_flash
>
> drivers/mtd/spi/sf_probe.c | 3
Hello Nathan,
Sorry, I didn't reply last time, becouse I'm quite busy.
On 04/28/2015 07:39 AM, Nathan wrote:
Still not sure where the problem lies. I thought I found an issue, but
it didn't fix anything and caused a different issue.
At first, after plugging in a bunch of printfs, I thought it
On 24 April 2015 at 17:21, Bin Meng wrote:
> With SPI flash moving to driver model, commit fbb0991 "dm: Convert
> spi_flash_probe() and 'sf probe' to use driver model" ignored the
> SST flash-specific write op (byte program & word program), which
> actually broke the SST flash from wroking.
>
> Th
Hi Simon,
On Tue, Apr 28, 2015 at 6:48 AM, Simon Glass wrote:
> Add a function to return the address of the Interrupt Descriptor Table.
>
> Signed-off-by: Simon Glass
> ---
>
> arch/x86/cpu/interrupts.c| 5 +
> arch/x86/include/asm/interrupt.h | 2 ++
> 2 files changed, 7 insertions
Hi Tom,
Please pick this PR.
thanks!
Jagan.
The following changes since commit d77447fdb122dab290fb1ad184a62456011e6e06:
serial: pl01x: fix PL010 regression (2015-04-21 10:05:42 -0400)
are available in the git repository at:
git://git.denx.de/u-boot-spi.git master
for you to fetch change
Hi Francesco,
On Tue, Apr 28, 2015 at 4:23 PM, Francesco Lucconi wrote:
> Yes, I've readed the README.x86 document provided from uboot, I've created
> my u-boot-dtb.bin following the rules of coreboot-x86 recipe.
> I suppose I have to apply several tunings since I'm working with a PC with
> i7-26
Yes, I've readed the README.x86 document provided from uboot, I've created
my u-boot-dtb.bin following the rules of coreboot-x86 recipe.
I suppose I have to apply several tunings since I'm working with a PC with
i7-2600 Intel Core CPU, right?
Here you have the screenshots of some starting phases on
On 09/05/2014 08:46 AM, Siva Durga Prasad Paladugu wrote:
> Update the ci_udc driver to support bulk transfer
> and also added capability of having multiple dtds
> if requested data is more thank 16K.
> These changes are tested for both the DFU and lthor.
>
> Signed-off-by: Siva Durga Prasad Palad
Hi Hans,
> So it seems that I'm not the only one seeing this, and I've been wrongly
> blaming it on the A33, instead it seems to be a kernel bug, triggered
> on my A33 due to the display resolution it has.
>
> For details see:
>
> http://www.spinics.net/lists/arm-kernel/msg413811.html
That's go
Hi Fei,
On Tue, Apr 28, 2015 at 7:36 AM, WANG FEI wrote:
> Meng Bin,
>
> I remember few weeks I've built a u-boot binary for Galileo, but I remember
> the generated u-boot.bin is not 256/512/1024/2048K, it possible is about
> 384K, is it correct? I want to use the u-boot you built as a reference.
It should be #ifdef instead of #if.
Signed-off-by: Bin Meng
---
arch/x86/lib/tables.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c
index b390a4b..0836e1e 100644
--- a/arch/x86/lib/tables.c
+++ b/arch/x86/lib/tables.c
@@ -23,7
Hi Francesco,
On Tue, Apr 28, 2015 at 4:40 PM, Francesco Lucconi wrote:
> Here you have the 512 bytes of MBR within the Virtual Disk Image (VID) of
> virtualbox. As you can notice there's not clearly the string "Error!"
> mentioned on previous screenshot.
> About MBR building to ease the procedur
2015-04-28 12:45 GMT+02:00 Bin Meng :
> Hi Francesco,
>
> On Tue, Apr 28, 2015 at 4:40 PM, Francesco Lucconi
> wrote:
> > Here you have the 512 bytes of MBR within the Virtual Disk Image (VID) of
> > virtualbox. As you can notice there's not clearly the string "Error!"
> > mentioned on previous s
>
> #ifdef CONFIG_FMAN_ENET
> #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
> -#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
> +#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
> +#elif defined(CONFIG_T1040D4RDB) || defined(CONFIG_T1042D4RDB)
> +#define CONFIG_SYS_SGMII1_PHY_AD
On 27 April 2015 at 08:56, haikun.w...@freescale.com
wrote:
> On 4/24/2015 11:55 PM, Simon Glass wrote:
>> Hi Haikun,
>>
>> On 24 April 2015 at 07:22, Haikun Wang wrote:
>>> Atmel DataFlash chips have commands different from common spi
>>> flash commands.
>>> Atmel DataFlash also have special pag
This could happen if we are being chainloaded by Coreboot with LPAE
enabled, as is the case on the Tegra-based Chromebooks.
Signed-off-by: Tomeu Vizoso
---
arch/arm/lib/cache-cp15.c | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
inde
I am new to this project. But I am so interested with it and I want to dive
into it. Where should I start ?
--
This is my life,but world of us~~
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Hi,
On 24 April 2015 at 22:33, Simon Glass wrote:
> These functions now rely on uclass_find_first/next_device() and assume that
> they will either return failure (-ve error code) or a device. In fact,
> coming to the end of a list is not considered failure and they return 0
> in that case.
>
> Th
From: Siva Durga Prasad Paladugu
Increase max sizes for OOB, Page size and eccpos to
suit for Micron MT29F32G08 part
Signed-off-by: Siva Durga Prasad Paladugu
---
include/linux/mtd/mtd.h | 2 +-
include/linux/mtd/nand.h | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/
Added initial nand driver support for arasan nand flash
controller.This supports nand erase,nand read, nand write
This uses the hardware ECC for read and write operations
Signed-off-by: Siva Durga Prasad Paladugu
---
drivers/mtd/nand/Makefile |1 +
drivers/mtd/nand/arasan_nfc.c | 1187 ++
Hi Jagan,
I didn't get chance to look at the series. Could you give me some time till
next week as I am little busy this week.
Regards,
Siva
> -Original Message-
> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
> Sent: Monday, April 27, 2015 8:32 PM
> To: u-boot@lists.denx.de; Siva
Hi Siva,
On 28 April 2015 at 18:21, Siva Durga Prasad Paladugu
wrote:
> Hi Jagan,
>
> I didn't get chance to look at the series. Could you give me some time till
> next week as I am little busy this week.
No issues, If something that I send it for v2 I will let you know.
>> -Original Messa
On 25 April 2015 at 14:18, Gabriel Huau wrote:
> Signed-off-by: Gabriel Huau
> ---
> Changes for v2:
> - Fix ordering of include header
>
> board/intel/minnowmax/minnowmax.c | 9 +
> include/configs/minnowmax.h | 1 +
> 2 files changed, 10 insertions(+)
>
> diff --git a/boa
Hi Gabriel,
On 25 April 2015 at 14:17, Gabriel Huau wrote:
> Every pin can be configured now from the device tree. A dt-bindings
> has been added to describe the different property available.
>
> Signed-off-by: Gabriel Huau
> ---
> Changes for v2:
> - Clean commit message
> - Ren
On 26 April 2015 at 07:54, Bin Meng wrote:
> On Sun, Apr 26, 2015 at 4:16 AM, Gabriel Huau wrote:
>> There are 6 banks:
>> 4 banks for CORE: available in S0 mode
>> 2 banks for SUS (Suspend): available in S0-S5 mode
>>
>> Signed-off-by: Gabriel Huau
>> ---
>> Changes for v2:
>> -
On 26 April 2015 at 07:52, Bin Meng wrote:
> Hi Gabriel,
>
> On Sun, Apr 26, 2015 at 4:16 AM, Gabriel Huau wrote:
>> The correct GPIOBASE address on the baytrail is 0x48
>>
>> Signed-off-by: Gabriel Huau
>> ---
>
> Reviewed-by: Bin Meng
Acked-by: Simon Glass
>
> Please edit your commit messa
On Tuesday, April 28, 2015 at 09:12:09 AM, Ramneek Mehresh wrote:
> Add support for DWC3 XHCI controller driver
>
> Signed-off-by: Ramneek Mehresh
Applied all, thanks!
Best regards,
Marek Vasut
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On Tuesday, April 28, 2015 at 10:59:16 AM, Michal Simek wrote:
> On 09/05/2014 08:46 AM, Siva Durga Prasad Paladugu wrote:
> > Update the ci_udc driver to support bulk transfer
> > and also added capability of having multiple dtds
> > if requested data is more thank 16K.
> > These changes are teste
On 28 April 2015 at 00:24, Hans de Goede wrote:
> Hi Simon,
>
> Thanks for the reviews.
>
>
> On 28-04-15 05:20, Simon Glass wrote:
>>
>> Hi Hans,
>>
>> On 26 April 2015 at 03:51, Hans de Goede wrote:
>>>
>>> Now that all sunxi boards are using driver-model for gpio (*), we can
>>> remove
>>> the
On 26 April 2015 at 08:08, Bin Meng wrote:
> On Sat, Apr 25, 2015 at 11:13 PM, Gabriel Huau
> wrote:
>> The SPI NOR on the minnowboard max is a MICRON N25Q064A
>>
>> Signed-off-by: Gabriel Huau
>> ---
>> Changes for v2:
>> - Update the dts to put the correct flash name
>>
>> arch/x86/d
On 27 April 2015 at 00:16, Bin Meng wrote:
> By default the legacy segments (Ah-Bh, Eh-Fh)
> do not decode to system RAM. Turn on the decode so that we can
> write configuration tables in the F segment.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/x86/cpu/quark/quark.c
On 27 April 2015 at 00:16, Bin Meng wrote:
> Previously the PIRQ routing table sanity check was performed against
> the original table provided by the platform codes. Now we switch to
> check its sanity on the final table in the F segment as this one is
> the one seen by the OS.
>
> Signed-off-by:
Hi Bin,
On 27 April 2015 at 00:16, Bin Meng wrote:
> Intel Quark SoC has the same interrupt routing mechanism as the
> Queensbay platform, only the difference is that PCI devices'
> INTA/B/C/D are harcoded and cannot be changed freely.
>
> Signed-off-by: Bin Meng
>
> ---
>
> arch/x86/cpu/quark/
On 27 April 2015 at 09:22, Bin Meng wrote:
> Move platform-specific options under in arch/x86/Kconfig forward right
> after the board-specific options but before any architecture-specific
> options. When it comes to the same Kconfig option, board-specific one
> takes take the highest precedence, t
On 27 April 2015 at 09:22, Bin Meng wrote:
> Since all x86 boards have been converted to use DM_SPI and
> DM_SPI_FLASH, move them to arch/Kconfig x86 section.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/Kconfig | 2 ++
> arch/x86/Kconfig | 6 --
> 2 files changed, 2 insertions(+), 6 delet
On 27 April 2015 at 09:22, Bin Meng wrote:
> Let arch/x86/Kconfig prompt board vendor first, then select
> the board model under that vendor. This way arch/x86/Kconfig
> only needs concern board vendor and leave the supported target
> list to board//Kconfig.
>
> Signed-off-by: Bin Meng
> ---
>
>
On 27 April 2015 at 09:22, Bin Meng wrote:
> Remove the ending period of the MARK_GRAPHICS_MEM_WRCOMB option. Also
> fix the indention of its help text.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/x86/Kconfig | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
Acked-by: Simon Glass
On 27 April 2015 at 09:22, Bin Meng wrote:
> Currently all x86 boards still use CONFIG_SYS_EXTRA_OPTIONS to define
> the text base address. Since it is deprecated, just remove it and use
> CONFIG_SYS_TEXT_BASE directly.
>
> Signed-off-by: Bin Meng
> ---
>
> Kconfig
On 28 April 2015 at 04:37, Bin Meng wrote:
> It should be #ifdef instead of #if.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/x86/lib/tables.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Acked-by: Simon Glass
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On Mon, Apr 27, 2015 at 11:30:43PM -0300, Fabio Estevam wrote:
> From: Fabio Estevam
>
> There are users of Cuboxi and Hummingboard that use these boards without
> connecting them to a USB/serial adapter.
>
> Allow such usage by allowing the HDMI port to act as stdout and USB keyboard
> as std
On Mon, Apr 27, 2015 at 11:30:44PM -0300, Fabio Estevam wrote:
> From: Fabio Estevam
>
> Let Solidrun's logo appear on Cuboxi and Hummingboard by default.
>
> Signed-off-by: Rabeeh Khoury
> Signed-off-by: Fabio Estevam
Reviewed-by: Tom Rini
--
Tom
signature.asc
Description: Digital sign
On Mon, Apr 27, 2015 at 11:30:41PM -0300, Fabio Estevam wrote:
> From: Fabio Estevam
>
> Add HDMI output using PLL5 as the source for the IPU DI clocks,
> and accurate VESA timings.
>
> These settings are based on the patch from Soeren Moch
> submitted for the tbs2910 mx6 based board.
>
> It
On Mon, Apr 27, 2015 at 11:30:42PM -0300, Fabio Estevam wrote:
> From: Fabio Estevam
>
> Enable USB Host1 port.
>
> Signed-off-by: Rabeeh Khoury
> Signed-off-by: Fabio Estevam
[snip]
> diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h
> index 207a2a6..e7a18c6 100644
> ---
On Fri, Apr 24, 2015 at 12:20:30PM +0200, Daniel Schwierzeck wrote:
> The following changes since commit d8c1d5d5fb6eafbc532982125f006e49f2c40e71:
>
> Merge branch 'buildman' of git://git.denx.de/u-boot-x86 (2015-04-23
> 14:56:47 -0400)
>
> are available in the git repository at:
>
> git:/
On Tue, Apr 28, 2015 at 01:47:35PM +0530, Jagannadha Sutradharudu Teki wrote:
> Hi Tom,
>
> Please pick this PR.
>
> thanks!
> Jagan.
>
> The following changes since commit d77447fdb122dab290fb1ad184a62456011e6e06:
>
> serial: pl01x: fix PL010 regression (2015-04-21 10:05:42 -0400)
>
> are
On Thu, Apr 23, 2015 at 07:17:51PM -0700, York Sun wrote:
> Tom,
>
> I am having trouble cloning git repositories. I hope this pull request was
> generated correctly. I saw "fatal: read error: Connection reset by peer" when
> creating this pull request.
>
> The following changes since commit d77
On Fri, Apr 24, 2015 at 09:37:02AM -0600, Simon Glass wrote:
> Hi Tom,
>
> The following changes since commit d8c1d5d5fb6eafbc532982125f006e49f2c40e71:
>
> Merge branch 'buildman' of git://git.denx.de/u-boot-x86 (2015-04-23
> 14:56:47 -0400)
>
> are available in the git repository at:
>
>
Hi Tom,
please pull from u-boot-imx, thanks !
The following changes since commit f33cdaa4c3da4a8fd35aa2f9a3172f31cc887b35:
Prepare v2015.04 (2015-04-13 10:53:03 -0400)
are available in the git repository at:
git://www.denx.de/git/u-boot-imx.git master
for you to fetch changes up to 205d58
Hi Tom,
On Tue, Apr 28, 2015 at 11:48 AM, Tom Rini wrote:
> Since we have FEC do we really need to add ASIX as well? Also, what
I can remove it if needed. Just kept the same as done in the Solidrun's U-boot.
> devices did you test this with for USB? I grabbed a Sandisk USB drive
> and on the
On Tue, Apr 28, 2015 at 12:11 PM, Fabio Estevam wrote:
> Hi Tom,
>
> On Tue, Apr 28, 2015 at 11:48 AM, Tom Rini wrote:
>
>> Since we have FEC do we really need to add ASIX as well? Also, what
>
> I can remove it if needed. Just kept the same as done in the Solidrun's
> U-boot.
>
>> devices did
On 04/28/2015 07:53 AM, Simon Glass wrote:
Hi Gabriel,
On 25 April 2015 at 14:17, Gabriel Huau wrote:
Every pin can be configured now from the device tree. A dt-bindings
has been added to describe the different property available.
diff --git a/include/dt-bindings/gpio/x86-gpio.h
b/include/
On 28 April 2015 at 07:53, Simon Glass wrote:
> On 26 April 2015 at 07:52, Bin Meng wrote:
>> Hi Gabriel,
>>
>> On Sun, Apr 26, 2015 at 4:16 AM, Gabriel Huau
>> wrote:
>>> The correct GPIOBASE address on the baytrail is 0x48
>>>
>>> Signed-off-by: Gabriel Huau
>>> ---
>>
>> Reviewed-by: Bin Me
On 28 April 2015 at 07:53, Simon Glass wrote:
> On 26 April 2015 at 07:54, Bin Meng wrote:
>> On Sun, Apr 26, 2015 at 4:16 AM, Gabriel Huau
>> wrote:
>>> There are 6 banks:
>>> 4 banks for CORE: available in S0 mode
>>> 2 banks for SUS (Suspend): available in S0-S5 mode
>>>
>>> Signed-o
On 28 April 2015 at 07:59, Simon Glass wrote:
> On 26 April 2015 at 08:08, Bin Meng wrote:
>> On Sat, Apr 25, 2015 at 11:13 PM, Gabriel Huau
>> wrote:
>>> The SPI NOR on the minnowboard max is a MICRON N25Q064A
>>>
>>> Signed-off-by: Gabriel Huau
>>> ---
>>> Changes for v2:
>>> - Updat
On 28 April 2015 at 08:05, Simon Glass wrote:
> On 27 April 2015 at 00:16, Bin Meng wrote:
>> By default the legacy segments (Ah-Bh, Eh-Fh)
>> do not decode to system RAM. Turn on the decode so that we can
>> write configuration tables in the F segment.
>>
>> Signed-off-by: Bin Me
On 28 April 2015 at 08:04, Simon Glass wrote:
> On 27 April 2015 at 00:16, Bin Meng wrote:
>> Previously the PIRQ routing table sanity check was performed against
>> the original table provided by the platform codes. Now we switch to
>> check its sanity on the final table in the F segment as this
On 25 April 2015 at 11:46, Simon Glass wrote:
> The descriptor provided with the FSP does not seem to work. Update the
> instructions to use the descriptor from the original Intel firmware.
>
> Signed-off-by: Simon Glass
> ---
>
> doc/README.x86 | 23 ---
> 1 file changed, 20
On 28 April 2015 at 08:11, Simon Glass wrote:
> On 27 April 2015 at 09:22, Bin Meng wrote:
>> Let arch/x86/Kconfig prompt board vendor first, then select
>> the board model under that vendor. This way arch/x86/Kconfig
>> only needs concern board vendor and leave the supported target
>> list to bo
On 28 April 2015 at 08:12, Simon Glass wrote:
> On 27 April 2015 at 09:22, Bin Meng wrote:
>> Since all x86 boards have been converted to use DM_SPI and
>> DM_SPI_FLASH, move them to arch/Kconfig x86 section.
>>
>> Signed-off-by: Bin Meng
>> ---
>>
>> arch/Kconfig | 2 ++
>> arch/x86/Kconfi
On 28 April 2015 at 08:12, Simon Glass wrote:
> On 27 April 2015 at 09:22, Bin Meng wrote:
>> Move platform-specific options under in arch/x86/Kconfig forward right
>> after the board-specific options but before any architecture-specific
>> options. When it comes to the same Kconfig option, board
On 28 April 2015 at 08:13, Simon Glass wrote:
> On 28 April 2015 at 04:37, Bin Meng wrote:
>> It should be #ifdef instead of #if.
>>
>> Signed-off-by: Bin Meng
>> ---
>>
>> arch/x86/lib/tables.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> Acked-by: Simon Glass
Applied to u-bo
On 28 April 2015 at 08:12, Simon Glass wrote:
> On 27 April 2015 at 09:22, Bin Meng wrote:
>> Currently all x86 boards still use CONFIG_SYS_EXTRA_OPTIONS to define
>> the text base address. Since it is deprecated, just remove it and use
>> CONFIG_SYS_TEXT_BASE directly.
>>
>> Signed-off-by: Bin M
On 28 April 2015 at 08:12, Simon Glass wrote:
> On 27 April 2015 at 09:22, Bin Meng wrote:
>> Remove the ending period of the MARK_GRAPHICS_MEM_WRCOMB option. Also
>> fix the indention of its help text.
>>
>> Signed-off-by: Bin Meng
>> ---
>>
>> arch/x86/Kconfig | 8
>> 1 file changed,
The MX6 has OTP bits specifying the processor speed grade as well as
temperature grade.
This series adds functions to return this information as well as adds the
details to the CPU info displayed.
Additionally we use the temperature grade to replace the hard-coded limits
in imx_thermal.c
I expec
The IMX6 has four different speed grades determined by eFUSE SPEED_GRADING
(OCOTP_CFG3[17:16]).
Display this value to make it clear the difference regarding the CPU speed
currently running at vs the max speed allowed per grade. Note that the power
on CPU speed is determined by OCOTP_CFG4[18].
I s
Replace the hard-coded values for min/max/passive with values derived from
the CPU temperature grade.
Cc: Ye.Li
Signed-off-by: Tim Harvey
---
drivers/thermal/imx_thermal.c | 29 +++--
1 file changed, 19 insertions(+), 10 deletions(-)
diff --git a/drivers/thermal/imx_the
The MX6 has a temperature grade defined by OCOTP_MEM0[7:6].
While the MX6SX also has temperature grades, I see no mention in the reference
manual where that information is stored in the OTP.
Signed-off-by: Tim Harvey
---
arch/arm/cpu/armv7/mx6/soc.c | 32 +++
Signed-off-by: Tim Harvey
---
arch/arm/include/asm/arch-mx6/imx-regs.h | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h
b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 9a4ad8b..35bb005 100644
--- a/arch/arm/include/asm/arch-mx6/im
Rijay,
On 04/28/2015 04:15 AM, Ciubotariu Codrin Constantin-B43658 wrote:
>>
>> #ifdef CONFIG_FMAN_ENET
>> #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
>> -#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
>> +#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
>> +#elif defined(CONFI
On 28 April 2015 at 14:51, Wandy Lau wrote:
> I am new to this project. But I am so interested with it and I want to dive
> into it. Where should I start ?
What you what to start with, see this wiki[1] for all details about
u-boot project
like documentation, development process, source code and e
On 27 April 2015 at 11:13, S Durga Prasad Paladugu
wrote:
> Hi All,
>
> I want to know whether we have FAT file system formatting support in u-boot?
> I would like to format my SD card from u-boot.
Probably formatting does it on host machine mostly.
+ Pantelis Antoniou may give more details.
th
Oleks,
I suggest to change the subject to "powerpc/mpc85xx: Add board support for
ucp1020".
On 04/15/2015 12:37 PM, Oleksandr G Zhadan wrote:
> New QorIQ p1020 based board support from Arcturus Networks Inc.
> http://www.arcturusnetworks.com/products/ucp1020/
>
> Signed-off-by: Michael Durrant
Oleks,
Suggest to change subject to "powerpc/mpc85xx: Fix compiling error for
common/cmd_gpio.c".
It would be helpful to put the compiling error into commit message.
On 04/15/2015 12:17 PM, Oleksandr G Zhadan wrote:
> 1. Include asm/mpc85xx_gpio.h into asm/gpio.h
> 2. Fix Incompatibility in func
On Tue, Apr 28, 2015 at 12:20:46PM -0300, Fabio Estevam wrote:
> On Tue, Apr 28, 2015 at 12:11 PM, Fabio Estevam wrote:
> > Hi Tom,
> >
> > On Tue, Apr 28, 2015 at 11:48 AM, Tom Rini wrote:
> >
> >> Since we have FEC do we really need to add ASIX as well? Also, what
> >
> > I can remove it if ne
On 22/04/2015 17:37, Nikolay Dimitrov wrote:
> This is proposal for clamping the MMDC/DDR3 clocks to the maximum supported
> frequencies as per imx6 SOC models, and for dynamically calculating valid
> clock value based on mem_speed.
>
> Currently the code uses impossible values for mem_speed (1333
On Tue, Apr 28, 2015 at 12:39:41PM -0400, Tom Rini wrote:
> On Tue, Apr 28, 2015 at 12:20:46PM -0300, Fabio Estevam wrote:
> > On Tue, Apr 28, 2015 at 12:11 PM, Fabio Estevam wrote:
> > > Hi Tom,
> > >
> > > On Tue, Apr 28, 2015 at 11:48 AM, Tom Rini wrote:
> > >
> > >> Since we have FEC do we re
On Tue, Apr 28, 2015 at 6:39 PM, Tom Rini wrote:
> On Tue, Apr 28, 2015 at 12:20:46PM -0300, Fabio Estevam wrote:
> > On Tue, Apr 28, 2015 at 12:11 PM, Fabio Estevam
> wrote:
> > > Hi Tom,
> > >
> > > On Tue, Apr 28, 2015 at 11:48 AM, Tom Rini wrote:
> > >
> > >> Since we have FEC do we really
On Tue, Apr 28, 2015 at 1:45 PM, Jon Nettleton wrote:
...
> Is CONFIG_SYS_USB_EVENT_POLL defined in the config? I found that without
> that usb input was not reliable. Even with it enabled some wireless
> keyboards behaved poorly.
For the keyboard it may indeed help but what about the USB pendr
On Tue, Apr 28, 2015 at 06:45:43PM +0200, Jon Nettleton wrote:
> On Tue, Apr 28, 2015 at 6:39 PM, Tom Rini wrote:
>
> > On Tue, Apr 28, 2015 at 12:20:46PM -0300, Fabio Estevam wrote:
> > > On Tue, Apr 28, 2015 at 12:11 PM, Fabio Estevam
> > wrote:
> > > > Hi Tom,
> > > >
> > > > On Tue, Apr 28,
On Tue, Apr 28, 2015 at 1:52 PM, Tom Rini wrote:
> On Tue, Apr 28, 2015 at 06:45:43PM +0200, Jon Nettleton wrote:
>> On Tue, Apr 28, 2015 at 6:39 PM, Tom Rini wrote:
>>
>> > On Tue, Apr 28, 2015 at 12:20:46PM -0300, Fabio Estevam wrote:
>> > > On Tue, Apr 28, 2015 at 12:11 PM, Fabio Estevam
>> >
Hi Tim,
On 28.04.2015 17:44, Tim Harvey wrote:
The MX6 has OTP bits specifying the processor speed grade as well as
temperature grade.
This series adds functions to return this information as well as adds the
details to the CPU info displayed.
Additionally we use the temperature grade to repla
On Tue, Apr 28, 2015 at 10:11 AM, Stefan Roese wrote:
> Hi Tim,
>
> On 28.04.2015 17:44, Tim Harvey wrote:
>>
>> The MX6 has OTP bits specifying the processor speed grade as well as
>> temperature grade.
>>
>> This series adds functions to return this information as well as adds the
>> details to
To replicate:
1. add to include/configs/p1_p2_rdb_pc.h "#define CONFIG_CMD_GPIO"
2. run `make P1020RDB-PC_defconfig`
3. run CROSS_COMPILE=powerpc-linux- make
and you will get:
common/built-in.o: In function `do_gpio':
u-boot/common/cmd_gpio.c:186: undefined reference to `gpio_request'
u-boot/commo
Hi Joakim,
On Mon, Apr 27, 2015 at 8:39 AM, Joakim Tjernlund
wrote:
> Trying to get a better handle of HUSH shell expressions, this does not work
> as I expect:
> => false && true || echo ECHO
> => false && false || echo ECHO
>
> none prints ECHO, seems like a bug?
I think it works as it should
Dear Joe Hershberger,
On 04/28/2015 11:00 AM, Joe Hershberger wrote:
Hi Joakim,
On Mon, Apr 27, 2015 at 8:39 AM, Joakim Tjernlund
wrote:
Trying to get a better handle of HUSH shell expressions, this does not work as
I expect:
=> false && true || echo ECHO
=> false && false || echo ECHO
none
Hi James,
On Tue, Apr 28, 2015 at 1:19 PM, James Chargin wrote:
> Dear Joe Hershberger,
>
> On 04/28/2015 11:00 AM, Joe Hershberger wrote:
>>
>> Hi Joakim,
>>
>> On Mon, Apr 27, 2015 at 8:39 AM, Joakim Tjernlund
>> wrote:
>>>
>>> Trying to get a better handle of HUSH shell expressions, this does
On Tue, Apr 28, 2015 at 1:52 PM, Tom Rini wrote:
>> Is CONFIG_SYS_USB_EVENT_POLL defined in the config? I found that without
>> that usb input was not reliable. Even with it enabled some wireless
>> keyboards behaved poorly.
>
> Just checked and yes it's set. I think I also had these not worki
Dear Joe,
On 04/28/2015 11:35 AM, Joe Hershberger wrote:
Hi James,
On Tue, Apr 28, 2015 at 1:19 PM, James Chargin wrote:
Dear Joe Hershberger,
On 04/28/2015 11:00 AM, Joe Hershberger wrote:
Hi Joakim,
On Mon, Apr 27, 2015 at 8:39 AM, Joakim Tjernlund
wrote:
Trying to get a better handl
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