Drop warnings in get_cpu_rev and changes the return value
(a u32 instead of char * is returned) of the function
to be coherent with other processors.
Signed-off-by: Stefano Babic
CC: Detlev Zundev
CC: Fabio Estevam
---
This is a follow-up patch of "MX31: drop warnings in get_cpu_rev",
as this
The tsec driver was defining the default MDIO address as
the TSEC_BASE + 0x520, but on eTSEC2 controllers, the first
TSEC's registers are separated from the MDIO registers. Use
the existing MDIO_BASE_ADDR, instead.
Signed-off-by: Andy Fleming
---
include/tsec.h |2 +-
1 files changed, 1 inse
On Wed, Apr 27, 2011 at 2:12 PM, Wolfgang Denk wrote:
> Dear Andy Fleming,
>
> In message you wrote:
>>
>> > From now on, follow the general rule "mmc dev [dev]" to change the
>> > mmc command applied device, like ide and usb...
> ...
>> I'd really prefer if there were still the option to specify
On Wed, Apr 27, 2011 at 10:44 PM, Lei Wen wrote:
>>> - mmc_init(mmc);
>>> + return 0;
>>> + } else if (strncmp(argv[1], "part", 4) == 0) {
>>> + block_dev_desc_t *mmc_dev;
>>> + struct mmc *mmc = find_mmc_device(mmc_cur_dev);
>
are available in the git repository at:
git://www.denx.de/git/u-boot-mmc.git master
Jason Liu (1):
fsl_esdhc: Fix multi-block read restriction on i.MX53 eSDHCv2
John Rigby (2):
MMC: make b_max unconditional
MMC: omap_hsmmc.c: disable multiblock rw on old rev omap34xx silicon
Hi Macpaul,
> cmd_bdinfo.c: clean up with 2.6.38 checkpatch.pl
>
> Signed-off-by: Macpaul Lin
Looks sane to me, thanks!
Acked-by: Detlev Zundel
--
Peace of mind isn't at all superficial to technical work. It's the
whole thing. That which produces it is good work and that which
destroys
Hi Macpaul,
> Hi Detlev,
>
> 2011/4/27 Detlev Zundel :
>> Hi Macpaul,
>>
>>> clean up with 2.6.38 checkpatch.pl
>>
>> There is indeed only one non-whitespace hunk in there:
>> It's ok that you do the line wrapping, but actually with such lists we
>> require alphabetical sorting of the clauses, so
Hi Igor,
[...]
> +1 to all said above, though some minor patching should be done:
>
> u-boot $ grep -rn machine_is_ --exclude=mach-types.h *
> arch/arm/cpu/arm920t/at91rm9200/ether.c:204:if (machine_is_csb337()) {
> board/ti/omap1610inn/omap1610innovator.c:66:if (machine_is_omap_h2())
> b
Hi Detlev,
> "Correct" threading however uses "References:" mail headers and can cope
> with changing subjects. Somehow you seem to know this, as v3 indeed
> _has_ such a correct header and thus the threading in my mail reader
> works just fine ;)
>
Yes. I did fix the References and In-reply-to
Hi Amarendra,
> Hi Wolfgang Denk,
>
> Thank you for the reply. Yes I am talking about "redundant environment".
>
> If we have four "redundant environment" copies in the same
> partition(mtd1)... Does the below fw_env.config configuration hold
> good ?
U-Boot cannot cope with more than two redunda
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DATUM DER NACHRICHT: 29.04.2011 12:00
ERGEBNISSE: Benachrichtigt
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Dear Andy Fleming,
In message you wrote:
>
> It's just that the other way would also be possible. I re-read the
> thread where this was discussed, and while I definitely agree that the
> originally proposed solution was highly error-prone, I think
> *allowing* users to do this is fine:
>
> mmc r
Dear Detlev Zundel,
In message you wrote:
>
> > Since I've correct the subject of this patch v3 according to the
> > "cosmetic" rule,
> > it seems patch v3 is out of this mailing thread.
>
> This change of the subject was the reason why I did not require you
> changing it as I know that Wolfgan
Dear Valerio Bardelli,
In message <4dba7d2e.5000...@microhard.biz> you wrote:
>
> we have a board based on AT91SAM9263 (Atmel) CPU and we use your U-Boot
> to debug the hardware and to boot OpenEmbedded Linux. Very good free
> product! ;))
The at91sam9263ek board is supported in Mainline U-Boot
This is a Delivery Status Notification (DSN).
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vjsyn...@vsnl.com.
I said
RCPT TO:
And they gave me the error;
550 5.1.1 unknown or illegal alias: vjsyn...@vsnl.com
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Dear John Rigby,
In message you wrote:
> Here a first draft design doc. It is based in part on the Fastboot
> implementation in the rowboat git repo (pointer below).
Thanks.
> Hooks into U-Boot
> =
>
> Fastboot gets access to the USB subsystem via the same interfaces as USB_TT
Hi John,
> Here a first draft design doc. It is based in part on the Fastboot
> implementation in the rowboat git repo (pointer below).
Thanks for this piece of documentation. Itcertainly helped me
understand that the "boot" part in fastboot is kind of a misnomer,
right?
Again it shows that a
Hi Mike,
> On Wed, Apr 27, 2011 at 11:25, Detlev Zundel wrote:
>> Now that we have the documentation, the code should be changed to reflect
>> it ;)
>>
>> Asd far as I can see, these are the places where HW_WATCHDOG is used
>> instead of WATCHDOG:
>
> the trouble is that watchdog.h doesnt seem to
Hi Macpaul,
>> "Correct" threading however uses "References:" mail headers and can cope
>> with changing subjects. Somehow you seem to know this, as v3 indeed
>> _has_ such a correct header and thus the threading in my mail reader
>> works just fine ;)
>>
>
> Yes. I did fix the References and In-
Hi Wolfgang,
[...]
>> This change of the subject was the reason why I did not require you
>> changing it as I know that Wolfgang currently matches patch versions by
>> subject strings.
>
> This is not quite correct. I refer to the Subject: only if no other
> thread information is present, i. e.
Hi Stefano,
> Drop warnings in get_cpu_rev and changes the return value
> (a u32 instead of char * is returned) of the function
> to be coherent with other processors.
>
> Signed-off-by: Stefano Babic
> CC: Detlev Zundev
Can you please correct the spelling of my name? Thanks.
> CC: Fabio Este
Hi Ben,
> In a future commit the behaviour of nand_write_skip_bad()
> will be further extended.
>
> Convert the only flag currently passed to the nand_write_
> skip_bad() function to a bitfield of only one allocated
> member. This should avoid an explosion of int's at the
> end of the parameter li
Hi Ben,
> Add another nand write. variant, ubi. This command will request of
> nand_write_skip_bad() that all trailing all-0xff pages will be
> dropped from eraseblocks as they are written as-per the
> reccommended behaviour of the UBI FAQ.
If I understand the code correctly, then the assumption
Hi Ben,
> It was found that on da850evm, where the NAND ECC used does not map all 0xff
> data to 0xff ECC, that flashing UBI and JFFS2 image from U-boot with nand
> write[.e] command resulted in alot of ECC errors... for UBI the result was
> an unmountable filesystem on second attach from linux. F
On 04/29/2011 01:36 PM, Detlev Zundel wrote:
> Hi Stefano,
>
>> Drop warnings in get_cpu_rev and changes the return value
>> (a u32 instead of char * is returned) of the function
>> to be coherent with other processors.
>>
>> Signed-off-by: Stefano Babic
>> CC: Detlev Zundev
>
> Can you please
On Apr 29, 2011, at 2:26 AM, Andy Fleming wrote:
> The tsec driver was defining the default MDIO address as
> the TSEC_BASE + 0x520, but on eTSEC2 controllers, the first
> TSEC's registers are separated from the MDIO registers. Use
> the existing MDIO_BASE_ADDR, instead.
>
> Signed-off-by: Andy
On Apr 26, 2011, at 3:31 AM, Shaohui Xie wrote:
> From: Mingkai Hu
>
> Signed-off-by: Mingkai Hu
> Singed-off-by: Jerry Huang
> Signed-off-by: Shaohui Xie
> Cc: Mike Frysinger
> ---
> changes for v2:
> remove #ifdef wrapper and refactor spi_xfer by use SPI_XFER(BEGIN | END).
> remove 'volat
On Apr 21, 2011, at 1:54 PM, Kumar Gala wrote:
> From: Jerry Huang
>
> Signed-off-by: Jerry Huang
> Signed-off-by: Zhao Chenhui
> Signed-off-by: Kumar Gala
> ---
> boards.cfg|1 +
> include/configs/P2020DS.h | 28
> 2 files changed, 29 inserti
On Apr 21, 2011, at 1:54 PM, Kumar Gala wrote:
> From: Priyanka Jain
>
> Also added support to save env to spi flash in case of SPIBOOT.
>
> Signed-off-by: Priyanka Jain
> Signed-off-by: Kumar Gala
> ---
> include/configs/P1_P2_RDB.h | 18 --
> 1 files changed, 16 insertions
On Apr 21, 2011, at 1:54 PM, Kumar Gala wrote:
> From: Jiang Yutang
>
> Signed-off-by: Jiang Yutang
> Signed-off-by: Kumar Gala
> ---
> board/freescale/p1022ds/p1022ds.c |3 +++
> include/configs/P1022DS.h | 15 +++
> 2 files changed, 18 insertions(+), 0 deletions(-)
On Apr 22, 2011, at 8:34 AM, Kumar Gala wrote:
> From: Timur Tabi
>
> SerDes PLL bandwidth default setting is incorrect when no lanes are
> configured as PCI Express.
>
> Signed-off-by: Timur Tabi
> Signed-off-by: Kumar Gala
> ---
> arch/powerpc/cpu/mpc85xx/cmd_errata.c |3 ++
> a
On Apr 22, 2011, at 8:34 AM, Kumar Gala wrote:
> From: Timur Tabi
>
> The work-around for P4080 erratum SERDES-8 requires all lanes of banks two
> and three to be disabled (powered down) in the RCW. Display a warning
> message if this is not the case.
>
> Signed-off-by: Timur Tabi
> Signed-o
On Apr 22, 2011, at 8:34 AM, Kumar Gala wrote:
> From: Timur Tabi
>
> Part of the SERDES9 erratum work-around is to set some bits in the SerDes
> TTLCR0 register for lanes configured as XAUI, SGMII, SRIO, or AURORA. The
> current code does this only for XAUI, so extend it to the other protocol
On Apr 22, 2011, at 8:34 AM, Kumar Gala wrote:
> From: Timur Tabi
>
> Bank powerdown through RCW[SRDS_LPD_Bn] for XAUI on FM2 and SGMII on FM1
> are swapped.
>
> Erratum SERDES-A001 says that if bank two is kept disabled and after bank
> three is enabled, then the PLL for bank three won't lock
On Apr 21, 2011, at 1:52 PM, Kumar Gala wrote:
> From: Lei Xu
>
> The workaround for ESDHC111 should also be applied on
> P2040/P3041/P5010/P5020 SoCs.
>
> Signed-off-by: Lei Xu
> Signed-off-by: Roy Zang
> Signed-off-by: Kumar Gala
> ---
> arch/powerpc/include/asm/config_mpc85xx.h |4 ++
On Apr 21, 2011, at 1:52 PM, Kumar Gala wrote:
> From: Kim Phillips
>
> versioned SEC properties changed names during development, so
> for now search and update LIODNs for both "secX.Y" and
> "sec-vX.Y" based properties.
>
> Signed-off-by: Kim Phillips
> Signed-off-by: Kumar Gala
> ---
> ar
On Apr 27, 2011, at 10:39 PM, Kumar Gala wrote:
> Introduce new CONFIG_SYS_FSL_TBCLK_DIV on 85xx platforms because
> different SoCs have different divisor amounts. All the PQ3 parts are
> /8, the P4080/P4080 is /16, and P2040/P3041/P5020 are /32.
>
> Signed-off-by: Kumar Gala
> ---
> * Added R
On Apr 12, 2011, at 2:10 PM, Kumar Gala wrote:
> From: Roy Zang
>
> The P2040, P3041, P5010, and P5020 all have internal USB PHYs that we
> need to enable for them to function.
>
> Signed-off-by: Roy Zang
> Signed-off-by: Kumar Gala
> ---
> arch/powerpc/cpu/mpc85xx/cpu_init.c | 17 ++
On Apr 9, 2011, at 1:47 PM, Kumar Gala wrote:
> The P3041DS & P5020DS boards are almost identical (except for the
> processor in them). Additionally they are based on the P4080DS board
> design so we use the some board code for all 3 boards.
>
> Some ngPIXIS (FPGA) registers where reserved on P
On Apr 9, 2011, at 3:40 PM, Kumar Gala wrote:
> From: Emil Medve
>
> Rework and add some new APIs to the fsl_corenet_serdes code for use by
> erratum and drivers.
>
> * Rename serdes_get_bank() to serdes_get_bank_by_lane()
> * Add serdes_get_first_lane returns which SERDES lane is used by devi
On Apr 9, 2011, at 3:40 PM, Kumar Gala wrote:
> From: Emil Medve
>
> Signed-off-by: Emil Medve
> Signed-off-by: Timur Tabi
> Signed-off-by: Kumar Gala
> ---
> arch/powerpc/cpu/mpc85xx/cmd_errata.c |3 +
> arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 107 +++
On Apr 9, 2011, at 12:55 PM, Kumar Gala wrote:
> From: Haiying Wang
>
> Fix fdt bportal to pass the bman revision number to kernel via device tree.
>
> Signed-off-by: Haiying Wang
> Signed-off-by: Kumar Gala
> ---
> arch/powerpc/cpu/mpc85xx/fdt.c |1 +
> arch/powerpc/cpu/mpc85xx/p
On Apr 9, 2011, at 1:22 PM, Kumar Gala wrote:
> From: Ramneek Mehresh
>
> Second USB controller only works for SPI and SD boot because of pin muxing
>
> Signed-off-by: Ramneek Mehresh
> ---
> arch/powerpc/include/asm/immap_85xx.h |1 +
> board/freescale/p1_p2_rdb/p1_p2_rdb.c | 14 +++
On Apr 9, 2011, at 12:54 PM, Kumar Gala wrote:
> From: Dipen Dudhat
>
> To make sure that machine change operation work successfully, change
> timing parameters first before changing machine for chip select on IFC.
>
> Signed-off-by: Dipen Dudhat
> Signed-off-by: Kumar Gala
> ---
> arch/powe
On Apr 9, 2011, at 12:49 PM, Kumar Gala wrote:
> From: Dipen Dudhat
>
> Signed-off-by: Dipen Dudhat
> Signed-off-by: Kumar Gala
> ---
> arch/powerpc/include/asm/immap_85xx.h | 71 +
> 1 files changed, 71 insertions(+), 0 deletions(-)
applied to 85xx
- k
On Apr 9, 2011, at 12:49 PM, Kumar Gala wrote:
> From: Priyanka Jain
>
> If we boot from a SD card use it for the environment as well.
>
> Signed-off-by: Priyanka Jain
> Signed-off-by: Poonam Aggrwal
> Signed-off-by: Kumar Gala
> ---
> include/configs/P1_P2_RDB.h |6 +-
> 1 files cha
On Apr 28, 2011, at 9:55 PM, Kumar Gala wrote:
> CONFIG_SYS_BOOTMAPSZ has been 64M on these boards for some time so we
> should also allow the kernel image to be up to 64M decompressed. This
> also matches what we pass to the OS based on the ePAPR specification.
>
> Signed-off-by: Kumar Gala
>
Hi Stefano,
[...]
>>> @@ -129,7 +129,7 @@ char *get_cpu_rev(void)
>>> for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
>>> if (srev == mx31_cpu_type[i].srev)
>>> return mx31_cpu_type[i].v;
>>> - return "unknown";
>>> + return srev;
>>
>> Hm, so we d
The following changes since commit a000b7950da938d2df37ec5e081cd0680e6e4bbe:
common: add a grepenv command (2011-04-28 01:00:07 +0200)
are available in the git repository at:
git://git.denx.de/u-boot-mpc85xx.git master
Andy Fleming (1):
tsec: Fix MDIO on devices with eTSEC2
Dipen Dudh
Hi,
> 1/ Get the latest DIRENT
> For example, if you create a file in linux jffs2 which config summary
> support, then you delete the file , you will not see the file in
> linux jffs2. But you can also see this file in uboot after you reset
> the system. That is because all the nodes in jffs
Hi Baidu,
> 1/ We should calculate the buf_len before we call
> get_fl_mem().
If I read your change correctly, then do you mean the following?
When we know what we want to read, we can calculate buf_len to be the
maximum size of the data to be read. Without this, we usually read
EMPTY_S
Hi Baidu,
> Check the return value when we do malloc.
>
> Signed-off-by: Baidu Liu
> ---
> fs/jffs2/jffs2_1pass.c | 12 ++--
> fs/jffs2/jffs2_nand_1pass.c |5 -
> 2 files changed, 14 insertions(+), 3 deletions(-)
>
> diff --git a/fs/jffs2/jffs2_1pass.c b/fs/jffs2/jffs2_1p
Hi Baidu,
> 1/ Syncs up with jffs2 in the linux kernel:
> If the first 256 Bytes is 0xff,we get the conclusion
> that the sector is empty.
>
> Signed-off-by: Baidu Liu
> ---
> fs/jffs2/jffs2_1pass.c | 11 ++-
> fs/jffs2/jffs2_nand_1pass.c | 13 ++---
> include/jffs2/j
Hi Baidu,
> 1/ Sync with kernel.
> If the 256-(struct jffs2_unknown_node *) bytes are
> 0xff after the cleanmarker. We get the conclusion that
> the sector is empty.
>
> Signed-off-by: Baidu Liu
> ---
> fs/jffs2/jffs2_1pass.c | 19 +--
> 1 files changed, 13 insertions(+), 6
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Hi, Detlev :
2011/4/29 Detlev Zundel :
> Hi,
>
>> 1/ Get the latest DIRENT
>> For example, if you create a file in linux jffs2 which config summary
>> support, then you delete the file , you will not see the file in
>> linux jffs2. But you can also see this file in uboot after you reset
>>
On Fri, 2011-04-29 at 13:58 +0200, Detlev Zundel wrote:
> Hi Ben,
>
> > It was found that on da850evm, where the NAND ECC used does not map all 0xff
> > data to 0xff ECC, that flashing UBI and JFFS2 image from U-boot with nand
> > write[.e] command resulted in alot of ECC errors... for UBI the res
Drop warnings in get_cpu_rev and changes the return value
(a u32 instead of char * is returned) of the function
to be coherent with other processors.
Signed-off-by: Stefano Babic
CC: Detlev Zundel
CC: Fabio Estevam
---
Changes:
- commit message
- "unknown" will be printed together with the
The compatible property for the L2 cache node (on 85xx systems that don't
have a CPC) was using a value for the property length that did not match
the actual length of the property.
Signed-off-by: Timur Tabi
---
arch/powerpc/cpu/mpc85xx/fdt.c | 13 +++--
1 files changed, 7 insertions(+
Andy Fleming wrote:
> The tsec driver was defining the default MDIO address as
> the TSEC_BASE + 0x520, but on eTSEC2 controllers, the first
> TSEC's registers are separated from the MDIO registers. Use
> the existing MDIO_BASE_ADDR, instead.
>
> Signed-off-by: Andy Fleming
Acked-by: Timur Tabi
Hi,Detlev
2011/4/29 Detlev Zundel :
> Hi Baidu,
>
>> 1/ We should calculate the buf_len before we call
>> get_fl_mem().
>
> If I read your change correctly, then do you mean the following?
>
> When we know what we want to read, we can calculate buf_len to be the
> maximum size of the data to b
Hi,Detlev
2011/4/29 Detlev Zundel :
> Hi Baidu,
>
>> 1/ We should calculate the buf_len before we call
>> get_fl_mem().
>
> If I read your change correctly, then do you mean the following?
>
> When we know what we want to read, we can calculate buf_len to be the
> maximum size of the data to b
On Apr 29, 2011, at 9:08 AM, Timur Tabi wrote:
> The compatible property for the L2 cache node (on 85xx systems that don't
> have a CPC) was using a value for the property length that did not match
> the actual length of the property.
>
> Signed-off-by: Timur Tabi
> ---
> arch/powerpc/cpu/mpc85
Kumar Gala wrote:
> Can we do:
> ""fsl,mpc%s-l2-cache-controller" "%c" "cache",
> cpu->name, 0);
>
> just for readability?
>
Sure, but couldn't you have told me that before you asked me to post it
upstream? :-)
--
Timur Tabi
Linux kernel developer at Freescale
_
The compatible property for the L2 cache node (on 85xx systems that don't
have a CPC) was using a value for the property length that did not match
the actual length of the property.
Signed-off-by: Timur Tabi
---
arch/powerpc/cpu/mpc85xx/fdt.c | 13 +++--
1 files changed, 7 insertions(+
Hi, Detlev
>> @@ -1470,9 +1471,16 @@ jffs2_1pass_build_lists(struct part_info * part)
>> /* lcd_off(); */
>>
>> /* if we are building a list we need to refresh the cache. */
>> - jffs_init_1pass_list(part);
>> + if(! jffs_init_1pass_list(part))
>> + return 0;
>> +
Hi, Detlev :
>> default:
>> /* unknown */
>> - putLabeledWord("UNKOWN COMPRESSION
>> METHOD = ", jNode->compr);
>> + putLabeledWord("UNKNOWN COMPRESSION
>>
Hi,Detlev
>> + }
>> +
>
> This has style-problems. Actually all of your patches have style
> problems. Checking them as one single patch gives:
>
> total: 32 errors, 22 warnings, 369 lines checked
>
> Please rework the whole series.
I do not know why my patch has sty
Hi Stefano,
> Drop warnings in get_cpu_rev and changes the return value
> (a u32 instead of char * is returned) of the function
> to be coherent with other processors.
>
> Signed-off-by: Stefano Babic
> CC: Detlev Zundel
> CC: Fabio Estevam
> ---
>
> Changes:
> - commit message
> - "unknown" wi
On Apr 29, 2011, at 9:58 AM, Timur Tabi wrote:
> The compatible property for the L2 cache node (on 85xx systems that don't
> have a CPC) was using a value for the property length that did not match
> the actual length of the property.
>
> Signed-off-by: Timur Tabi
> ---
> arch/powerpc/cpu/mpc85
On Apr 14, 2011, at 12:39 PM, Kyle Moffett wrote:
> Signed-off-by: Kyle Moffett
> ---
> arch/powerpc/cpu/mpc8xxx/ddr/util.c | 18 +-
> 1 files changed, 9 insertions(+), 9 deletions(-)
applied to 85xx
- k
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The following changes since commit a000b7950da938d2df37ec5e081cd0680e6e4bbe:
common: add a grepenv command (2011-04-28 01:00:07 +0200)
are available in the git repository at:
git://git.denx.de/u-boot-mpc85xx.git master
Andy Fleming (1):
tsec: Fix MDIO on devices with eTSEC2
Dipen Dudh
I'm attempting to extend u-boot to request some IPMI information from a
BMC attached to a uart, and was wondering how best to approach the
problem. My first concern is whether to add "cmd" type code or use the
u-boot API, and the second concern, is to how to configure and access
the 2nd serial por
On Apr 18, 2011, at 9:47 PM, Zhao Chenhui wrote:
> Convert the PCI base address into a virtual address.
>
> Signed-off-by: Zhao Chenhui
> Signed-off-by: Li Yang
> ---
> drivers/usb/host/ehci-pci.c |5 ++---
> 1 files changed, 2 insertions(+), 3 deletions(-)
Remy,
any comments or acceptanc
Hi Baidu,
> Hi, Detlev :
>
> 2011/4/29 Detlev Zundel :
>> Hi,
>>
>>> 1/ Get the latest DIRENT
>>> For example, if you create a file in linux jffs2 which config summary
>>> support, then you delete the file , you will not see the file in
>>> linux jffs2. But you can also see this file in uboo
Hi Baidu,
[...]
>>> diff --git a/fs/jffs2/jffs2_1pass.c b/fs/jffs2/jffs2_1pass.c
>>> index 8eb77b1..be6ac78 100644
>>> --- a/fs/jffs2/jffs2_1pass.c
>>> +++ b/fs/jffs2/jffs2_1pass.c
>>> @@ -1643,6 +1643,8 @@ jffs2_1pass_build_lists(struct part_info * part)
>>> case JFFS2_NODE
Hi Baidu,
> Hi, Detlev
>
>
>>> @@ -1470,9 +1471,16 @@ jffs2_1pass_build_lists(struct part_info * part)
>>> /* lcd_off(); */
>>>
>>> /* if we are building a list we need to refresh the cache. */
>>> - jffs_init_1pass_list(part);
>>> + if(! jffs_init_1pass_list(part))
>>> +
On Fri, Apr 29, 2011 at 10:34 AM, Kumar Gala wrote:
> Timur Tabi (7):
> powerpc/86xx: remove empty board_early_init_f()
> powerpc/fsl: add 'pixis_reset dump' command
> powerpc/85xx: Implement work-around for P4080 erratum SERDES-A005
> powerpc/85xx: Display SERDES 8 erratum war
We've been bitten by the PPC405EX CHIP_21 erratum. I've looked through the
U-Boot code, but it doesn't appear that there is a work-around for this one.
The following patch is my adaptation of AMCC's suggestion as to the fix. But
I have to say that I don't care for it, if for no other reason that
On Apr 29, 2011, at 12:36 PM, Tabi Timur-B04825 wrote:
>
> What about this patch:
>
> http://patchwork.ozlabs.org/patch/71614/
>
> It was ACK'd by gvb:
>
> http://lists.denx.de/pipermail/u-boot/2011-April/089791.html
I'd rather we just fix the addresses up rather than verifying them.
- k
__
On Fri, 29 Apr 2011 15:16:59 -0500
Kumar Gala wrote:
>
> On Apr 29, 2011, at 12:36 PM, Tabi Timur-B04825 wrote:
>
> >
> > What about this patch:
> >
> > http://patchwork.ozlabs.org/patch/71614/
> >
> > It was ACK'd by gvb:
> >
> > http://lists.denx.de/pipermail/u-boot/2011-April/089791.html
Dear Timur Tabi,
In message <1304089126-11945-1-git-send-email-ti...@freescale.com> you wrote:
> The compatible property for the L2 cache node (on 85xx systems that don't
> have a CPC) was using a value for the property length that did not match
> the actual length of the property.
>
> Signed-off
Dear Kumar Gala,
In message <8188c4ac-9553-4f2d-9370-9416d63af...@freescale.com> you wrote:
>
> On Apr 29, 2011, at 9:58 AM, Timur Tabi wrote:
>
> > The compatible property for the L2 cache node (on 85xx systems that don't
> > have a CPC) was using a value for the property length that did not ma
On Apr 29, 2011, at 10:34 AM, Kumar Gala wrote:
> The following changes since commit a000b7950da938d2df37ec5e081cd0680e6e4bbe:
>
> common: add a grepenv command (2011-04-28 01:00:07 +0200)
>
> are available in the git repository at:
> git://git.denx.de/u-boot-mpc85xx.git master
Did another p
Dear Kumar Gala,
In message you
wrote:
>
> The following changes since commit a000b7950da938d2df37ec5e081cd0680e6e4bbe:
>
> common: add a grepenv command (2011-04-28 01:00:07 +0200)
>
> are available in the git repository at:
> git://git.denx.de/u-boot-mpc85xx.git master
NAK. I refuse to
On Apr 29, 2011, at 3:33 PM, Wolfgang Denk wrote:
> Dear Kumar Gala,
>
> In message <8188c4ac-9553-4f2d-9370-9416d63af...@freescale.com> you wrote:
>>
>> On Apr 29, 2011, at 9:58 AM, Timur Tabi wrote:
>>
>>> The compatible property for the L2 cache node (on 85xx systems that don't
>>> have a C
On Apr 29, 2011, at 3:35 PM, Wolfgang Denk wrote:
> Dear Kumar Gala,
>
> In message you
> wrote:
>>
>> The following changes since commit a000b7950da938d2df37ec5e081cd0680e6e4bbe:
>>
>> common: add a grepenv command (2011-04-28 01:00:07 +0200)
>>
>> are available in the git repository at:
The following changes since commit e2b1fb98dab08f18e456fd8d846440fe81567785:
Sandeep Paulraj (1):
Merge branch 'master' of git://git.denx.de/u-boot-arm
are available in the git repository at:
git://git.denx.de/u-boot-ti.git master
Ben Gardiner (1):
da850evm: fix NAND WSTROBE an
Dear Kumar Gala,
In message you wrote:
>
> I was thinking the patch wasn't going to have any additional commentary.
The rule is that we allow _a_few_working_days_ of review time
normally - not just a few minutes.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgan
Dear Kumar Gala,
In message <40b22acd-651c-4765-ba19-421d3abe1...@kernel.crashing.org> you wrote:
>
> Did another push to drop:
>
> * powerpc/85xx: fix compatible property for the L2 cache node
Please send a new pull req when all is ready. Thanks.
Best regards,
Wolfgang Denk
--
DENX Softwa
On Fri, 29 Apr 2011 22:30:58 +0200
Wolfgang Denk wrote:
> Dear Timur Tabi,
>
> In message <1304089126-11945-1-git-send-email-ti...@freescale.com> you wrote:
> > The compatible property for the L2 cache node (on 85xx systems that don't
> > have a CPC) was using a value for the property length tha
[ w/ L2 patch dropped ]
The following changes since commit a000b7950da938d2df37ec5e081cd0680e6e4bbe:
common: add a grepenv command (2011-04-28 01:00:07 +0200)
are available in the git repository at:
git://git.denx.de/u-boot-mpc85xx.git master
Andy Fleming (1):
tsec: Fix MDIO on device
> > nhk8815: move config targets from Makefile to boards.cfg
> >
> > are available in the git repository at:
> >
> >git://git.denx.de/u-boot-ti.git master
> >
> > Ben Gardiner (1):
> >da850evm: fix NAND WSTROBE and TA timings
> >
> > board/davinci/da8xxevm/da850evm.c |4
Dear Andy Fleming,
In message <1304065909-16710-1-git-send-email-aflem...@freescale.com> you wrote:
> are available in the git repository at:
>
> git://www.denx.de/git/u-boot-mmc.git master
>
> Jason Liu (1):
> fsl_esdhc: Fix multi-block read restriction on i.MX53 eSDHCv2
>
> John Rigby
Dear Alper YILDIRIM,
In message <31267662.p...@talk.nabble.com> you wrote:
>
> I found the offending patch, it is the following commit that
> makes usb broken on OMAPL138. When i revert the patch the
> problem no more occurs.
>
> 3c0659b535b075be124c3d2a0714e55e65c46737
> ARM: Avoid compiler op
Dear Scott Wood,
In message <20110429154457.0fee3...@schlenkerla.am.freescale.net> you wrote:
>
> > > len = sprintf(compat_buf,
> > > - "fsl,mpc%s-l2-cache-controller", cpu->name);
> > > + "fsl,mpc%s-l2-cache-controller" "%c" "cache
Wolfgang Denk wrote:
>> > Except that his version works and your version doesn't. With your version
>> > sprintf will stop reading the format string after "controller".
> Yes, and this is why I call this a dirty hack, as it's obfuscating
> what's going on and what the intended result is.
I disag
The compatible property for the L2 cache node (on 85xx systems that don't
have a CPC) was using a value for the property length that did not match
the actual length of the property.
Signed-off-by: Timur Tabi
---
arch/powerpc/cpu/mpc85xx/fdt.c | 20
1 files changed, 12 inse
The compatible property for the L2 cache node (on 85xx systems that don't
have a CPC) was using a value for the property length that did not match
the actual length of the property.
Signed-off-by: Timur Tabi
---
arch/powerpc/cpu/mpc85xx/fdt.c | 20
1 files changed, 12 inse
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