On 04/22/2011 07:45 AM, Jason Hui wrote:
> Hi, Stefano,
Hi Jason,
>>> int checkboard(void)
>>> {
>>> u32 system_rev = get_cpu_rev();
>>> - u32 cause;
>>> - struct src *src_regs = (struct src *)SRC_BASE_ADDR;
>>
>> This seems to me not the best solution. If we have now factored out
On 04/15/2011 10:29 PM, Scott Wood wrote:
>
> nand_scan() is broken into head and tail functions. In Linux, the driver
> calls these, and can look at the chip info before tail is called. In
> U-boot, common code drives this, and the controller driver is not involved
> -- but it would be good to
andes_spi is an spi interface developed by Andes Tech.
Signed-off-by: Macpaul Lin
---
drivers/spi/Makefile|1 +
drivers/spi/andes_spi.c | 302 +++
drivers/spi/andes_spi.h | 128
3 files changed, 431 insertions(+), 0 delet
Convert all the comments at the top of the file into help text for people
to easily get at with standard -h/--help options.
Signed-off-by: Mike Frysinger
---
MAKEALL | 100 +++
1 files changed, 49 insertions(+), 51 deletions(-)
diff -
Wolfgang Denk wrote on 2011/04/20 22:13:35:
>
> Dear Joakim Tjernlund,
>
> In message
> you
> wrote:
> >
> > OK, I managed to script the change, patch last in mail.
>
> Thanks.
>
> > However CROSS_COMPILE=powerpc-softfloat-linux-gnu- ./MAKEALL TQM862L
> > TQM855L TQM860L
> > does not build fo
Hi, Stefano,
2011/4/22 Stefano Babic :
> On 04/22/2011 07:45 AM, Jason Hui wrote:
>> Hi, Stefano,
>
> Hi Jason,
>
int checkboard(void)
{
u32 system_rev = get_cpu_rev();
- u32 cause;
- struct src *src_regs = (struct src *)SRC_BASE_ADDR;
>>>
>>> This seems to
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Hi, Stefano,
2011/4/22 Stefano Babic :
> On 04/22/2011 06:36 AM, Jason Hui wrote:
>>
>> OK, I will resend the patchset as the following layout:
>>
>> MX5: clock: Add clock config interface
>> MX5: factor out boot cause funciton to common code
>> PMIC: Add dialog pmic support
>> MX53: support for f
Dear Graeme Russ,
In message <4db0cf2f.2020...@gmail.com> you wrote:
>
> > That said, if someone wants to maintain a U-Boot version, that'd be great.
>
> So, if someone maintains a U-Boot fork of checkpatch, keeps it up-to-date
> with the Linux version, and pushes patches back up to Linux (to kee
Dear Zach Pfeffer,
In message you wrote:
>
> So, "Google uses it aside", it seems that being able to boot via USB
> is a useful thing and fastboot is a particular solution; I'm not
> entirely sure what other USB u-boot extensions exist apart from those
Well, DFU support is a standard solution, a
On 04/22/2011 10:33 AM, Jason Liu wrote:
>
> Is there any rule that we need must follow to set the
> CONFIG_SYS_MEMTEST_START
> CONFIG_SYS_MEMTEST_END ??
There is no rule, it was only a question if there are some specific reasons.
>
> If no, I think the value we set is free. Here I set for 64KB
From: Mingkai Hu
Signed-off-by: Mingkai Hu
Singed-off-by: Jerry Huang
Signed-off-by: Shaohui Xie
Cc: Mike Frysinger
---
changes for v2:
remove #ifdef wrapper and refactor spi_xfer by use SPI_XFER(BEGIN | END).
remove 'volatile' use I/O accessors instead.
changes for v3:
move powerpc specific
espi flash read returns invalid data if the read length is more than 0xFFFA
bytes, it supports maximum transaction of 2^16 bytes at a time, resister
spcom[TRANLEN] is 16 bits. If the transaction length is greater than 0x,
it need to be split into multiple transactions.
Signed-off-by: Shaohui
>From: vapierfil...@gmail.com [mailto:vapierfil...@gmail.com] On Behalf Of
>Mike Frysinger
>Sent: Friday, April 22, 2011 1:17 AM
>To: Xie Shaohui-B21989
>Cc: u-boot@lists.denx.de; Gala Kumar-B11780; Zang Roy-R61911
>Subject: Re: [PATCH 2/2][v2] powerpc: make espi can read more than 0xFFFA
>bytes
>
On 22/04/11 18:54, Wolfgang Denk wrote:
> Dear Graeme Russ,
>
> In message <4db0cf2f.2020...@gmail.com> you wrote:
>>
>>> That said, if someone wants to maintain a U-Boot version, that'd be great.
>>
>> So, if someone maintains a U-Boot fork of checkpatch, keeps it up-to-date
>> with the Linux ver
On 22/04/11 16:18, Albert ARIBAUD wrote:
> Le 22/04/2011 02:43, Graeme Russ a écrit :
>
>> So, if someone maintains a U-Boot fork of checkpatch, keeps it up-to-date
>> with the Linux version, and pushes patches back up to Linux (to keep them
>> is sync as much as practicable possible) would we agr
On Thu, Apr 21, 2011 at 1:59 PM, Kumar Gala wrote:
> Introduce new CONFIG_SYS_FSL_TBCLK_DIV on 85xx platforms because
> different SoCs have different divisor amounts. All the PQ3 parts are
> /8, the P4080/P4080 is /16, and P2040/P3041/P5020 are /32.
Shouldn't there also be a README update to doc
Dear Jason Liu,
In message you wrote:
>
> > I think the only issue is if there is some reasons to set the test range
> > to only 64KB, except the fact this was the value set for the mx51evk. If
> > you do not see any special reasons, you could increase the
> > CONFIG_SYS_MEMTEST_END to a larger
On 2011/04/20 12:17 PM, Rogan Dawes wrote:
> Now if I can just figure out how to write to my flash using OpenOCD, I
> can hopefully recover.
>
> Regards,
>
> Rogan
Phew! Thanks to Albert's sloflash utility, I was finally able to get
something back into my flash, and get the board booting again.
Dear Graeme Russ,
In message <4db15dd7.8050...@gmail.com> you wrote:
>
> > I think it wouldbe even better if we could push our changes back into
> > the "mainline" version of checkpatch, so that the U-Boot specific
> > behaviour can beenabled by a command line option (checkpatch --uboot ?).
> >
>
Hi Albert,
my new pull request. Take care that I drop patches for the MX53 LOCO
board as discussed on the mailing list (they were part of last pull
request, commit 96c1b214b47416ae07aac267e45a600cc9567eed in uboot-arm).
This pull is against u-boot tree, as after dropping the patches I
rebased on i
The boot cause code has been factor out to soc common
code,we need drop the part from the board support code
This patch also remove the redundant cpu version print
Signed-off-by: Jason Liu
---
changes since v1
-include more clean up by remove the redundant cpu version print
---
board/efikamx/ef
Add clock config interface support, so that we
can configure CPU or DDR clock in the later init
Signed-off-by: Jason Liu
---
arch/arm/cpu/armv7/mx5/clock.c | 551 +-
arch/arm/include/asm/arch-mx5/clock.h|4 +
arch/arm/include/asm/arch-mx5/crm_regs.h
Add dialog pmic(DA9053) driver with I2C interface support
Signed-off-by: Jason Liu
---
drivers/misc/Makefile |1 +
drivers/misc/dialog_pmic.c | 123 +
include/da9053.h | 186
3 files changed, 310 insert
This patch add initial support for freescale MX53LOCO board.
Network(FEC),SD/MMC,UART have been supported by this patch
The patch also config CPU:1GHZ,DDR:400MHZ for better peformance
Signed-off-by: Jason Liu
---
Changes since v5:
- merge the "Add power init support" patch
changes since v4:
- re
Hi, Wolfgang,
2011/4/22 Wolfgang Denk :
> Dear Jason Liu,
>
> In message you wrote:
>>
>> > I think the only issue is if there is some reasons to set the test range
>> > to only 64KB, except the fact this was the value set for the mx51evk. If
>> > you do not see any special reasons, you could inc
* add USB host support to eb_cpux9k2 board
Signed-off-by: Jens Scharsig
---
include/configs/eb_cpux9k2.h | 16 +++-
1 files changed, 15 insertions(+), 1 deletions(-)
diff --git a/include/configs/eb_cpux9k2.h b/include/configs/eb_cpux9k2.h
index 754fc8b..9d99f65 100644
--- a/inc
On Apr 22, 2011, at 6:50 AM, Tabi Timur-B04825 wrote:
> On Thu, Apr 21, 2011 at 1:59 PM, Kumar Gala wrote:
>> Introduce new CONFIG_SYS_FSL_TBCLK_DIV on 85xx platforms because
>> different SoCs have different divisor amounts. All the PQ3 parts are
>> /8, the P4080/P4080 is /16, and P2040/P3041/P
From: Timur Tabi
Part of the SERDES9 erratum work-around is to set some bits in the SerDes
TTLCR0 register for lanes configured as XAUI, SGMII, SRIO, or AURORA. The
current code does this only for XAUI, so extend it to the other protocols.
Signed-off-by: Timur Tabi
Signed-off-by: Kumar Gala
-
From: Timur Tabi
Bank powerdown through RCW[SRDS_LPD_Bn] for XAUI on FM2 and SGMII on FM1
are swapped.
Erratum SERDES-A001 says that if bank two is kept disabled and after bank
three is enabled, then the PLL for bank three won't lock properly. The
work-around is to enable and then disable bank
From: Timur Tabi
The work-around for P4080 erratum SERDES-8 requires all lanes of banks two
and three to be disabled (powered down) in the RCW. Display a warning
message if this is not the case.
Signed-off-by: Timur Tabi
Signed-off-by: Kumar Gala
---
arch/powerpc/cpu/mpc85xx/fsl_corenet_serd
From: Timur Tabi
SerDes PLL bandwidth default setting is incorrect when no lanes are
configured as PCI Express.
Signed-off-by: Timur Tabi
Signed-off-by: Kumar Gala
---
arch/powerpc/cpu/mpc85xx/cmd_errata.c |3 ++
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 48 +++
Kumar Gala wrote:
> The
> work-around is to enable and then disable bank two after bank three is
> disabled.
That should say, "after bank three is enabled".
--
Timur Tabi
Linux kernel developer at Freescale
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On Apr 22, 2011, at 8:47 AM, Tabi Timur-B04825 wrote:
> Kumar Gala wrote:
>> The
>> work-around is to enable and then disable bank two after bank three is
>> disabled.
>
> That should say, "after bank three is enabled".
Will fix when I apply
- k
___
Le 22/04/2011 14:45, Rogan Dawes a écrit :
> On 2011/04/20 12:17 PM, Rogan Dawes wrote:
>> Now if I can just figure out how to write to my flash using OpenOCD, I
>> can hopefully recover.
>>
>> Regards,
>>
>> Rogan
>
> Phew! Thanks to Albert's sloflash utility, I was finally able to get
> something
On 04/22/2011 02:55 PM, Jason Liu wrote:
> Add dialog pmic(DA9053) driver with I2C interface support
>
Hi Jason,
> diff --git a/drivers/misc/dialog_pmic.c b/drivers/misc/dialog_pmic.c
> new file mode 100644
> index 000..95dc6ea
> --- /dev/null
> +++ b/drivers/misc/dialog_pmic.c
> @@ -0,0 +1,
Hi, Stefano,
2011/4/22 Stefano Babic :
> On 04/22/2011 02:55 PM, Jason Liu wrote:
>> Add dialog pmic(DA9053) driver with I2C interface support
>>
>
> Hi Jason,
>
>> diff --git a/drivers/misc/dialog_pmic.c b/drivers/misc/dialog_pmic.c
>> new file mode 100644
>> index 000..95dc6ea
>> --- /dev/nu
>> So, "Google uses it aside", it seems that being able to boot via USB
>> is a useful thing and fastboot is a particular solution; I'm not
>> entirely sure what other USB u-boot extensions exist apart from those
>
> Well, DFU support is a standard solution, and the LF / CELF has just
> recently as
On Fri, 22 Apr 2011 08:26:55 -0500
Kumar Gala wrote:
>
> On Apr 22, 2011, at 6:50 AM, Tabi Timur-B04825 wrote:
>
> > On Thu, Apr 21, 2011 at 1:59 PM, Kumar Gala
> > wrote:
> >> Introduce new CONFIG_SYS_FSL_TBCLK_DIV on 85xx platforms because
> >> different SoCs have different divisor amounts.
Le 22/04/2011 14:50, Stefano Babic a écrit :
> Hi Albert,
>
> my new pull request. Take care that I drop patches for the MX53 LOCO
> board as discussed on the mailing list (they were part of last pull
> request, commit 96c1b214b47416ae07aac267e45a600cc9567eed in uboot-arm).
> This pull is against u
On Fri, Apr 22, 2011 at 8:26 AM, Kumar Gala wrote:
>> Shouldn't there also be a README update to document this option?
>
> I think its self evident what it is.
I have to disagree. Without reading the patch description, it's hard
to know what value to choose for this macro. Besides, Wolfgang is
On Fri, Apr 22, 2011 at 4:30 AM, Shaohui Xie wrote:
> --- a/include/spi.h
> +++ b/include/spi.h
> /*---
> + * Representation of a SPI slave data.
> + * div16: whether System clock/16 is the input to the eSPI BRG.
> + * pm:
On Fri, Apr 22, 2011 at 3:20 AM, Macpaul Lin wrote:
> +#ifdef DEBUG
> +#define debug(fmt, args...) printf(fmt, ##args)
> +#else
> +#define debug(fmt, args...)
> +#endif
common.h already provides this for you
> +void andes_spi_spit_en(struct andes_spi_slave *ds)
> +{
> + debug("%s: dcr: %
Hi Mike,
> + ds->slave.bus = bus;
> > + ds->slave.cs = cs;
> > + ds->regs = (struct andes_spi_regs *)CONFIG_SYS_SPI_BASE;
> > + ds->freq = max_hz;
>
>
your spi controller has no frequency limit ? your spi_claim_bus
> indicates that there is ...
>
>
Hey, it really strange b
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