> On Mon, Jan 30, 2012 at 7:53 PM, Marek Vasut wrote:
> > Hi Fabio, did they also test stepping through the power_init() ?
>
> They tested stepping using their standalone code, not U-boot.
>
> Regards,
>
> Fabio Estevam
Can you jab me on G? I'm on the problem and I have a possible suspect.
___
On Mon, Jan 30, 2012 at 7:53 PM, Marek Vasut wrote:
> Hi Fabio, did they also test stepping through the power_init() ?
They tested stepping using their standalone code, not U-boot.
Regards,
Fabio Estevam
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h
Hi Fabio,
>>> Could you please post a patch with your proposed change so that we can test
>>> it?
Still working on it. Got delayed by an incompatibility between the SoC and an
SD-Card
controller. I'm the only software developer currently on this project, so I
swich
back-and-forth all the time.
> Hi Robert,
>
> On Wed, Jan 25, 2012 at 2:36 PM, Robert Deliën wrote:
> > Hi Fabio,
> >
> >> Could you please post a patch with your proposed change so that we can
> >> test it?
> >
> > I was hoping for a suggestion from you, as you know this SoC far better
> > than me. Currently I am trying d
Hi Robert,
On Wed, Jan 25, 2012 at 2:36 PM, Robert Deliën wrote:
> Hi Fabio,
>
>> Could you please post a patch with your proposed change so that we can test
>> it?
>
> I was hoping for a suggestion from you, as you know this SoC far better than
> me.
> Currently I am trying different solutions
>> When I swap power_init and mem_init though, the board boots fine, othervise
>> it
>> hangs.
>
> Ok, so looks like this is not compiler related issue then.
I will try this too. I've noticed that mem_init also touched PLL bypass, etc.
I'm starting to wonder if we need to touch PLL bypass in po
> On Thu, Jan 26, 2012 at 4:32 PM, Marek Vasut wrote:
> > Hi Fabio,
> >
> > I bought a really crappy custom board a few days ago (some china-made
> > crap) sporting mx287, but apparently I'm hitting similar issue you do
> > here.
> >
> > When I swap power_init and mem_init though, the board boot
On Thu, Jan 26, 2012 at 4:32 PM, Marek Vasut wrote:
> Hi Fabio,
>
> I bought a really crappy custom board a few days ago (some china-made crap)
> sporting mx287, but apparently I'm hitting similar issue you do here.
>
> When I swap power_init and mem_init though, the board boots fine, othervise i
> Hi Robert,
>
> On 1/25/12, Marek Vasut wrote:
> >> Shouldn't we configure clkctrl_frac0 - or at least disable CPU clock
> >> gating - before disabling PLL bypass?
> >
> > This seems reasonable. Fabio, can you comment?
>
> Could you please post a patch with your proposed change so that we can
>> My 'fix' as it is now, doesn't fix any real problem. It's not finished yet.
>> As it looks now, it makes the JTAG connection unreliable. Data is getting
>> corrupted when it's read or written. However, the system no longer hangs
>> up itself.
>
> That IS a progress.
Progress is made, but no co
> > Robert ... do you really want to cooperate and help fix stuff mainline or
> > do you want to keep everyone in blind, make them guess/help you and when
> > you fix something, never come back and have the fix only for yourself?
>
> Well, given my very verbose thread start, including oscillograph
> Robert ... do you really want to cooperate and help fix stuff mainline or do
> you
> want to keep everyone in blind, make them guess/help you and when you fix
> something, never come back and have the fix only for yourself?
Well, given my very verbose thread start, including oscillographs, it i
> > From your previous email, it looked like that was proper solution. You
> > can still send a patch so we can test and proceed further in sync.
>
> I will send it in, as soon as I have a solution that enables instruction
> stepping through this code.
>
> > What do you mean?
>
> If my 'solution
> From your previous email, it looked like that was proper solution. You can
> still
> send a patch so we can test and proceed further in sync.
I will send it in, as soon as I have a solution that enables instruction
stepping through
this code.
> What do you mean?
If my 'solution' doesn't enab
> Hi Fabio,
>
> > Could you please post a patch with your proposed change so that we can
> > test it?
>
> I was hoping for a suggestion from you, as you know this SoC far better
> than me. Currently I am trying different solutions. Even though they
> prevent the system from hanging up, they still
Hi Fabio,
> Could you please post a patch with your proposed change so that we can test
> it?
I was hoping for a suggestion from you, as you know this SoC far better than me.
Currently I am trying different solutions. Even though they prevent the system
from
hanging up, they still don't enable
Hi Robert,
On 1/25/12, Marek Vasut wrote:
>> Shouldn't we configure clkctrl_frac0 - or at least disable CPU clock
>> gating - before disabling PLL bypass?
>
> This seems reasonable. Fabio, can you comment?
Could you please post a patch with your proposed change so that we can test it?
Regards,
> Hi Marek/Fabio,
>
> I think there's an error in code setting up the CPU clock in the
> SPL for the i.MX28. When instruction stepping through
> mx28_power_clock2pll in spl_power_init.c, the processor drops dead
> right after PLL bypass has been disabled.
Stepping through the code is not recommen
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