On 02/08/2014 07:01 AM, Marek Vasut wrote:
> On Friday, February 07, 2014 at 05:24:27 PM, Stephen Warren wrote:
>> On 02/07/2014 06:48 AM, Marek Vasut wrote:
>>> On Friday, February 07, 2014 at 07:48:06 AM, Stephen Warren wrote:
On 02/06/2014 07:53 PM, Marek Vasut wrote:
> On Thursday, Feb
On Friday, February 07, 2014 at 05:24:27 PM, Stephen Warren wrote:
> On 02/07/2014 06:48 AM, Marek Vasut wrote:
> > On Friday, February 07, 2014 at 07:48:06 AM, Stephen Warren wrote:
> >> On 02/06/2014 07:53 PM, Marek Vasut wrote:
> >>> On Thursday, February 06, 2014 at 09:13:06 PM, Stephen Warren
On 02/07/2014 06:48 AM, Marek Vasut wrote:
> On Friday, February 07, 2014 at 07:48:06 AM, Stephen Warren wrote:
>> On 02/06/2014 07:53 PM, Marek Vasut wrote:
>>> On Thursday, February 06, 2014 at 09:13:06 PM, Stephen Warren wrote:
From: Stephen Warren
These data structures are passe
On Friday, February 07, 2014 at 07:48:06 AM, Stephen Warren wrote:
> On 02/06/2014 07:53 PM, Marek Vasut wrote:
> > On Thursday, February 06, 2014 at 09:13:06 PM, Stephen Warren wrote:
> >> From: Stephen Warren
> >>
> >> These data structures are passed to cache-flushing routines, and hence
> >>
On 02/06/2014 07:53 PM, Marek Vasut wrote:
> On Thursday, February 06, 2014 at 09:13:06 PM, Stephen Warren wrote:
>> From: Stephen Warren
>>
>> These data structures are passed to cache-flushing routines, and hence
>> must be conform to both the USB the cache-flusing alignment requirements.
>> Tha
On Thursday, February 06, 2014 at 09:13:06 PM, Stephen Warren wrote:
> From: Stephen Warren
>
> These data structures are passed to cache-flushing routines, and hence
> must be conform to both the USB the cache-flusing alignment requirements.
> That means aligning to USB_DMA_MINALIGN. This is imp
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