Hi Bin,
Sorry for the late.
I applied the patch and it seems to work. I'll do more tests. Thanks.
Regards,
Hilbert
This e-mail and its attachment may contain PEGATRON Corp information that is
confidential or privileged, and are solely for the use of the individual to
whom this e-mail is addres
Hi Bin,
As the earlier post, do you have any comments? Thanks.
Regards,
Hilbert
This e-mail and its attachment may contain PEGATRON Corp information that is
confidential or privileged, and are solely for the use of the individual to
whom this e-mail is addressed. If you are not the intended rec
Hi Hilbert,
On Wed, Jun 22, 2016 at 2:24 PM, Hilbert Tu(杜睿哲_Pegatron)
wrote:
> Hi Bin,
>
> As the earlier post, do you have any comments? Thanks.
>
Can you try this patch [1] and let me know if it fixes the issue?
[1]: http://patchwork.ozlabs.org/patch/639039/
Regards,
Bin
On Wed, Jun 22, 2016 at 1:19 PM, Yaroslav wrote:
> Hello.
>
> I have a similar problem with U-Boot on Intel Atom C2000.
> And I have found that the issue with the SPI flash is caused by a file
> x86/cpu/coreboot/pci.c which contains an empty driver claiming to be
> compatible with intel,pch7 and i
Hello.
I have a similar problem with U-Boot on Intel Atom C2000.
And I have found that the issue with the SPI flash is caused by a file
x86/cpu/coreboot/pci.c which contains an empty driver claiming to be
compatible with intel,pch7 and intel,pch9. After commenting it out the SPI
flash is being pro
Hi Bin
Thanks for your help.
Following is my dts file for your reference. I use qemu-x86_q35 in u-boot as
dts template. Orginally I think the ops->read_config should maps to
pci_x86_read_config(), but the dump result is it failed in the logic "if
(!ops->read_config)" in pci_bus_read_config()
Hi Hilbert,
On Thu, Jun 16, 2016 at 3:46 PM, Hilbert Tu(杜睿哲_Pegatron)
wrote:
> Hi Bin,
>
> Sorry for the top-posting.
>
> After check the datasheet, I think my SPI address was wrong due to null
> ops->read_config in pci_bus_read_config().
I don't think pci_bus_read_config() has null ops->read_c
Hi Bin,
Sorry for the top-posting.
After check the datasheet, I think my SPI address was wrong due to null
ops->read_config in pci_bus_read_config().
My dts file:
spi: spi {
#address-cells = <1>;
#size-cells = <0>;
+Simon
On Wed, Jun 15, 2016 at 4:42 PM, Hilbert Tu(杜睿哲_Pegatron)
wrote:
> Hi Bin,
>
> Thanks for your information.
>
> The SPI address I mentioned was dumped from pch_get_spi_base(). But I have no
> idea where to check my memory mapping.
You need check your SoC datasheet.
> It is possible that
Hi Hilbert,
On Wed, Jun 15, 2016 at 2:30 PM, Hilbert Tu(杜睿哲_Pegatron)
wrote:
> Hi Simon,
>
> I have checked the SPI base address in coreboot and u-boot. They are
> different. I am not sure is it due to the memory remapping.
> In coreboot, the SPI address is 0xfed0100
> In u-boot, the SPI address
Hi Simon,
I have checked the SPI base address in coreboot and u-boot. They are different.
I am not sure is it due to the memory remapping.
In coreboot, the SPI address is 0xfed0100
In u-boot, the SPI address is 0x7fc36e00
Do you have any comments? Thanks.
Regards,
Hilbert
This e-mail and its att
Hi Hilbert,
On 2 June 2016 at 19:40, Bin Meng wrote:
> Hi Hilbert,
>
> On Thu, Jun 2, 2016 at 11:46 AM, Hilbert Tu(杜睿哲_Pegatron)
> wrote:
>> Hi Bin,
>>
>> Sorry for the late.
>>
>> I have checked with Intel's support and following is their response:
>>
On the other hand, for the question abo
Hi Hilbert,
On Thu, Jun 2, 2016 at 11:46 AM, Hilbert Tu(杜睿哲_Pegatron)
wrote:
> Hi Bin,
>
> Sorry for the late.
>
> I have checked with Intel's support and following is their response:
>
>>>On the other hand, for the question about ICH7 or ICH9. Unfortunately, the
>>>Bios Writers Guides (BWGs) or
]
Sent: Wednesday, June 01, 2016 11:36 AM
To: Hilbert Tu(杜睿哲_Pegatron)
Cc: u-boot@lists.denx.de
Subject: Re: [U-Boot] u-boot-x86 sf probe fail
Hi,
On Tue, May 31, 2016 at 6:14 PM, Hilbert Tu(杜睿哲_Pegatron)
wrote:
> Hi,
>
> I use Coreboot with u-boot-x86 as payload to bring-up my Intel Atom
Hi,
On Tue, May 31, 2016 at 6:14 PM, Hilbert Tu(杜睿哲_Pegatron)
wrote:
> Hi,
>
> I use Coreboot with u-boot-x86 as payload to bring-up my Intel Atom C2000
> platform, but I cannot make my SPI flash(w25q128fv) to work.
> Actually the SPI was detected under coreboot with correct ID, but in u-boot
>
Hi,
I use Coreboot with u-boot-x86 as payload to bring-up my Intel Atom C2000
platform, but I cannot make my SPI flash(w25q128fv) to work.
Actually the SPI was detected under coreboot with correct ID, but in u-boot “sf
probe” command, it just always failed.
After tracing and code dump, I found i
16 matches
Mail list logo