Hi Hilbert, On 2 June 2016 at 19:40, Bin Meng <bmeng...@gmail.com> wrote: > Hi Hilbert, > > On Thu, Jun 2, 2016 at 11:46 AM, Hilbert Tu(杜睿哲_Pegatron) > <hilbert...@pegatroncorp.com> wrote: >> Hi Bin, >> >> Sorry for the late. >> >> I have checked with Intel's support and following is their response: >> >>>>On the other hand, for the question about ICH7 or ICH9. Unfortunately, the >>>>Bios Writers Guides (BWGs) or the EDS is unstated any information about >>>>ICH9. But, reviewing in section 22.4.1 on page 498 of the EDS specifies >>>>that the non-descriptor mode is the same as ICH7 mode. However, the >>>>non-descriptor mode is not supported and a valid Flash Descriptor is >>>>required for this SoC. >> >> So I think the current u-boot cannot support SPI access under Atom C2000 >> with Intel FSP. I am still working on how to read the related registers in >> u-boot since I am not sure the default SPI base address (0x00001fff) is >> correct or not. If you know that, please advise. Thanks. > > I am confused, You said you were booting U-Boot from coreboot, so > U-Boot itself does not use Intel FSP. But here you mentioned Intel > FSP? > > The SPI base address 0x1ffff does not look correct. That's probably > the failure of SPI flash probe.
You started another thread, but can we continue the discussion here? It sounds like you are using coreboot with an FSP. So U-Boot should be able to access SPI flash. I suggest you dig into the SPI driver in coreboot, and see if the SPI base address is the same. I agree with Bin that 1ffff sounds wrong. See the call to pch_get_spi_base() in the U-Boot SPI driver. Regards, Simon _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
