On Tuesday, July 28, 2015 at 09:21:50 PM, Dinh Nguyen wrote:
> On 7/27/15 3:49 PM, Marek Vasut wrote:
> > The current bridge reset code, which de-asserted the bridge reset,
> > was activelly polling whether the FPGA is programmed and ready and
>
> s/activelly/actively
>
> Again...only comment for
On 7/27/15 3:49 PM, Marek Vasut wrote:
> The current bridge reset code, which de-asserted the bridge reset,
> was activelly polling whether the FPGA is programmed and ready and
s/activelly/actively
Again...only comment for this patch, no need to resend.
Dinh
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The current bridge reset code, which de-asserted the bridge reset,
was activelly polling whether the FPGA is programmed and ready and
in case it was (!), the code called hang(). This makes no sense at
all. Repair it such that the code instead checks whether the FPGA
is programmed, but without any p
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