On Wednesday, October 01, 2014 at 08:18:58 AM, Chin Liang See wrote:
> On Sun, 2014-09-21 at 14:58 +0200, ma...@denx.de wrote:
> > This entire series is the second stab at making SoCFPGA usable with
> > mainline U-Boot again. There are much fewer bits missing than in the
> > last series, more clean
On Sun, 2014-09-21 at 14:58 +0200, ma...@denx.de wrote:
> This entire series is the second stab at making SoCFPGA usable with
> mainline U-Boot again. There are much fewer bits missing than in the
> last series, more cleanup happened and bugs were fixed. This allows
> me to use mainline U-Boot on m
On Monday, September 29, 2014 at 01:12:37 PM, Pavel Machek wrote:
> Hi!
>
> > This entire series is the second stab at making SoCFPGA usable with
> > mainline U-Boot again. There are much fewer bits missing than in the
> > last series, more cleanup happened and bugs were fixed. This allows
> > me
Hi!
> This entire series is the second stab at making SoCFPGA usable with
> mainline U-Boot again. There are much fewer bits missing than in the
> last series, more cleanup happened and bugs were fixed. This allows
> me to use mainline U-Boot on my SoCFPGA systems.
You can add my
Acked-by: Pave
On 21.09.2014 14:58, Marek Vasut wrote:
This entire series is the second stab at making SoCFPGA usable with
mainline U-Boot again. There are much fewer bits missing than in the
last series, more cleanup happened and bugs were fixed. This allows
me to use mainline U-Boot on my SoCFPGA systems.
Th
This entire series is the second stab at making SoCFPGA usable with
mainline U-Boot again. There are much fewer bits missing than in the
last series, more cleanup happened and bugs were fixed. This allows
me to use mainline U-Boot on my SoCFPGA systems.
The big missing part is the SPL generation,
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