On Sun, 2014-09-21 at 14:58 +0200, ma...@denx.de wrote: > This entire series is the second stab at making SoCFPGA usable with > mainline U-Boot again. There are much fewer bits missing than in the > last series, more cleanup happened and bugs were fixed. This allows > me to use mainline U-Boot on my SoCFPGA systems. > > The big missing part is the SPL generation, which still needs a lot > of additional work. We also miss the Cadence QSPI controller driver. > > This set contains patches for a few subsystems, which are utilized > by the SoCFPGA, but the most part is the SoCFPGA chip support. This > series now contains cleanup for the mayhem in drivers/fpga/altera.c > code, which was terrible, but is now much better. >
Thanks Marek, I tested this series of patches and here are the outcome I have. SDMMC - Working as I can read and write to SDMMC Boot - Working as I can boot till Linux Ethernet - Seems not working for me. FPGA programming - Seems not working for me too. I will help to look into those features which are not working for me. But this series of patches serves as a good start. Tested-by: Chin Liang See <cl...@altera.com> Thanks Chin Liang _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
