ai Hu
> Subject: RE: [U-Boot] [PATCH] armv8: Enable CPUECTLR.SMPEN for data
> coherency
>
> From: Prabhakar Kushwaha
>
> >> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of york
> >> On 06/30/2016 02:03 AM, Gong Qianyu wrote:
> >> > Fr
gt; Subject: RE: [U-Boot] [PATCH] armv8: Enable CPUECTLR.SMPEN for data
> coherency
>
> From: Prabhakar Kushwaha
>
> >> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of york
> >> On 06/30/2016 02:03 AM, Gong Qianyu wrote:
> >> > From:
From: Prabhakar Kushwaha
>> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of york
>> On 06/30/2016 02:03 AM, Gong Qianyu wrote:
>> > From: Mingkai Hu
>> >
>> > Data coherency is enabled only when the CPUECTLR.SMPEN bit is set.
>> > The SMPEN bit should be set before enabling the
.com
> Cc: Mingkai Hu
> Subject: Re: [U-Boot] [PATCH] armv8: Enable CPUECTLR.SMPEN for data
> coherency
>
> On 06/30/2016 02:03 AM, Gong Qianyu wrote:
> > From: Mingkai Hu
> >
> > Data coherency is enabled only when the CPUECTLR.SMPEN bit is set. The
> &g
lbert.u.b...@aribaud.net; u-
> > b...@lists.denx.de; s.temerkha...@gmail.com;
> > yamada.masah...@socionext.com
> > Cc: Mingkai Hu
> > Subject: Re: [U-Boot] [PATCH] armv8: Enable CPUECTLR.SMPEN for data
> > coherency
> >
> > On 06/30/2016 02:03 AM, Gong Qianyu wro
On Thu, Jun 30, 2016 at 04:51:48PM +0800, Gong Qianyu wrote:
> From: Mingkai Hu
>
> Data coherency is enabled only when the CPUECTLR.SMPEN bit is
> set. The SMPEN bit should be set before enabling the data cache.
> If not enabled, the cache is not coherent with other cores and
> data corruption c
On 06/30/2016 02:03 AM, Gong Qianyu wrote:
> From: Mingkai Hu
>
> Data coherency is enabled only when the CPUECTLR.SMPEN bit is
> set. The SMPEN bit should be set before enabling the data cache.
> If not enabled, the cache is not coherent with other cores and
> data corruption could occur.
>
> Sig
Hi.
2016-06-30 17:51 GMT+09:00 Gong Qianyu :
> From: Mingkai Hu
>
> Data coherency is enabled only when the CPUECTLR.SMPEN bit is
> set. The SMPEN bit should be set before enabling the data cache.
> If not enabled, the cache is not coherent with other cores and
> data corruption could occur.
>
From: Mingkai Hu
Data coherency is enabled only when the CPUECTLR.SMPEN bit is
set. The SMPEN bit should be set before enabling the data cache.
If not enabled, the cache is not coherent with other cores and
data corruption could occur.
Signed-off-by: Mingkai Hu
Signed-off-by: Gong Qianyu
diff
9 matches
Mail list logo
