On Wednesday, August 10, 2011 03:45:11 AM Hong Xu wrote:
> Hi Marek Vasut,
>
> On 08/10/2011 03:55 AM, Marek Vasut wrote:
> > On Tuesday, August 09, 2011 03:57:41 AM Hong Xu wrote:
> >> Hi Marek Vasut,
>
> >> On 08/09/2011 01:34 AM, Marek Vasut wrote:
> [...]
>
> printf("WARNING: %s -
Hi Marek Vasut,
On 08/10/2011 03:55 AM, Marek Vasut wrote:
> On Tuesday, August 09, 2011 03:57:41 AM Hong Xu wrote:
>> Hi Marek Vasut,
>>
>> On 08/09/2011 01:34 AM, Marek Vasut wrote:
[...]
printf("WARNING: %s - start address %x is not aligned\n"
__FUNCTION__, start);
On Tuesday, August 09, 2011 03:57:41 AM Hong Xu wrote:
> Hi Marek Vasut,
>
> On 08/09/2011 01:34 AM, Marek Vasut wrote:
> > On Monday, August 08, 2011 10:01:19 AM Albert ARIBAUD wrote:
> >> Hi Hong Xu,
> >>
> >> Le 08/08/2011 05:20, Hong Xu a écrit :
> >>> After DMA operation, we need to maintain
Hi Marek Vasut,
On Monday 08 August 2011 11:04 PM, Marek Vasut wrote:
> On Monday, August 08, 2011 10:01:19 AM Albert ARIBAUD wrote:
>> Hi Hong Xu,
>>
>> Le 08/08/2011 05:20, Hong Xu a écrit :
>>> After DMA operation, we need to maintain D-Cache coherency.
>>> So that the DCache must be invalidate
Hi Marek Vasut,
On 08/09/2011 01:34 AM, Marek Vasut wrote:
> On Monday, August 08, 2011 10:01:19 AM Albert ARIBAUD wrote:
>> Hi Hong Xu,
>>
>> Le 08/08/2011 05:20, Hong Xu a écrit :
>>> After DMA operation, we need to maintain D-Cache coherency.
>>> So that the DCache must be invalidated (hence CP
Le 08/08/2011 19:34, Marek Vasut a écrit :
>> Thinking more about the degenerate case -- why not round *up* the start
>> address, and round *down* the stop address, that is, *reduce* the area
>> to the aligned portion rather than *expand* it into the unknown? That
>> would make data in "partially
On Monday, August 08, 2011 10:01:19 AM Albert ARIBAUD wrote:
> Hi Hong Xu,
>
> Le 08/08/2011 05:20, Hong Xu a écrit :
> > After DMA operation, we need to maintain D-Cache coherency.
> > So that the DCache must be invalidated (hence CPU will fetch
> > data written by DMA controller from RAM).
> >
Hi Albert,
On 08/08/2011 04:01 PM, Albert ARIBAUD wrote:
> Hi Hong Xu,
>
> Le 08/08/2011 05:20, Hong Xu a écrit :
>> After DMA operation, we need to maintain D-Cache coherency.
>> So that the DCache must be invalidated (hence CPU will fetch
[...]
>> unaligned buffer and only round up/down the bu
Hi Hong Xu,
Le 08/08/2011 05:20, Hong Xu a écrit :
> After DMA operation, we need to maintain D-Cache coherency.
> So that the DCache must be invalidated (hence CPU will fetch
> data written by DMA controller from RAM).
>
> Tested on AT91SAM9261EK with Peripheral DMA controller.
>
> Signed-off-by:
After DMA operation, we need to maintain D-Cache coherency.
So that the DCache must be invalidated (hence CPU will fetch
data written by DMA controller from RAM).
Tested on AT91SAM9261EK with Peripheral DMA controller.
Signed-off-by: Hong Xu
Tested-by: Elen Song
CC: Albert Aribaud
CC: Aneesh V
Le 04/08/2011 05:45, Hong Xu a écrit :
> After DMA transfer, we need to maintain D-Cache coherency.
> We need to clean cache (write back the dirty lines) and then
> make the cache invalidate as well(hence CPU will fetch data
> written by DMA controller from RAM).
>
> Tested on AT91SAM9261EK with Pe
After DMA transfer, we need to maintain D-Cache coherency.
We need to clean cache (write back the dirty lines) and then
make the cache invalidate as well(hence CPU will fetch data
written by DMA controller from RAM).
Tested on AT91SAM9261EK with Peripheral DMA controller.
Signed-off-by: Hong Xu
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