From: Alif Zakuan Yuslaimi
Initialize the actread variable to prevent undefined behavior
that can occur if the variable is used before being assigned a
value.
This will help to prevent potential issues, especially if
actread is used (e.g., read, incremented, or returned) before
being explicitly
From: Tingting Meng
Add defconfig for Agilex7 M-series.
Signed-off-by: Tingting Meng
Signed-off-by: Alif Zakuan Yuslaimi
---
configs/socfpga_agilex7m_defconfig | 19 +++
1 file changed, 19 insertions(+)
create mode 100644 configs/socfpga_agilex7m_defconfig
diff --git a
From: Tingting Meng
Update Makefile to support Agilex7 M-series platform enablement.
Signed-off-by: Tingting Meng
Signed-off-by: Alif Zakuan Yuslaimi
---
arch/arm/mach-socfpga/Makefile | 19 +++
board/intel/agilex7m-socdk/Makefile | 7 +++
2 files changed, 26
From: Tingting Meng
Update Kconfig for new platform Agilex7 M-series.
Signed-off-by: Tingting Meng
Signed-off-by: Alif Zakuan Yuslaimi
---
arch/arm/Kconfig | 2 +-
arch/arm/mach-socfpga/Kconfig | 19 +++
2 files changed, 20 insertions(+), 1 deletion(-)
diff
From: Tingting Meng
Fix wrong memory size calculation in clamshell mode
Signed-off-by: Tingting Meng
Signed-off-by: Alif Zakuan Yuslaimi
---
drivers/ddr/altera/sdram_soc64.c | 16 +++-
drivers/ddr/altera/sdram_soc64.h | 5 +
2 files changed, 20 insertions(+), 1 deletion
From: Tingting Meng
Clean up bit-shift by zero bit
Signed-off-by: Tingting Meng
Signed-off-by: Alif Zakuan Yuslaimi
---
drivers/ddr/altera/sdram_soc64.h | 64
1 file changed, 32 insertions(+), 32 deletions(-)
diff --git a/drivers/ddr/altera/sdram_soc64.h b
.
Signed-off-by: Tingting Meng
Signed-off-by: Alif Zakuan Yuslaimi
---
.../include/mach/base_addr_soc64.h| 6 +-
.../include/mach/system_manager_soc64.h | 3 +
drivers/ddr/altera/Makefile | 1 +
drivers/ddr/altera/sdram_agilex7m.c | 500
with the list of supported mailbox command type and opcode.
Signed-off-by: Tingting Meng
Signed-off-by: Alif Zakuan Yuslaimi
---
drivers/ddr/altera/uibssm_mailbox.c | 321
drivers/ddr/altera/uibssm_mailbox.h | 116 ++
2 files changed, 437 insertions(+)
create
From: Tingting Meng
Agilex7 M-series reuse the clock driver from Agilex.
Signed-off-by: Tingting Meng
Signed-off-by: Alif Zakuan Yuslaimi
---
arch/arm/mach-socfpga/include/mach/clock_manager.h | 4 ++--
arch/arm/mach-socfpga/misc.c | 1 +
drivers/clk/altera/Makefile
roper.
Signed-off-by: Tingting Meng
Signed-off-by: Alif Zakuan Yuslaimi
---
arch/arm/Kconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1de2a895dd4..d7c9e18fa41 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -22,6 +22,9 @@ conf
From: Tingting Meng
Add config header file for new platform Agilex7 M-series.
Signed-off-by: Tingting Meng
Signed-off-by: Alif Zakuan Yuslaimi
---
include/configs/socfpga_agilex7m_socdk.h | 12
1 file changed, 12 insertions(+)
create mode 100644 include/configs
From: Tingting Meng
Add platform related files for new platform Agilex7 M-series.
Signed-off-by: Tingting Meng
Signed-off-by: Alif Zakuan Yuslaimi
---
arch/arm/mach-socfpga/include/mach/misc.h | 3 +-
arch/arm/mach-socfpga/spl_agilex7m.c | 106 ++
board/intel
ux by removing
custom/legacy DTS handling and instead relying on the standardized
definitions provided by the upstream Linux DTS.
Signed-off-by: Tingting Meng
Signed-off-by: Alif Zakuan Yuslaimi
---
arch/arm/dts/Makefile | 1 -
arch/arm/dts/socfpga_agilex-u-boot.dtsi
From: Tingting Meng
Handoff settings updated for new platform Agilex7 M-series.
Signed-off-by: Tingting Meng
Signed-off-by: Alif Zakuan Yuslaimi
---
arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/arm
From: Tingting Meng
To improve help info for bridge enable/disable command.
Signed-off-by: Tingting Meng
Signed-off-by: Alif Zakuan Yuslaimi
---
arch/arm/mach-socfpga/misc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach
From: Tingting Meng
Agilex7 M-series support has been added using upstream Linux DTS.
socfpga_agilex_socdk-u-boot.dtsi was updated to support both Agilex and
Agilex7 M-series platforms.
Signed-off-by: Tingting Meng
Signed-off-by: Alif Zakuan Yuslaimi
---
arch/arm/dts/socfpga_agilex-u
From: Tingting Meng
Reorganize misplaced properties by moving board-common settings from
socfpga_agilex_socdk-u-boot.dtsi to socfpga_agilex-u-boot.dtsi to maintain
proper separation between common and board-level configurations.
Signed-off-by: Tingting Meng
Signed-off-by: Alif Zakuan Yuslaimi
From: Alif Zakuan Yuslaimi
SPL checks for a magic word in the system manager's scratch
register to determine if an L2 reset has occurred. If detected,
SPL places all slave CPUs (CPU1–3) into WFI mode. The master
CPU (CPU0) then initiates a warm reset by writing to the RMR_EL3
system registe
From: Alif Zakuan Yuslaimi
Put all slave CPUs (CPU1-3) into WFI mode. Master CPU (CPU0) writes
the magic word into system manager's scratch register to indicate
the system has performed L2 reset and request reset manager to
perform hardware handshake and then trigger L2 reset. CPU0 put
i
From: Alif Zakuan Yuslaimi
Agilex retrieves its clock manager address via probing its own clock
driver model during the SPL initialization.
Therefore, excluding Agilex from calling its clock driver in misc
driver to retrieve the clock manager address.
Once all SoC64 devices has been
From: Alif Zakuan Yuslaimi
Added environment variables needed to support NAND distro boot
Signed-off-by: Alif Zakuan Yuslaimi
---
include/configs/socfpga_soc64_common.h | 32 +-
1 file changed, 31 insertions(+), 1 deletion(-)
diff --git a/include/configs
From: Alif Zakuan Yuslaimi
The DDR data rate must be set correctly in the DDRIOCTRL
register according to the Actual Clock Frequency (ACF) value.
By enabling the reading of ACF value from bit 18 of the boot
scratch register during initialization, the DDR data rate is
able to be configured
From: Alif Zakuan Yuslaimi
The boot scratch cold reg 8 is shared between DBE, DDR init progress
update and Linux EDAC. This patch defines how the bits are used by
respective features above and their macro names used in U-Boot.
Signed-off-by: Tien Fong Chee
Signed-off-by: Alif Zakuan Yuslaimi
From: Alif Zakuan Yuslaimi
Remove redundant code for MPFE CSR firewall disabled as this was
already set in DTreg dts.
Signed-off-by: Tien Fong Chee
Signed-off-by: Alif Zakuan Yuslaimi
---
drivers/ddr/altera/sdram_agilex.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/ddr
From: Alif Zakuan Yuslaimi
The base address of system manager can be retrieved
using DT framework through the system manager driver.
Enable system manager support for Agilex by probing the
system manager driver to initialize during SPL boot up.
Signed-off-by: Boon Khai Ng
Signed-off-by: Alif
From: Alif Zakuan Yuslaimi
Setting up firewall regions based on SDRAM memory banks configuration
(up to CONFIG_NR_DRAM_BANKS banks) instead of using whole address space.
First 1 MiB (0 to 0xf) of SDRAM is configured as secure region,
other address spaces are non-secure regions. The ARM
From: Alif Zakuan Yuslaimi
Refactor system manager initialization by searching for system manager
alias in Agilex5 device tree instead of manually passing node name to
the device model calling function
Signed-off-by: Alif Zakuan Yuslaimi
---
arch/arm/dts/socfpga_agilex5.dtsi | 4
From: Alif Zakuan Yuslaimi
Enable backup for data section to support warm reset in Agilex SPL as
no SPL image would be reloaded in warm reset.
Signed-off-by: Alif Zakuan Yuslaimi
---
arch/arm/mach-socfpga/spl_agilex.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a
From: Alif Zakuan Yuslaimi
Asynchronous aborts were previously masked at SPL
entry.
To ensure early detection of system errors
such as ECC faults or bus errors, asynchronous aborts
should be explicitly unmasked by clearing the A-bit in
the DAIF register during Agilex SPL initialization.
Signed
From: Alif Zakuan Yuslaimi
Enable watchdog as early as possible after clock initialization
which is set at 10 seconds.
Signed-off-by: Alif Zakuan Yuslaimi
---
arch/arm/mach-socfpga/spl_agilex.c | 10 +-
drivers/watchdog/Kconfig | 2 +-
2 files changed, 10 insertions(+), 2
From: Alif Zakuan Yuslaimi
Replace cm_wait_for_fsm() function with wait_for_bit_le32() function
which supports accurate timeout.
Signed-off-by: Alif Zakuan Yuslaimi
---
drivers/clk/altera/clk-agilex.c | 24
1 file changed, 20 insertions(+), 4 deletions(-)
diff --git
From: Alif Zakuan Yuslaimi
Update exisitng Agilex device tree to support multiple flashes boot
- MMC, QSPI and NAND.
Signed-off-by: Alif Zakuan Yuslaimi
---
MAINTAINERS | 3 ++-
arch/arm/dts/socfpga_agilex.dtsi | 4
arch/arm/dts
From: Alif Zakuan Yuslaimi
Update Agilex SPL code to implement device tree model
for firewall registers setup by using DTreg driver to
probe from device tree for the firewall settings instead
of calling firewall driver function.
Signed-off-by: Alif Zakuan Yuslaimi
---
arch/arm/dts
From: Alif Zakuan Yuslaimi
Combine all MMC, NAND and QSPI configs into single defconfig which is named
as "socfpga_agilex_defconfig". This will be the default defconfig to use.
It supports booting from all three flashes using ARM Trusted Firmware (ATF)
as the secure runtime monitor.
From: Alif Zakuan Yuslaimi
Update the ARMv8 generic timer frequency register (cntfrq_el0)
with the actual hardware timer frequency (COUNTER_FREQUENCY_REAL).
The generic timer frequency was set to 0x2 during boot clk
which needs to be set to 0x4 when transition from boot clk
to
From: Alif Zakuan Yuslaimi
This patch set updates the boot support for the Altera SoCFPGA Agilex7/7M
platform in U-Boot. The changes include:
1. Board-specific configurations and setup required to enable Agilex7/7M
multiboot operation in U-Boot.
2. Integration of
From: Alif Zakuan Yuslaimi
Improve the current clock manager base address retrieval by probing the
clocks phandle under the mmc node in the device tree instead of probing
the clock manager node name in the device tree.
This will help to make the driver more scalable for more families as we
no
From: Alif Zakuan Yuslaimi
Add image loader used by the NAND SPL into the full Denali NAND
driver. This allows usage of the full Denali NAND driver in SPL instead
of the reduced SPL-only version.
Signed-off-by: Tien Fong Chee
Signed-off-by: Alif Zakuan Yuslaimi
---
drivers/mtd/nand/raw
From: Alif Zakuan Yuslaimi
Some drivers, like Denali NAND, depends on extensive NAND core
functionality that is not present in the minimal SPL configuration.
This patch series seeks to resolve this by implementing the existing image
loader from NAND SPL into Denali NAND driver subsystem, as
From: Alif Zakuan Yuslaimi
Add configuration option to compile the entire NAND framework into
U-Boot SPL. This is required by some drivers, like the Denali NAND,
which use a lot of functionality from the NAND core.
Signed-off-by: Marek Vasut
Signed-off-by: Tien Fong Chee
Signed-off-by: Alif
From: Alif Zakuan Yuslaimi
Update the MMC driver to retrieve the clock manager base address via
probing the clock manager node in the device tree.
Signed-off-by: Alif Zakuan Yuslaimi
---
drivers/mmc/socfpga_dw_mmc.c | 22 ++
1 file changed, 18 insertions(+), 4 deletions
From: Alif Zakuan Yuslaimi
Agilex5 FSBL is required to disable the power of unused peripheral SRAM
blocks to reduce power consumption.
Introducing a new power manager driver for Agilex5 which will be called
as part of Agilex5 SPL initialization process.
This driver will read the peripheral
From: Alif Zakuan Yuslaimi
Altera has separated from Intel as a standalone company.
Update CPU info printout naming from Intel to Altera.
Signed-off-by: Alif Zakuan Yuslaimi
---
arch/arm/mach-socfpga/misc_soc64.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm
From: Alif Zakuan Yuslaimi
Use GPIO hogging method in device tree to set SDIO_SEL pin (portb3)
direction as output with value 0 after power-on reset.
This is to ensure stable 0V voltage reading from SDIO_SEL GPIO pin
after board init.
Signed-off-by: Alif Zakuan Yuslaimi
---
arch/arm/dts
From: Tingting Meng
CONFIG_BLOBLIST_FIXED and CONFIG_BLOBLIST_ADDR options were
unintentionally removed during recent external updates to the defconfig.
This patch restores the missing entries to ensure proper board
functionality. No new features are introduced.
Fixes: d6a53f523afe ("spl: Add an
From: Tingting Meng
CONFIG_BLOBLIST_FIXED and CONFIG_BLOBLIST_ADDR options were
unintentionally removed during recent external updates to the defconfig.
This patch restores the missing entries to ensure proper board
functionality. No new features are introduced.
Fixes: d6a53f523afe ("spl: Add an
From: Alif Zakuan Yuslaimi
Enable Marvell Ethernet PHYs support for Agilex5 defconfig
Signed-off-by: Alif Zakuan Yuslaimi
---
configs/socfpga_agilex5_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/socfpga_agilex5_defconfig
b/configs/socfpga_agilex5_defconfig
index
From: Alif Zakuan Yuslaimi
Enable F2S bridge reset support for SoC64 families.
The F2S bridges are soc2fpga, lwhps2fpga, fpga2soc, f2sdram0, f2sdram1,
and f2sdram2.
F2SDRAM bridge is only available on Stratix10.
This patch set has been tested on Agilex 5 devkit with QSPI boot
(UBI/UBIFS
From: Alif Zakuan Yuslaimi
Enable reset support for FPGA2SDRAM bridge for Stratix10, as well as
FPGA2SoC and SoC2FPGA bridges for all SoC64 families.
Signed-off-by: Alif Zakuan Yuslaimi
---
arch/arm/mach-socfpga/reset_manager_s10.c | 236 ++
1 file changed, 198 insertions
From: Alif Zakuan Yuslaimi
Add reset manager registers in preparation for F2S bridge reset
support as well as the mask support to enable/disable the bridges.
Mask value:
BIT0: soc2fpga
BIT1: lwhps2fpga
BIT2: fpga2soc
These bridges are available only in Stratix10:
BIT3: f2sdram0
BIT4: f2sdram1
From: Alif Zakuan Yuslaimi
Send out "HPS_STAGE_NOTIFY" mailbox command to the
Secure Device Manager (SDM) in SPL to inform SDM on
FSBL execution.
This is necessary for the SDM to recognize that the
FSBL stage has begun its execution and should be
made as early as possible in the FS
From: Alif Zakuan Yuslaimi
Introduce a new mailbox command to notify the Secure Device Manager (SDM)
on the stage of HPS code execution.
Generally, there are three main code execution stages: First Stage Boot
Loader (FSBL) which is U-Boot SPL, Second Stage Boot Loader (SSBL) which
is U-Boot
From: Alif Zakuan Yuslaimi
Introducing a new mailbox command "HPS_STAGE_NOTIFY" to notify Secure
Device Manager (SDM) on the stage of HPS code execution.
Generally, there are three main code execution stages: First Stage Boot
Loader (FSBL) which is U-Boot SPL, Second Stage Boot Lo
From: Alif Zakuan Yuslaimi
The boot_scratch_cold register is generally used for passing
critical system info between SPL, U-Boot and Linux.
Documenting the usage of boot_scratch_cold8 and boot_scratch_cold9
sticky registers for capturing the Uncorrected Errors
(UE) and the UE Address. This is
From: Alif Zakuan Yuslaimi
Introduce a new symbol in the beginning of .data section in
the common ARMv8 linker script and use that as a reference
for data save and restore.
Previously, the code would rely on calculating the start of
the .data section address via data size, however, we observed
From: Alif Zakuan Yuslaimi
Some customers prefer to minimize the use of external oscillators,
especially when using the FPGA first configuration mode.
By enabling the configuration of the HPS internal oscillator as
the boot_clk source instead of the default external oscillator,
(HPS_OSC_CLK) in
From: Alif Zakuan Yuslaimi
Automatically start watchdog timer for Agilex5. This
configuration is enabled by default in the Kconfig,
hence removing this configuration from Agilex5 defconfig.
Signed-off-by: Alif Zakuan Yuslaimi
---
configs/socfpga_agilex5_defconfig | 1 -
1 file changed, 1
From: Tien Fong Chee
Enable XGMAC for SoCFPGA Agilex5 devkit.
Signed-off-by: Tien Fong Chee
---
configs/socfpga_agilex5_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/socfpga_agilex5_defconfig
b/configs/socfpga_agilex5_defconfig
index 97b00a82129..2b71ccac025 100644
---
From: Alif Zakuan Yuslaimi
Add the required configuration in the U-Boot env to enable Linux QSPI
boot with UBI / UBIFS.
Signed-off-by: Alif Zakuan Yuslaimi
Signed-off-by: Tien Fong Chee
---
configs/socfpga_agilex5_defconfig | 1 +
include/configs/socfpga_soc64_common.h | 6 ++
2
From: Tien Fong Chee
Add board_boot_order() to retrieve the list of boot devices from
spl-boot-order property in device tree. This board_boot_order()
would be used for all Intel SOC64 devices.
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/spl_soc64.c | 103 +++
From: Alif Zakuan Yuslaimi
Use default common ARMv8 linker script instead of a separate
SoC64 linker script
Signed-off-by: Alif Zakuan Yuslaimi
---
v1->v2
- Move to common ARMv8 linker script
---
configs/socfpga_agilex5_defconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/conf
From: Tingting Meng
Adding DDR driver support for Agilex5 series.
Signed-off-by: Tingting Meng
---
MAINTAINERS | 2 +
arch/arm/dts/socfpga_agilex5-u-boot.dtsi | 251 ++
arch/arm/dts/socfpga_agilex5.dtsi | 8 +
.../arm/dts/socfpga_agile
From: Tien Fong Chee
Add SPL support for Agilex5 SoCFPGA.
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/Makefile | 3 +
arch/arm/mach-socfpga/spl_agilex5.c | 89 +
2 files changed, 92 insertions(+)
create mode 100644 arch/arm/mach-socfpga/spl_agilex
From: Alif Zakuan Yuslaimi
As cache is enabled in U-Boot and disabled in ATF(BL31). We need to
perform cache flush of buffers that are shared between U-Boot and
ATF using secure monitor calls.
Signed-off-by: Mahesh Rao
Signed-off-by: Tien Fong Chee
Signed-off-by: Alif Zakuan Yuslaimi
From: Tien Fong Chee
Adding configuration for SPL malloc pool.
Signed-off-by: Tien Fong Chee
---
configs/socfpga_agilex5_defconfig | 4
1 file changed, 4 insertions(+)
diff --git a/configs/socfpga_agilex5_defconfig
b/configs/socfpga_agilex5_defconfig
index 60e625ea805..2a2c76113cd 10064
From: Alif Zakuan Yuslaimi
Board ID is exported as environment variable for use to boot Linux with FIT
configuration.
Signed-off-by: Alif Zakuan Yuslaimi
Signed-off-by: Tien Fong Chee
---
v1->v2
- use env_set_ulong() instead of env_set()
---
arch/arm/mach-socfpga/board.c |
From: Tien Fong Chee
Allow non-secure accesses only with SMMU peripherals. This would protect
the content in DDR secure region from accidentally modified by SMMU
peripherals.
Signed-off-by: Tien Fong Chee
---
arch/arm/dts/socfpga_agilex5-u-boot.dtsi | 34
arch/arm/mach
From: Alif Zakuan Yuslaimi
Update the print info per Agilex5
Signed-off-by: Tien Fong Chee
Signed-off-by: Alif Zakuan Yuslaimi
---
v1->v2
- Simplify printout logic writing
---
arch/arm/mach-socfpga/misc_soc64.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/
From: Tien Fong Chee
set/way instructions "dc cisw" which is used by the "dcache flush" command
only flushing CPU data caches from L1 -> L2 -> L3 to system memory cache in
cache coherency unit, hence this patch enables data flush from system
memory cache of CCU into DDR memory.
Signed-off-by: Ti
From: Alif Zakuan Yuslaimi
Enable PSCI reset driver for Agilex5 cold and warm reset
Signed-off-by: Alif Zakuan Yuslaimi
Signed-off-by: Tien Fong Chee
---
v1->v2
- Use common PSCI reset driver instead of implementing separate
reset driver for Agilex5
---
arch/arm/Kconfig | 1 +
1 f
From: Tien Fong Chee
These firewall configure settings are needed to disable firewall on
respective hardware component so both secure and non-secure transactions
are allowed.
Signed-off-by: Tien Fong Chee
---
arch/arm/dts/socfpga_agilex5-u-boot.dtsi | 166 +++
1 file change
From: Tien Fong Chee
Enable XGMAC for SoCFPGA Agilex5 devkit.
Signed-off-by: Tien Fong Chee
Link: https://lore.kernel.org/all/20241204064755.10226-2-mun.yew.t...@intel.com/
---
v1->v2
- include Linux lore link for Linux upstream progress
---
.../arm/dts/socfpga_agilex5_socdk-u-boot.dtsi | 34
From: Tien Fong Chee
These configuration settings are required to enable cache maintenance and
access between initiators and targets.
Signed-off-by: Tien Fong Chee
---
arch/arm/dts/socfpga_agilex5-u-boot.dtsi | 210 +++
1 file changed, 210 insertions(+)
diff --git a/arch/a
From: Tien Fong Chee
Agilex5 supports both HPS handoff data and DDR handoff data.
Existing HPS handoff functions are restructured to support both existing
devices and Agilex5 device.
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/Makefile | 1 +
arch/arm/mach-socfp
From: Alif Zakuan Yuslaimi
Status polling is used instead of using interrupt controller for Agilex5.
Disabling GICV3 in Agilex5 target, as well as disabling GICV2 enabled by
default for all SoCFPGA devices.
All the other SoCFPGA devices uses GICV2, thus enabling GICV2 in each of
the devices
From: Alif Zakuan Yuslaimi
PLL frequency would overshoot from the original target in
synchronous mode during low VCC voltage condition.
To resolve this issue, PLL is set to run on asynchronous mode
instead of enabling synchronous mode in the clock driver.
Signed-off-by: Muhammad Hazim Izzat
From: Alif Zakuan Yuslaimi
There are 5 L4 watchdogs and one SDM triggered warm reset bit
in Agilex5 reset manager "stat" register where bit 16:20 for L4
watchdogs. Assigning value 1 to these bits in the register address
will initiate SDM to trigger warm reset.
Introducing new warm
From: Alif Zakuan Yuslaimi
Replace cm_wait_for_fsm() function with wait_for_bit_le32() function
which supports accurate timeout.
Signed-off-by: Alif Zakuan Yuslaimi
Signed-off-by: Tien Fong Chee
---
drivers/clk/altera/clk-agilex5.c | 22 +-
1 file changed, 17 insertions
From: Alif Zakuan Yuslaimi
Agilex5 retrieves its clock manager address via probing its own clock
driver model during SPL initialization.
Therefore, excluding Agilex5 from calling generic clock driver in misc
driver.
Signed-off-by: Alif Zakuan Yuslaimi
---
v1->v2
- probe from DT for Agil
From: Tien Fong Chee
Initial creation of new system manager driver.
Add supports for the SOCFPGA System Manager Register block which
aggregates different peripheral function into one area.
On 64 bit ARM parts, the system manager only can be accessed during
EL3 mode, this driver model provide use
From: Alif Zakuan Yuslaimi
This patch set introduces boot support for the Altera SoCFPGA Agilex 5 platform
in U-Boot. The changes include:
1. Board-specific configurations and setup required to enable Agilex 5
operation in U-Boot.
2. Integration of cache coherency
From: Alif Zakuan Yuslaimi
Enable i2c3 node in Agilex5 device tree
Signed-off-by: Alif Zakuan Yuslaimi
---
arch/arm/dts/socfpga_agilex5_socdk.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/socfpga_agilex5_socdk.dts
b/arch/arm/dts/socfpga_agilex5_socdk.dts
index
From: Alif Zakuan Yuslaimi
The current write and notify SDM to read mechanism has a flaw where
SDM is not notified enough to be able to read all the data in the buffer.
This is caused by SDM doorbell will only be sent out once the command
buffer overflow check is satisfied. If the command
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